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Tue, 25 Aug 2026 21:18:48 +0000 (UTC) Received: from [127.0.1.1] (unknown [10.124.178.20]) by az2uksmom1.o.css.fujitsu.com (Postfix) with ESMTP id B7D8D1801127; Tue, 25 Aug 2026 21:18:43 +0000 (UTC) From: Itaru Kitayama Date: Wed, 26 Aug 2026 06:18:34 +0900 Subject: [PATCH 1/2] KVM: selftest: arm64: Support 5-level paging in stage 1 translation table Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260826-arm64-52bit-va-v1-1-14ec98211363@fujitsu.com> References: <20260826-arm64-52bit-va-v1-0-14ec98211363@fujitsu.com> In-Reply-To: <20260826-arm64-52bit-va-v1-0-14ec98211363@fujitsu.com> To: Marc Zyngier , Oliver Upton , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Paolo Bonzini , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Itaru Kitayama , Takayuki Okamoto X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787692718; l=7169; i=itaru.kitayama@fujitsu.com; s=20260825; h=from:subject:message-id; bh=j6Asuk1cnBvinvk3JEqecrbzglvqkmx5gA73gonKR8E=; b=6T4a5KAqdlBssANDbaEO8tnHAZpKT80qJ+CiRvnlccosN/JQ7RnXybQTuU1Lj3I1glKWbng5R v+ctyoyhppqDVTJrhBt32hdWL9u8NACxpgs82TvetXzsX5OahtXaLtn X-Developer-Key: i=itaru.kitayama@fujitsu.com; a=ed25519; pk=g9bTnr9giRP7JwNSZHy+OMLQZBEUtSE9tUnXso0hH1Y= Add p4d_index() for when 5-level paging required, i.e., V52 guest mode IDs. With the index helper function, _virt_pg_map() handles 5-level paging case, and aarch64_vcpu_setup() now is aware of the new V52 guest mode IDs. Signed-off-by: Itaru Kitayama Reviewed-by: Takayuki Okamoto --- .../selftests/kvm/include/arm64/processor.h | 2 + tools/testing/selftests/kvm/lib/arm64/processor.c | 87 ++++++++++++++++++= ++-- 2 files changed, 84 insertions(+), 5 deletions(-) diff --git a/tools/testing/selftests/kvm/include/arm64/processor.h b/tools/= testing/selftests/kvm/include/arm64/processor.h index b8a902ba8573..a6fd7a9b379e 100644 --- a/tools/testing/selftests/kvm/include/arm64/processor.h +++ b/tools/testing/selftests/kvm/include/arm64/processor.h @@ -113,6 +113,7 @@ =20 #define PTE_VALID BIT(0) #define PGD_TYPE_TABLE BIT(1) +#define P4D_TYPE_TABLE BIT(1) #define PUD_TYPE_TABLE BIT(1) #define PMD_TYPE_TABLE BIT(1) #define PTE_TYPE_PAGE BIT(1) @@ -167,6 +168,7 @@ enum { (v) =3D=3D VECTOR_SYNC_LOWER_64 || \ (v) =3D=3D VECTOR_SYNC_LOWER_32) =20 +u32 aarch64_get_supported_va_size(void); void aarch64_get_supported_page_sizes(u32 ipa, u32 *ipa4k, u32 *ipa16k, u32 *ipa64k); =20 diff --git a/tools/testing/selftests/kvm/lib/arm64/processor.c b/tools/test= ing/selftests/kvm/lib/arm64/processor.c index 01325bf4d36f..9108e14a9b5b 100644 --- a/tools/testing/selftests/kvm/lib/arm64/processor.c +++ b/tools/testing/selftests/kvm/lib/arm64/processor.c @@ -29,13 +29,25 @@ static u64 pgd_index(struct kvm_vm *vm, gva_t gva) return (gva >> shift) & mask; } =20 +static u64 p4d_index(struct kvm_vm *vm, gva_t gva) +{ + unsigned int shift =3D 3 * (vm->page_shift - 3) + vm->page_shift; + u64 mask =3D (1UL << (vm->page_shift - 3)) - 1; + + TEST_ASSERT(vm->mmu.pgtable_levels =3D=3D 5, + "Mode %d does not have 5 page table levels", vm->mode); + + return (gva >> shift) & mask; +} + static u64 pud_index(struct kvm_vm *vm, gva_t gva) { unsigned int shift =3D 2 * (vm->page_shift - 3) + vm->page_shift; u64 mask =3D (1UL << (vm->page_shift - 3)) - 1; =20 - TEST_ASSERT(vm->mmu.pgtable_levels =3D=3D 4, - "Mode %d does not have 4 page table levels", vm->mode); + TEST_ASSERT(vm->mmu.pgtable_levels >=3D 4, + "Mode %d does not have at least 4 page table levels", + vm->mode); =20 return (gva >> shift) & mask; } @@ -147,6 +159,12 @@ static void _virt_pg_map(struct kvm_vm *vm, gva_t gva,= gpa_t gpa, PGD_TYPE_TABLE | PTE_VALID); =20 switch (vm->mmu.pgtable_levels) { + case 5: + ptep =3D addr_gpa2hva(vm, pte_addr(vm, *ptep)) + p4d_index(vm, gva) * 8; + if (!*ptep) + *ptep =3D addr_pte(vm, vm_alloc_page_table(vm), + P4D_TYPE_TABLE | PTE_VALID); + /* fall through */ case 4: ptep =3D addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pud_index(vm, gva) * 8; if (!*ptep) @@ -163,7 +181,7 @@ static void _virt_pg_map(struct kvm_vm *vm, gva_t gva, = gpa_t gpa, ptep =3D addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pte_index(vm, gva) * 8; break; default: - TEST_FAIL("Page table levels must be 2, 3, or 4"); + TEST_FAIL("Page table levels must be 2, 3, 4, or 5"); } =20 pg_attr =3D PTE_AF | PTE_ATTRINDX(attr_idx) | PTE_TYPE_PAGE | PTE_VALID; @@ -182,18 +200,35 @@ void virt_arch_pg_map(struct kvm_vm *vm, gva_t gva, g= pa_t gpa) =20 u64 *virt_get_pte_hva_at_level(struct kvm_vm *vm, gva_t gva, int level) { + int start_level =3D 4 - vm->mmu.pgtable_levels; u64 *ptep; =20 + TEST_ASSERT(level >=3D start_level && level <=3D 3, + "Invalid translation level %d, valid range is %d-3", + level, start_level); + if (!vm->mmu.pgd_created) goto unmapped_gva; =20 ptep =3D addr_gpa2hva(vm, vm->mmu.pgd) + pgd_index(vm, gva) * 8; if (!ptep) goto unmapped_gva; - if (level =3D=3D 0) + /* + * Stage-1 translation starts at level -1 for a five-level page + * table, and at levels 0, 1, or 2 for four-, three-, or two-level + * page tables, respectively. + */ + if (level =3D=3D start_level) return ptep; =20 switch (vm->mmu.pgtable_levels) { + case 5: + ptep =3D addr_gpa2hva(vm, pte_addr(vm, *ptep)) + p4d_index(vm, gva) * 8; + if (!ptep) + goto unmapped_gva; + if (level =3D=3D 0) + break; + /* fall through */ case 4: ptep =3D addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pud_index(vm, gva) * 8; if (!ptep) @@ -214,7 +249,7 @@ u64 *virt_get_pte_hva_at_level(struct kvm_vm *vm, gva_t= gva, int level) goto unmapped_gva; break; default: - TEST_FAIL("Page table levels must be 2, 3, or 4"); + TEST_FAIL("Page table levels must be 2, 3, 4, or 5"); } =20 return ptep; @@ -321,12 +356,14 @@ void aarch64_vcpu_setup(struct kvm_vcpu *vcpu, struct= kvm_vcpu_init *init) case VM_MODE_PXXVYY_4K: TEST_FAIL("AArch64 does not support 4K sized pages " "with ANY-bit physical address ranges"); + case VM_MODE_P52V52_64K: case VM_MODE_P52V48_64K: case VM_MODE_P48V48_64K: case VM_MODE_P40V48_64K: case VM_MODE_P36V48_64K: tcr_el1 |=3D TCR_TG0_64K; break; + case VM_MODE_P52V52_16K: case VM_MODE_P52V48_16K: case VM_MODE_P48V48_16K: case VM_MODE_P40V48_16K: @@ -334,6 +371,7 @@ void aarch64_vcpu_setup(struct kvm_vcpu *vcpu, struct k= vm_vcpu_init *init) case VM_MODE_P36V47_16K: tcr_el1 |=3D TCR_TG0_16K; break; + case VM_MODE_P52V52_4K: case VM_MODE_P52V48_4K: case VM_MODE_P48V48_4K: case VM_MODE_P40V48_4K: @@ -348,6 +386,9 @@ void aarch64_vcpu_setup(struct kvm_vcpu *vcpu, struct k= vm_vcpu_init *init) =20 /* Configure output size */ switch (vm->mode) { + case VM_MODE_P52V52_4K: + case VM_MODE_P52V52_16K: + case VM_MODE_P52V52_64K: case VM_MODE_P52V48_4K: case VM_MODE_P52V48_16K: case VM_MODE_P52V48_64K: @@ -578,6 +619,42 @@ static u32 max_ipa_for_page_size(u32 vm_ipa, u32 gran, return min(vm_ipa, 48U); } =20 +u32 aarch64_get_supported_va_size(void) +{ + struct kvm_vcpu_init preferred_init =3D {}; + int kvm_fd, vm_fd, vcpu_fd, err; + u64 val; + u32 va_range; + struct kvm_one_reg reg =3D { + .id =3D KVM_ARM64_SYS_REG(SYS_ID_AA64MMFR2_EL1), + .addr =3D (u64)&val, + }; + + kvm_fd =3D open_kvm_dev_path_or_exit(); + vm_fd =3D __kvm_ioctl(kvm_fd, KVM_CREATE_VM, NULL); + TEST_ASSERT(vm_fd >=3D 0, KVM_IOCTL_ERROR(KVM_CREATE_VM, vm_fd)); + + vcpu_fd =3D ioctl(vm_fd, KVM_CREATE_VCPU, 0); + TEST_ASSERT(vcpu_fd >=3D 0, KVM_IOCTL_ERROR(KVM_CREATE_VCPU, vcpu_fd)); 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Tue, 25 Aug 2026 21:18:47 +0000 (UTC) From: Itaru Kitayama Date: Wed, 26 Aug 2026 06:18:35 +0900 Subject: [PATCH 2/2] KVM: selftests: arm64: Add 52-bit VA guest modes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260826-arm64-52bit-va-v1-2-14ec98211363@fujitsu.com> References: <20260826-arm64-52bit-va-v1-0-14ec98211363@fujitsu.com> In-Reply-To: <20260826-arm64-52bit-va-v1-0-14ec98211363@fujitsu.com> To: Marc Zyngier , Oliver Upton , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Paolo Bonzini , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Itaru Kitayama , Takayuki Okamoto X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787692718; l=4987; i=itaru.kitayama@fujitsu.com; s=20260825; h=from:subject:message-id; bh=70JDFubTVkBsDgJS+Q5x0sY6ZqnQo0abv+xo6mjXvqY=; b=ZHsdORZZInAmcydx9m1zTcNgmLZVUmMpigF0GjTpwFoRUApwYAlxNWL1Iyxbgd3+bkTV5CIKA TM139YCgkS+Dh7GS1EiU69FwFgnlB+Z4dMFUe3eAH5TfkH6jDxrt9oy X-Developer-Key: i=itaru.kitayama@fujitsu.com; a=ed25519; pk=g9bTnr9giRP7JwNSZHy+OMLQZBEUtSE9tUnXso0hH1Y= Add P52V52 guest mode IDs for the 4K, 16K and 64K translation granules, along with their mode descriptions and parameters. Advertise the 4KB and 16KB modes when the corresponding granule supports a 52-bit IPA, implying FEAT_LPA2 support. For the 64K mode, also require 52-bit VA support. This makes the 52-bit VA configurations available to KVM selftests now that the arm64 page-table code supports 5-level stage-1 translation. Signed-off-by: Itaru Kitayama Reviewed-by: Takayuki Okamoto --- tools/testing/selftests/kvm/include/kvm_util.h | 3 +++ tools/testing/selftests/kvm/lib/arm64/processor.c | 2 +- tools/testing/selftests/kvm/lib/guest_modes.c | 5 +++++ tools/testing/selftests/kvm/lib/kvm_util.c | 11 +++++++++++ 4 files changed, 20 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/include/kvm_util.h b/tools/testing= /selftests/kvm/include/kvm_util.h index 04a910164a29..9040281c0992 100644 --- a/tools/testing/selftests/kvm/include/kvm_util.h +++ b/tools/testing/selftests/kvm/include/kvm_util.h @@ -184,6 +184,9 @@ enum vm_guest_mode { VM_MODE_P52V48_4K, VM_MODE_P52V48_16K, VM_MODE_P52V48_64K, + VM_MODE_P52V52_4K, + VM_MODE_P52V52_16K, + VM_MODE_P52V52_64K, VM_MODE_P48V48_4K, VM_MODE_P48V48_16K, VM_MODE_P48V48_64K, diff --git a/tools/testing/selftests/kvm/lib/arm64/processor.c b/tools/test= ing/selftests/kvm/lib/arm64/processor.c index 9108e14a9b5b..bcdf670c9eb8 100644 --- a/tools/testing/selftests/kvm/lib/arm64/processor.c +++ b/tools/testing/selftests/kvm/lib/arm64/processor.c @@ -46,7 +46,7 @@ static u64 pud_index(struct kvm_vm *vm, gva_t gva) u64 mask =3D (1UL << (vm->page_shift - 3)) - 1; =20 TEST_ASSERT(vm->mmu.pgtable_levels >=3D 4, - "Mode %d does not have at least 4 page table levels", + "Mode %d does not have >=3D 4 page table levels", vm->mode); =20 return (gva >> shift) & mask; diff --git a/tools/testing/selftests/kvm/lib/guest_modes.c b/tools/testing/= selftests/kvm/lib/guest_modes.c index 7a96c43b5704..4f121e2987e9 100644 --- a/tools/testing/selftests/kvm/lib/guest_modes.c +++ b/tools/testing/selftests/kvm/lib/guest_modes.c @@ -21,10 +21,15 @@ void guest_modes_append_default(void) { unsigned int limit =3D kvm_check_cap(KVM_CAP_ARM_VM_IPA_SIZE); u32 ipa4k, ipa16k, ipa64k; + u32 va; int i; =20 aarch64_get_supported_page_sizes(limit, &ipa4k, &ipa16k, &ipa64k); + va =3D aarch64_get_supported_va_size(); =20 + guest_mode_append(VM_MODE_P52V52_4K, ipa4k >=3D 52); + guest_mode_append(VM_MODE_P52V52_16K, ipa16k >=3D 52); + guest_mode_append(VM_MODE_P52V52_64K, ipa64k >=3D 52 && va >=3D 52); guest_mode_append(VM_MODE_P52V48_4K, ipa4k >=3D 52); guest_mode_append(VM_MODE_P52V48_16K, ipa16k >=3D 52); guest_mode_append(VM_MODE_P52V48_64K, ipa64k >=3D 52); diff --git a/tools/testing/selftests/kvm/lib/kvm_util.c b/tools/testing/sel= ftests/kvm/lib/kvm_util.c index 195f3fdae1e3..3fbc5b0d75ff 100644 --- a/tools/testing/selftests/kvm/lib/kvm_util.c +++ b/tools/testing/selftests/kvm/lib/kvm_util.c @@ -195,6 +195,9 @@ const char *vm_guest_mode_string(u32 i) [VM_MODE_P52V48_4K] =3D "PA-bits:52, VA-bits:48, 4K pages", [VM_MODE_P52V48_16K] =3D "PA-bits:52, VA-bits:48, 16K pages", [VM_MODE_P52V48_64K] =3D "PA-bits:52, VA-bits:48, 64K pages", + [VM_MODE_P52V52_4K] =3D "PA-bits:52, VA-bits:52, 4K pages", + [VM_MODE_P52V52_16K] =3D "PA-bits:52, VA-bits:52, 16K pages", + [VM_MODE_P52V52_64K] =3D "PA-bits:52, VA-bits:52, 64K pages", [VM_MODE_P48V48_4K] =3D "PA-bits:48, VA-bits:48, 4K pages", [VM_MODE_P48V48_16K] =3D "PA-bits:48, VA-bits:48, 16K pages", [VM_MODE_P48V48_64K] =3D "PA-bits:48, VA-bits:48, 64K pages", @@ -231,6 +234,9 @@ const struct vm_guest_mode_params vm_guest_mode_params[= ] =3D { [VM_MODE_P52V48_4K] =3D { 52, 48, 0x1000, 12 }, [VM_MODE_P52V48_16K] =3D { 52, 48, 0x4000, 14 }, [VM_MODE_P52V48_64K] =3D { 52, 48, 0x10000, 16 }, + [VM_MODE_P52V52_4K] =3D { 52, 52, 0x1000, 12 }, + [VM_MODE_P52V52_16K] =3D { 52, 52, 0x4000, 14 }, + [VM_MODE_P52V52_64K] =3D { 52, 52, 0x10000, 16 }, [VM_MODE_P48V48_4K] =3D { 48, 48, 0x1000, 12 }, [VM_MODE_P48V48_16K] =3D { 48, 48, 0x4000, 14 }, [VM_MODE_P48V48_64K] =3D { 48, 48, 0x10000, 16 }, @@ -298,10 +304,14 @@ struct kvm_vm *____vm_create(struct vm_shape shape) =20 /* Setup mode specific traits. */ switch (vm->mode) { + case VM_MODE_P52V52_4K: + vm->mmu.pgtable_levels =3D 5; + break; case VM_MODE_P52V48_4K: vm->mmu.pgtable_levels =3D 4; break; case VM_MODE_P52V48_64K: + case VM_MODE_P52V52_64K: vm->mmu.pgtable_levels =3D 3; break; case VM_MODE_P48V48_4K: @@ -322,6 +332,7 @@ struct kvm_vm *____vm_create(struct vm_shape shape) case VM_MODE_P48V48_16K: case VM_MODE_P40V48_16K: case VM_MODE_P36V48_16K: + case VM_MODE_P52V52_16K: vm->mmu.pgtable_levels =3D 4; break; case VM_MODE_P47V47_16K: --=20 2.43.0