From nobody Mon Sep 28 05:42:43 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62AAA1FBC8C; Tue, 25 Aug 2026 18:15:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787681737; cv=none; b=RNsSyyw+4bxO3aa9WM2nCPHvM0/Mm1IObmwinaCFwE8ZTEwXX2QU1d5FL0U/AM5EkeFQAoT5/6wwtkLqa9fhbUoG6KGu/bRL4tkGwwlLFyhvglZKBtOaDK7NzQqedUapcacqh41q1zcYW5iOrW6hqxFtquVqGqACtMHy6BcH4Wc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787681737; c=relaxed/simple; bh=C4Hw0dpWxnLm2zqjWobf/Gjv3zcKQWi2XEYwTIGVV98=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZdpOVMHZRUwrsbFmVoQ7YxEdVu8QZME6KRkAeC8rMLQvam908TISLkm6246X9guomIlm9Ozb7b/xxG7BZdM9Ct/MFfoiqRE2sXMpvA28KKCQvOuuCTUOsobAO43XL0zxSBUFR71UL4lbYZbRGtvjLEo7Uv6rhiEN9/ngVOwSADg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=N7aZnNIF; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="N7aZnNIF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1787681735; x=1819217735; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=C4Hw0dpWxnLm2zqjWobf/Gjv3zcKQWi2XEYwTIGVV98=; b=N7aZnNIFbYH72dGismo79mcd3a+y1VdB1YpDHDDrBQWeuM5E3rs0O8GO 3ghdSL2sIJQYxLsbHUNAi61anwfIa+KREg/40S7bIvNIUKYhHDBNswPvN NiVSudgIb4m8AkvH3iA4kQ0cf0E8cN/0R3VByIYKfWvyYgTB+5LV4p4YG P3ts/nXoCetL53G2KEosYQb252cQ9g4Q6Vt3jJ6VuGdSMNSpNSWc/XiTh KqAgKD8S/FyKNdofsJ2KZ8WMMOSBUy2hfX4FkZzaLbICEk9KuD/x8SA+V ACxjcm5c/GrOocf1N70lojZhweJk2jPRPJOgcqCUhgDB3kdtd4hfKCmVA w==; X-CSE-ConnectionGUID: ViEooYxxTnCHMp16KzoVJw== X-CSE-MsgGUID: 8s1Hl23yTj67xKwF0EZPlw== X-IronPort-AV: E=McAfee;i="6800,10657,11886"; a="88174201" X-IronPort-AV: E=Sophos;i="6.25,243,1779174000"; d="scan'208";a="88174201" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2026 11:15:33 -0700 X-CSE-ConnectionGUID: ZTMJkrCzT8agKRfoAVrQSg== X-CSE-MsgGUID: 97HmDp8mRvyALdPrknG9GQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,243,1779174000"; d="scan'208";a="265559594" Received: from aschofie-mobl2.amr.corp.intel.com (HELO agluck-desk3.home.arpa) ([10.124.222.141]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2026 11:15:33 -0700 From: Tony Luck To: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Hans de Goede Cc: Borislav Petkov , Breno Leitao , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Qiuxu Zhuo , Tony Luck Subject: [PATCH 1/7] cacheinfo: Export get_cpu_cacheinfo_id() for loadable modules Date: Tue, 25 Aug 2026 11:15:20 -0700 Message-ID: <20260825181526.13203-2-tony.luck@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260825181526.13203-1-tony.luck@intel.com> References: <20260825181526.13203-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Qiuxu Zhuo Loadable drivers that track bitfix filter state need the cache ID to distinguish shared cache instances. Without access to the cache ID, CPUs sharing the same cache cannot be associated with the same tracking state. The existing helper cannot be used by loadable modules because it depends on a non-exported symbol, preventing the such drivers from building as a module. Export get_cpu_cacheinfo_id() so loadable modules can retrieve cache IDs through a common cacheinfo interface. Signed-off-by: Qiuxu Zhuo Signed-off-by: Tony Luck --- include/linux/cacheinfo.h | 12 +----------- drivers/base/cacheinfo.c | 17 +++++++++++++++++ 2 files changed, 18 insertions(+), 11 deletions(-) diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h index fc879ac4cc4f..56fa646df0d1 100644 --- a/include/linux/cacheinfo.h +++ b/include/linux/cacheinfo.h @@ -82,6 +82,7 @@ struct cpu_cacheinfo { }; =20 struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu); +int get_cpu_cacheinfo_id(int cpu, int level); int early_cache_level(unsigned int cpu); int init_cache_level(unsigned int cpu); int init_of_cache_level(unsigned int cpu); @@ -137,17 +138,6 @@ static inline struct cacheinfo *get_cpu_cacheinfo_leve= l(int cpu, int level) return NULL; } =20 -/* - * Get the id of the cache associated with @cpu at level @level. - * cpuhp lock must be held. - */ -static inline int get_cpu_cacheinfo_id(int cpu, int level) -{ - struct cacheinfo *ci =3D get_cpu_cacheinfo_level(cpu, level); - - return ci ? ci->id : -1; -} - #if defined(CONFIG_ARM64) || defined(CONFIG_ARM) #define use_arch_cache_info() (true) #else diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index 70701d3bc81c..28d193bf6064 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -38,6 +38,23 @@ struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu) return ci_cacheinfo(cpu); } =20 +/** + * get_cpu_cacheinfo_id - Return the cache ID for a CPU and cache level + * @cpu: CPU number + * @level: Cache level + * + * The caller must hold the cpuhp lock. + * + * Return: Cache ID on success, or -1 if no matching cache exists. + */ +int get_cpu_cacheinfo_id(int cpu, int level) +{ + struct cacheinfo *ci =3D get_cpu_cacheinfo_level(cpu, level); + + return ci ? ci->id : -1; +} +EXPORT_SYMBOL_GPL(get_cpu_cacheinfo_id); + static inline bool cache_leaves_are_shared(struct cacheinfo *this_leaf, struct cacheinfo *sib_leaf) { --=20 2.55.0 From nobody Mon Sep 28 05:42:43 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AACB23EAAA; Tue, 25 Aug 2026 18:15:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787681738; cv=none; b=R37t43HVlEnpw6X3JAFoR344d7KdoJa8Wm2Ute8Dh8HZtKRMrtSEObEmMxFtKuo7R3cDbk9tZZsexaVTGy0TY60l616nA9nqobtL6WPqlnbuz6WW/sbg6Lc57p03CrMM547DAZDJh+nOZmBWFNAXntozVj15XoddvrjzxXU1l7E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787681738; c=relaxed/simple; bh=HpXSFglQBwpdFwyc3DEg6LqxExJmQQCYCkTKib1d9Aw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=s5jRtAwdg06EG0rzOUW89rwK/HlQCaU1trExasFTcTbSOyjQhDNJolrneIOsvAjpa/Tn1z7xne7v2THE9RDkgv8FPjuM2dOueRFdBxvicRJBwcReKYqrim1G74rL20g2S8QQOtv1ecZ+SqMjZYxjwioaNSTPFhE4TtSSfFo6xaY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Uzf2SCon; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Uzf2SCon" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1787681736; x=1819217736; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HpXSFglQBwpdFwyc3DEg6LqxExJmQQCYCkTKib1d9Aw=; b=Uzf2SConFzvh43StwN9t0q14ef0uj3Q0Em0a/VdpVQleq32F2kWUfFkp kWrhSVx9XcDUriaiEPYHMebn7Gh38JByk2LNwRAEc1aC6hu8hBaZ7jweZ 2O8SNm3x8g9SYYUuqLOBLdM2UummKulemrI3PXu8pn+URzcs4cmNiEAvW /zBa0TnKOvGXnoITHRWzBpkHI8l0XRJNqpbF373xEGth6w3b+GD1Pchbk AGLzebmp4D99Lz1ElhsIh0w7qvf965FoOLX+BrEsWs0siFG47I06pPBpS 5wZT2WLFuOBTXVIyzed14Ac78uIOKQ+tHDlM/5sxcyst8Mx8Y6bYZs7f6 g==; X-CSE-ConnectionGUID: LLqwP6UCSB2KmQiunLfsDw== X-CSE-MsgGUID: eX7zEROXRgm2AaRsbYVr/w== X-IronPort-AV: E=McAfee;i="6800,10657,11886"; a="88174206" X-IronPort-AV: E=Sophos;i="6.25,243,1779174000"; d="scan'208";a="88174206" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2026 11:15:34 -0700 X-CSE-ConnectionGUID: j6tLA+LfSlyXS21Zo2B6PA== X-CSE-MsgGUID: kOwfoDxQQS6AoEaIUWoJuQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,243,1779174000"; d="scan'208";a="265559598" Received: from aschofie-mobl2.amr.corp.intel.com (HELO agluck-desk3.home.arpa) ([10.124.222.141]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2026 11:15:33 -0700 From: Tony Luck To: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Hans de Goede Cc: Borislav Petkov , Breno Leitao , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck , Qiuxu Zhuo Subject: [PATCH 2/7] x86/mce: Enumeration updates for Intel bitfix filter reset Date: Tue, 25 Aug 2026 11:15:21 -0700 Message-ID: <20260825181526.13203-3-tony.luck@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260825181526.13203-1-tony.luck@intel.com> References: <20260825181526.13203-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" IA32_CORE_CAPABILITIES enumerates the bitfix filter reset feature. Also add definitions for the threshold status field in the machine check status registers. Co-developed-by: Qiuxu Zhuo Signed-off-by: Qiuxu Zhuo Signed-off-by: Tony Luck --- arch/x86/include/asm/mce.h | 6 ++++++ arch/x86/include/asm/msr-index.h | 2 ++ 2 files changed, 8 insertions(+) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index e575b702063d..0d5bcb6f1750 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -13,6 +13,7 @@ #define MCG_CTL_P BIT_ULL(8) /* MCG_CTL register available */ #define MCG_EXT_P BIT_ULL(9) /* Extended registers available */ #define MCG_CMCI_P BIT_ULL(10) /* CMCI supported */ +#define MCG_TES_P BIT_ULL(11) /* Threshold-based error status supported = */ #define MCG_SEAM_NR BIT_ULL(12) /* MCG_STATUS_SEAM_NR supported */ #define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */ #define MCG_EXT_CNT_SHIFT 16 @@ -41,6 +42,11 @@ #define MCI_STATUS_PCC BIT_ULL(57) /* processor context corrupt */ #define MCI_STATUS_S BIT_ULL(56) /* Signaled machine check */ #define MCI_STATUS_AR BIT_ULL(55) /* Action required */ +#define MCI_STATUS_TES_SHIFT 53 /* Threshold-based error status = */ +#define MCI_STATUS_TES_MASK GENMASK_ULL(54, 53) +#define MCI_STATUS_TES(s) (((s) & MCI_STATUS_TES_MASK) >> MCI_STATUS_TES_S= HIFT) +#define MCI_STATUS_TES_GREEN 1 /* Threshold-based errors below thres= hold */ +#define MCI_STATUS_TES_YELLOW 2 /* Threshold-based errors above thre= shold */ #define MCI_STATUS_CEC_SHIFT 38 /* Corrected Error Count */ #define MCI_STATUS_CEC_MASK GENMASK_ULL(52,38) #define MCI_STATUS_CEC(c) (((c) & MCI_STATUS_CEC_MASK) >> MCI_STATUS_CEC_S= HIFT) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 18c4be75e927..13d3efc87b14 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -114,6 +114,8 @@ #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS BIT(MSR_IA32_CORE_CAPS_INTEGRI= TY_CAPS_BIT) #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5 #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLI= T_LOCK_DETECT_BIT) +#define MSR_IA32_CORE_CAPS_BFF_RESET_DETECT_BIT 9 +#define MSR_IA32_CORE_CAPS_BFF_RESET_DETECT BIT(MSR_IA32_CORE_CAPS_BFF_R= ESET_DETECT_BIT) =20 #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 #define NHM_C3_AUTO_DEMOTE (1UL << 25) --=20 2.55.0 From nobody Mon Sep 28 05:42:43 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D009326AC5; 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a="88174211" X-IronPort-AV: E=Sophos;i="6.25,243,1779174000"; d="scan'208";a="88174211" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2026 11:15:34 -0700 X-CSE-ConnectionGUID: O8RDDvbzRzmwUn5PrwoCIw== X-CSE-MsgGUID: pcdRHad8Sy+I+cP0WGIprg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,243,1779174000"; d="scan'208";a="265559602" Received: from aschofie-mobl2.amr.corp.intel.com (HELO agluck-desk3.home.arpa) ([10.124.222.141]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2026 11:15:34 -0700 From: Tony Luck To: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Hans de Goede Cc: Borislav Petkov , Breno Leitao , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck , Qiuxu Zhuo Subject: [PATCH 3/7] platform/x86/intel/bff: Add stub Intel bitfix filter driver Date: Tue, 25 Aug 2026 11:15:22 -0700 Message-ID: <20260825181526.13203-4-tony.luck@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260825181526.13203-1-tony.luck@intel.com> References: <20260825181526.13203-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Check if platform supports enhanced cache error reporting and the bitfix filter reset feature. Co-developed-by: Qiuxu Zhuo Signed-off-by: Qiuxu Zhuo Signed-off-by: Tony Luck --- drivers/platform/x86/intel/bff.c | 59 +++++++++++++++++++++++++++++ drivers/platform/x86/intel/Kconfig | 13 +++++++ drivers/platform/x86/intel/Makefile | 1 + 3 files changed, 73 insertions(+) create mode 100644 drivers/platform/x86/intel/bff.c diff --git a/drivers/platform/x86/intel/bff.c b/drivers/platform/x86/intel/= bff.c new file mode 100644 index 000000000000..9522bdb1401d --- /dev/null +++ b/drivers/platform/x86/intel/bff.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright(c) 2026 Intel Corporation. */ + +/* + * Intel driver to reset bitfix filters when they overflow. + * + * Each bitfix filter has limited slots to track corrected errors. + * These slots can be filled by transient corrected errors (e.g., + * bit flips from particle strikes) that don't represent permanent + * hardware defects. + * + * When the filter overflows (yellow status), reset it to reclaim + * slots occupied by transient corrected errors. If the overflow + * repeats frequently after reset, it indicates persistent hardware + * defects that need attention: the system should be scheduled for + * servicing. + */ +#define pr_fmt(fmt) "bff: " fmt + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +static int __init bff_init(void) +{ + u64 core_caps, mcg_cap; + + if (!cpu_feature_enabled(X86_FEATURE_MCA)) + return -ENODEV; + rdmsrq(MSR_IA32_MCG_CAP, mcg_cap); + if (!(mcg_cap & MCG_TES_P)) + return -ENODEV; + + if (!cpu_feature_enabled(X86_FEATURE_CORE_CAPABILITIES)) + return -ENODEV; + + rdmsrq(MSR_IA32_CORE_CAPS, core_caps); + if (!(core_caps & MSR_IA32_CORE_CAPS_BFF_RESET_DETECT)) + return -ENODEV; + + return 0; +} + +static void __exit bff_exit(void) +{ +} + +module_init(bff_init); +module_exit(bff_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Intel bitfix filter reset driver"); diff --git a/drivers/platform/x86/intel/Kconfig b/drivers/platform/x86/inte= l/Kconfig index 2900407d6095..f4e9af0116ee 100644 --- a/drivers/platform/x86/intel/Kconfig +++ b/drivers/platform/x86/intel/Kconfig @@ -251,3 +251,16 @@ config INTEL_VSEC =20 To compile this driver as a module, choose M here: the module will be called intel_vsec. + +config INTEL_BFF_RESET + tristate "Intel bitfix filter reset driver" + depends on CPU_SUP_INTEL && X86_MCE + help + Adds support for Intel systems that implement bitfix filters to + suppress repeated logging and signaling of the same corrected + error. Those filters can become clogged with transient errors + over time. Clearing the filter may make space for additional + hard errors. + + To compile this driver as a module, choose M here: the module will + be called intel_bff. diff --git a/drivers/platform/x86/intel/Makefile b/drivers/platform/x86/int= el/Makefile index 138b13756158..dc4e374758d5 100644 --- a/drivers/platform/x86/intel/Makefile +++ b/drivers/platform/x86/intel/Makefile @@ -27,6 +27,7 @@ intel-target-$(CONFIG_INTEL_ISHTP_ECLITE) +=3D ishtp_ecli= te.o intel-target-$(CONFIG_INTEL_OAKTRAIL) +=3D oaktrail.o intel-target-$(CONFIG_INTEL_SDSI) +=3D sdsi.o intel-target-$(CONFIG_INTEL_VSEC) +=3D vsec.o +intel-target-$(CONFIG_INTEL_BFF_RESET) +=3D bff.o =20 # Intel PMIC / PMC / P-Unit drivers intel-target-$(CONFIG_INTEL_BYTCRC_PWRSRC) +=3D bytcrc_pwrsrc.o --=20 2.55.0 From nobody Mon Sep 28 05:42:43 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE24723ABBF; Tue, 25 Aug 2026 18:15:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787681739; cv=none; b=pGOSISyZ9DGOUl5SJ6jr4Aa+PbY4Uv1+zdWx9iaXdc+uiqc6dlxGFsZNMrkVDodPLNn3l18/8R0najOlSvtp9l33LcEryezbWcIfDYsM6yepdwFDHj59slv9mWa2qMwWT+l07O+N8JNcmzCpaWSUu17PtH7U4UIilrBSNpWKlhI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787681739; c=relaxed/simple; bh=+cdNIaAabyorKn/HrwhM9Ndub9E+MnRccu4cl/hmMCM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sDAf2lthBueuIRlda4Zcf/Uo9FBdTj1w2V7F4evBQlhDeepVtO060e3MHmUBQcerYZhbL7+HF72660h3W5sosZTXElXK9f6lZowRfKzIFFABuY0//Y2LUvAjWGlmpdRPUo21146ccI1/ZVdb55LXZxkzjyn3QCzRM0zf7+IpdpM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=iLSLVwed; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="iLSLVwed" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1787681737; x=1819217737; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+cdNIaAabyorKn/HrwhM9Ndub9E+MnRccu4cl/hmMCM=; b=iLSLVwed6jf7/AAVU+lNwwSuDBMMjDlx4Oxlns9PVraiNQUU86wiMOWy A8xfkVwSNDEfW48LsI+8KnBwqhxlvozqOjcOe05VOCCaG3Zm74c17CzkN TVGVbVjPn8Rs7ETLv3qFRUENZsV9CbKj4qlBWiax1cQ2zE4G2tTvLvxkW nz2pyOdbYVA7iXDQijCtPQaDkyTqjm8bmCcF2ZTNypQq9XhaoYhHUJsJT yjKEUsxYEDdh2WEYBzrIOQX5ZTMzm+abieeSOlUN3t1fEoB5ta3SmOYgl OI2GlLvBq9BVFIRm5ZHgwC6xl7gjCVLOS6hDMQHULtcyooOPH9pQPL6j/ g==; X-CSE-ConnectionGUID: JUmmEfriToWdUgOsQ4lwCA== X-CSE-MsgGUID: vLANiyO+QiKPrvLPimZ7AQ== X-IronPort-AV: E=McAfee;i="6800,10657,11886"; a="88174216" X-IronPort-AV: E=Sophos;i="6.25,243,1779174000"; d="scan'208";a="88174216" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2026 11:15:34 -0700 X-CSE-ConnectionGUID: sO0dtylRQkqW7ORIW42BOQ== X-CSE-MsgGUID: 9lbD1c29TG2JBe8pzQUYpQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,243,1779174000"; d="scan'208";a="265559605" Received: from aschofie-mobl2.amr.corp.intel.com (HELO agluck-desk3.home.arpa) ([10.124.222.141]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2026 11:15:34 -0700 From: Tony Luck To: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Hans de Goede Cc: Borislav Petkov , Breno Leitao , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck , Qiuxu Zhuo Subject: [PATCH 4/7] platform/x86/intel/bff: Add Diamond Rapids support Date: Tue, 25 Aug 2026 11:15:23 -0700 Message-ID: <20260825181526.13203-5-tony.luck@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260825181526.13203-1-tony.luck@intel.com> References: <20260825181526.13203-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There are potentially bitfix filters associated with each machine check bank. Only some banks may implement them. Machine check banks have varying scope. E.g. there is a separate L2 cache for each module, each instance has its own bitfix filter. Add information that will be used to map a pair to a unique instance number for a bitfix filter. Co-developed-by: Qiuxu Zhuo Signed-off-by: Qiuxu Zhuo Signed-off-by: Tony Luck --- drivers/platform/x86/intel/bff.c | 41 ++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/platform/x86/intel/bff.c b/drivers/platform/x86/intel/= bff.c index 9522bdb1401d..6360bbc92347 100644 --- a/drivers/platform/x86/intel/bff.c +++ b/drivers/platform/x86/intel/bff.c @@ -18,18 +18,51 @@ #define pr_fmt(fmt) "bff: " fmt =20 #include +#include #include #include #include +#include #include =20 +#include #include +#include #include #include #include =20 +/* Machine check bank scope types */ +enum bff_type { + BFF_NONE =3D 0, + BFF_BANK_DCU, + BFF_BANK_DTLB, + BFF_BANK_MLC, + BFF_BANK_CCF, + BFF_BANK_HSF, + BFF_BANK_IOCACHE, +}; + +static const enum bff_type dmr_mcbanks[MAX_NR_BANKS] =3D { + [1] =3D BFF_BANK_DCU, + [2] =3D BFF_BANK_DTLB, + [3] =3D BFF_BANK_MLC, + [6] =3D BFF_BANK_CCF, + [13] =3D BFF_BANK_HSF, + [17] =3D BFF_BANK_IOCACHE +}; + +static const struct x86_cpu_id bff_cpu_ids[] __initconst =3D { + X86_MATCH_VFM(INTEL_DIAMONDRAPIDS_X, dmr_mcbanks), + {} +}; +MODULE_DEVICE_TABLE(x86cpu, bff_cpu_ids); + +static const enum bff_type *bank_types; + static int __init bff_init(void) { + const struct x86_cpu_id *m; u64 core_caps, mcg_cap; =20 if (!cpu_feature_enabled(X86_FEATURE_MCA)) @@ -45,6 +78,14 @@ static int __init bff_init(void) if (!(core_caps & MSR_IA32_CORE_CAPS_BFF_RESET_DETECT)) return -ENODEV; =20 + m =3D x86_match_cpu(bff_cpu_ids); + if (!m) { + pr_info("CPU supports bitfix filter, but driver does not\n"); + return -ENODEV; + } + + bank_types =3D (const enum bff_type *)m->driver_data; + return 0; } =20 --=20 2.55.0 From nobody Mon Sep 28 05:42:43 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4696431E840; Tue, 25 Aug 2026 18:15:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; 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25 Aug 2026 11:15:34 -0700 X-CSE-ConnectionGUID: 8IepgpC7Rsa+YC0s/Bn9Sw== X-CSE-MsgGUID: GX8QeEONRiCqpxHWvwnv4w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,243,1779174000"; d="scan'208";a="265559608" Received: from aschofie-mobl2.amr.corp.intel.com (HELO agluck-desk3.home.arpa) ([10.124.222.141]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2026 11:15:34 -0700 From: Tony Luck To: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Hans de Goede Cc: Borislav Petkov , Breno Leitao , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck , Qiuxu Zhuo Subject: [PATCH 5/7] platform/x86/intel/bff: Reset bitfix filter when it overflows Date: Tue, 25 Aug 2026 11:15:24 -0700 Message-ID: <20260825181526.13203-6-tony.luck@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260825181526.13203-1-tony.luck@intel.com> References: <20260825181526.13203-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Get notifications for all errors logged in machine check banks. Skip any that do not indicate a bitfix filter overflow. Reset the bitfix filter using the CPU that reported the error to get the right scoped machine check bank. Co-developed-by: Qiuxu Zhuo Signed-off-by: Qiuxu Zhuo Signed-off-by: Tony Luck --- drivers/platform/x86/intel/bff.c | 41 ++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/platform/x86/intel/bff.c b/drivers/platform/x86/intel/= bff.c index 6360bbc92347..8cc29d11e019 100644 --- a/drivers/platform/x86/intel/bff.c +++ b/drivers/platform/x86/intel/bff.c @@ -17,11 +17,13 @@ */ #define pr_fmt(fmt) "bff: " fmt =20 +#include #include #include #include #include #include +#include #include #include =20 @@ -32,6 +34,11 @@ #include #include =20 +/* Intel bitfix filter control register defines */ +#define MSR_MC0_BFF_CTL 0x000006c0 +#define MSR_MCx_BFF_CTL(x) (MSR_MC0_BFF_CTL + (x)) +#define MCI_BFF_RESET BIT_ULL(0) + /* Machine check bank scope types */ enum bff_type { BFF_NONE =3D 0, @@ -60,6 +67,37 @@ MODULE_DEVICE_TABLE(x86cpu, bff_cpu_ids); =20 static const enum bff_type *bank_types; =20 +static void handle_bff(struct mce *mce) +{ + /* The bitfix filter overflowed, get the target CPU to reset it. */ + if (wrmsrq_on_cpu(mce->extcpu, MSR_MCx_BFF_CTL(mce->bank), MCI_BFF_RESET)) + pr_warn("Failed to reset bitfix filter for CPU %d Bank %d\n", mce->extcp= u, mce->bank); +} + +static int bff_mce_notify(struct notifier_block *nb, unsigned long val, vo= id *data) +{ + struct mce *mce =3D (struct mce *)data; + + /* TES is undefined for uncorrected errors. */ + if (mce->status & MCI_STATUS_UC) + return NOTIFY_DONE; + + if (MCI_STATUS_TES(mce->status) !=3D MCI_STATUS_TES_YELLOW) + return NOTIFY_DONE; + + if (mce->bank >=3D MAX_NR_BANKS || bank_types[mce->bank] =3D=3D BFF_NONE) + return NOTIFY_DONE; + + handle_bff(mce); + + return NOTIFY_DONE; +} + +static struct notifier_block bff_notifier =3D { + .notifier_call =3D bff_mce_notify, + .priority =3D MCE_PRIO_EARLY, +}; + static int __init bff_init(void) { const struct x86_cpu_id *m; @@ -86,11 +124,14 @@ static int __init bff_init(void) =20 bank_types =3D (const enum bff_type *)m->driver_data; =20 + mce_register_decode_chain(&bff_notifier); + return 0; } =20 static void __exit bff_exit(void) { + mce_unregister_decode_chain(&bff_notifier); } =20 module_init(bff_init); --=20 2.55.0 From nobody Mon Sep 28 05:42:43 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9FDDA346E54; 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a="88174226" X-IronPort-AV: E=Sophos;i="6.25,243,1779174000"; d="scan'208";a="88174226" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2026 11:15:35 -0700 X-CSE-ConnectionGUID: aukwALA0RqihITxgGtoj3Q== X-CSE-MsgGUID: 9CnREe/JRaKfAbr13APjdA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,243,1779174000"; d="scan'208";a="265559611" Received: from aschofie-mobl2.amr.corp.intel.com (HELO agluck-desk3.home.arpa) ([10.124.222.141]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2026 11:15:35 -0700 From: Tony Luck To: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Hans de Goede Cc: Borislav Petkov , Breno Leitao , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck , Qiuxu Zhuo Subject: [PATCH 6/7] platform/x86/intel/bff: Compute unique ID for overflowed filter Date: Tue, 25 Aug 2026 11:15:25 -0700 Message-ID: <20260825181526.13203-7-tony.luck@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260825181526.13203-1-tony.luck@intel.com> References: <20260825181526.13203-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Each L2 cache instance has its own bitfix filter, but always reports errors in machine check bank 3 (on Diamond Rapids). Compute a unique bitfix filter instance number based on the CPU that logged the error and the machine check bank number. Special case for banks associated with the Integrated Memory Hub (IMH). Here the "even" numbered CPU modules are associated with IMH0 and the "odd" modules with IMH1. The unique id will be used to store a time stamp of when the bitfix filter overflowed so that frequent overflows can be logged. Co-developed-by: Qiuxu Zhuo Signed-off-by: Qiuxu Zhuo Signed-off-by: Tony Luck --- drivers/platform/x86/intel/bff.c | 74 ++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/drivers/platform/x86/intel/bff.c b/drivers/platform/x86/intel/= bff.c index 8cc29d11e019..ae9dc0bf2777 100644 --- a/drivers/platform/x86/intel/bff.c +++ b/drivers/platform/x86/intel/bff.c @@ -18,13 +18,18 @@ #define pr_fmt(fmt) "bff: " fmt =20 #include +#include +#include #include +#include #include #include #include +#include #include #include #include +#include #include =20 #include @@ -34,6 +39,8 @@ #include #include =20 +#define NUM_IMH_PER_SKT 2 + /* Intel bitfix filter control register defines */ #define MSR_MC0_BFF_CTL 0x000006c0 #define MSR_MCx_BFF_CTL(x) (MSR_MC0_BFF_CTL + (x)) @@ -67,11 +74,78 @@ MODULE_DEVICE_TABLE(x86cpu, bff_cpu_ids); =20 static const enum bff_type *bank_types; =20 +/* Diamond Rapids maps APICID[2] to the IMH instance. */ +static void bff_set_imh_id(struct mce *mce, unsigned long *id) +{ + int imh_num =3D (NUM_IMH_PER_SKT * topology_physical_package_id(mce->extc= pu)) + + ((mce->apicid >> 2) & 0x1); + + *id |=3D imh_num; +} + +static bool bff_set_cache_id(int cpu, int level, unsigned long *id) +{ + int cacheid; + + guard(cpus_read_lock)(); + + cacheid =3D get_cpu_cacheinfo_id(cpu, level); + if (cacheid =3D=3D -1) { + pr_warn("Could not get L%d cache id for CPU %d\n", level, cpu); + return false; + } + + *id |=3D cacheid; + + return true; +} + +#define BFF_ID_BANK_SHIFT 16 + +/* + * Cache IDs are only unique within a cache level. + * Include the MCA bank number so each BFF-capable hardware + * resource has a unique tracking ID. + */ +static unsigned long get_bff_id(struct mce *mce) +{ + unsigned long id =3D (unsigned long)mce->bank << BFF_ID_BANK_SHIFT; + + switch (bank_types[mce->bank]) { + case BFF_BANK_DCU: + case BFF_BANK_DTLB: + if (!bff_set_cache_id(mce->extcpu, 1, &id)) + return ULONG_MAX; + break; + + case BFF_BANK_MLC: + if (!bff_set_cache_id(mce->extcpu, 2, &id)) + return ULONG_MAX; + break; + + case BFF_BANK_CCF: + if (!bff_set_cache_id(mce->extcpu, 3, &id)) + return ULONG_MAX; + break; + + case BFF_BANK_HSF: + case BFF_BANK_IOCACHE: + bff_set_imh_id(mce, &id); + break; + default: + return ULONG_MAX; + } + + return id; +} + static void handle_bff(struct mce *mce) { /* The bitfix filter overflowed, get the target CPU to reset it. */ if (wrmsrq_on_cpu(mce->extcpu, MSR_MCx_BFF_CTL(mce->bank), MCI_BFF_RESET)) pr_warn("Failed to reset bitfix filter for CPU %d Bank %d\n", mce->extcp= u, mce->bank); + + pr_debug("unique_id =3D 0x%lx\n", get_bff_id(mce)); } =20 static int bff_mce_notify(struct notifier_block *nb, unsigned long val, vo= id *data) --=20 2.55.0 From nobody Mon Sep 28 05:42:43 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76E8D331ED6; Tue, 25 Aug 2026 18:15:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; 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25 Aug 2026 11:15:35 -0700 X-CSE-ConnectionGUID: 9c+OJRBNRaOnatZg6yJojA== X-CSE-MsgGUID: 1LtFGbwXRtqbYIncNl/6AQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,243,1779174000"; d="scan'208";a="265559616" Received: from aschofie-mobl2.amr.corp.intel.com (HELO agluck-desk3.home.arpa) ([10.124.222.141]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2026 11:15:35 -0700 From: Tony Luck To: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Hans de Goede Cc: Borislav Petkov , Breno Leitao , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck , Qiuxu Zhuo Subject: [PATCH 7/7] platform/x86/intel/bff: Report frequent filter resets Date: Tue, 25 Aug 2026 11:15:26 -0700 Message-ID: <20260825181526.13203-8-tony.luck@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260825181526.13203-1-tony.luck@intel.com> References: <20260825181526.13203-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If an instance of a bitfix filter contains some transient errors built up over time, then resetting the filter will free up slots in the filter to store persistent errors. Save a time stamp when "yellow" status is seen and clear the filter. Log at KERN_WARNING level if the overflow occurred quickly after a previous overflow on the same bitfix filter instance. Use KERN_NOTICE for first, or long delayed, overflow. Co-developed-by: Qiuxu Zhuo Signed-off-by: Qiuxu Zhuo Signed-off-by: Tony Luck --- drivers/platform/x86/intel/bff.c | 71 +++++++++++++++++++++++++++++++- 1 file changed, 70 insertions(+), 1 deletion(-) diff --git a/drivers/platform/x86/intel/bff.c b/drivers/platform/x86/intel/= bff.c index ae9dc0bf2777..7c22a1ad6b9d 100644 --- a/drivers/platform/x86/intel/bff.c +++ b/drivers/platform/x86/intel/bff.c @@ -23,14 +23,19 @@ #include #include #include +#include #include +#include #include +#include #include #include #include #include +#include #include #include +#include =20 #include #include @@ -39,6 +44,16 @@ #include #include =20 +/* + * A 10-minute observation period helps distinguish between: + * + * - A long-term accumulation of transient corrected errors + * (filter stays clear after reset). + * + * - Permanent defects (filter overflows again quickly). + */ +#define BFF_OVERFLOW_INTERVAL secs_to_jiffies(10 * 60) + #define NUM_IMH_PER_SKT 2 =20 /* Intel bitfix filter control register defines */ @@ -74,6 +89,8 @@ MODULE_DEVICE_TABLE(x86cpu, bff_cpu_ids); =20 static const enum bff_type *bank_types; =20 +static DEFINE_XARRAY(bff_bank_xa); + /* Diamond Rapids maps APICID[2] to the IMH instance. */ static void bff_set_imh_id(struct mce *mce, unsigned long *id) { @@ -139,13 +156,58 @@ static unsigned long get_bff_id(struct mce *mce) return id; } =20 +/* + * Save current timestamp for bff_id. Return true if it is within + * BFF_OVERFLOW_INTERVAL of previous timestamp for this bff_id. + */ +static bool bff_note_event_and_check_burst(unsigned long bff_id) +{ + unsigned long now =3D jiffies, when; + unsigned long *ts; + + if (bff_id =3D=3D ULONG_MAX) + return false; + + ts =3D xa_load(&bff_bank_xa, bff_id); + if (!ts) { + ts =3D kzalloc_obj(*ts); + if (!ts) { + pr_warn("Timestamp allocation failed\n"); + return false; + } + if (IS_ERR(xa_store(&bff_bank_xa, bff_id, ts, GFP_KERNEL))) { + kfree(ts); + pr_warn("Timestamp save failure\n"); + return false; + } + *ts =3D now; + + return false; + } + + when =3D *ts + BFF_OVERFLOW_INTERVAL; + *ts =3D now; + + return time_before(now, when); +} + static void handle_bff(struct mce *mce) { + bool burst =3D false; + /* The bitfix filter overflowed, get the target CPU to reset it. */ if (wrmsrq_on_cpu(mce->extcpu, MSR_MCx_BFF_CTL(mce->bank), MCI_BFF_RESET)) pr_warn("Failed to reset bitfix filter for CPU %d Bank %d\n", mce->extcp= u, mce->bank); =20 - pr_debug("unique_id =3D 0x%lx\n", get_bff_id(mce)); + /* Get unique id for bitfix filter instance that overflowed */ + burst =3D bff_note_event_and_check_burst(get_bff_id(mce)); + + if (burst) + pr_warn_ratelimited(HW_ERR "Socket %d CPU %d Bank %d bitfix filter overf= lowed frequently\n", + mce->socketid, mce->extcpu, mce->bank); + else + pr_notice_ratelimited(HW_ERR "Socket %d CPU %d Bank %d bitfix filter ove= rflowed\n", + mce->socketid, mce->extcpu, mce->bank); } =20 static int bff_mce_notify(struct notifier_block *nb, unsigned long val, vo= id *data) @@ -205,7 +267,14 @@ static int __init bff_init(void) =20 static void __exit bff_exit(void) { + unsigned long bff_id; + unsigned long *ts; + mce_unregister_decode_chain(&bff_notifier); + + xa_for_each(&bff_bank_xa, bff_id, ts) + kfree(ts); + xa_destroy(&bff_bank_xa); } =20 module_init(bff_init); --=20 2.55.0