From nobody Mon Sep 28 06:37:32 2026 Received: from mta0.migadu.com (out-228.mta0.migadu.com [91.218.175.228]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F0E438944E for ; Tue, 25 Aug 2026 16:42:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.228 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787676153; cv=none; b=hzaMLzQW7+PABv8R2kmwFWOBzi+pGbLVdJ1m36Zf+o9BmVSjfnAv8tQ4IpyEaZircMuRlcYBIG/b7ll5JteHJrKKwl7itvwDwzOccPKzWNMYVfBf73Op85vnM6wkQznna8GAnlyXKvGIuD/NmetegkHaldU2yuo+pplCX5sNGt0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787676153; c=relaxed/simple; bh=zQU2cneHWYiXgdAM5Ki7+W+91fket5ATQUH8SgIxbj8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fdsny/uR57bQvFkQi5i3Qc5SuaTldMc8Lz4N3T72h4+EPeHDB6CZ96wGRBgTRz3MjozNAerEtaF2EblSi3h5628h7u569RYJQof0j+T6IQY6rHzrV56Bc/RQ2iOrV1eJ3e8LuSRFZroxbKrALMgpJdUyg4nsoQXMeAPlUMrOn0k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=JeBT/yCI; arc=none smtp.client-ip=91.218.175.228 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="JeBT/yCI" X-Envelope-To: linux-kernel@vger.kernel.org DKIM-Signature: a=rsa-sha256; bh=zQU2cneHWYiXgdAM5Ki7+W+91fket5ATQUH8SgIxbj8=; c=simple/simple; d=linux.dev; h=from:to:subject:date:message-id:mime-version:content-type; s=key1; t=1787676150; v=1; x=1788280950; b=JeBT/yCId6Nw/f6FxMpE+FJ9DvG61j0vYhq4T1ddN5O92skKQ2/Xas5uIh6bqC2269YRGDIT OZupAdBGbry7mKjL8YWmjq/L8j1aqi+wyrtFmP1IbnYDhK5fj2ykyIQwdCLagtJvPMpmITRas3k KXFYvJXlgUbcfeqFrJybgelk= X-Envelope-To: linux-kernel@vger.kernel.org Received: from claudy.local (2a01:4b00:ad36:1d00:3a05:25ff:fe33:35a9) by smtp.migadu.com with ESMTPS id eb5a6faaae912dd9; Tue, 25 Aug 2026 16:42:30 +0000 X-Mizu-Trace-ID: eb5a6faaae912dd9 X-Migadu-Flow: FLOW_OUT From: Fuad Tabba To: Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org Cc: Marc Zyngier , Oliver Upton , Mark Rutland , Suzuki K Poulose , Mark Brown , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, Fuad Tabba Subject: [PATCH v4 1/2] arm64: Apply overrides to CPU local capabilities Date: Tue, 25 Aug 2026 17:42:18 +0100 Message-Id: <20260825164219.3347229-2-fuad.tabba@linux.dev> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260825164219.3347229-1-fuad.tabba@linux.dev> References: <20260825164219.3347229-1-fuad.tabba@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Suzuki K Poulose If an override has been applied, make sure we apply that for the secondary CPUs too, to limit the features. Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/all/afc5bd00-28ca-413b-b047-ee53589c285d@arm.= com/ Cc: stable@vger.kernel.org [Fuad: whitespace and comment fixes] Signed-off-by: Fuad Tabba Reviewed-by: Catalin Marinas --- arch/arm64/kernel/cpufeature.c | 42 +++++++++++++++++++++++++++------- 1 file changed, 34 insertions(+), 8 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 9a22df0c5120f..88b15b5ef2f7f 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1232,10 +1232,43 @@ void __init init_cpu_features(struct cpuinfo_arm64 = *info) init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); } =20 +/* + * Sanitise the register fields to clamp the values to the overrides that + * have been applied. + */ +static u64 override_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 val) +{ + const struct arm64_ftr_bits *ftrp; + + if (!reg || !reg->override->mask) + return val; + + for (ftrp =3D reg->ftr_bits; ftrp->width; ftrp++) { + u64 ftr_mask =3D arm64_ftr_mask(ftrp); + s64 ftr_val, ftr_ovr, ftr_safe; + + /* Skip the fields not overridden */ + if ((ftr_mask & reg->override->mask) !=3D ftr_mask) + continue; + + ftr_val =3D arm64_ftr_value(ftrp, val); + ftr_ovr =3D arm64_ftr_value(ftrp, reg->override->val); + ftr_safe =3D arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_val); + + if (ftr_safe !=3D ftr_val) + val =3D arm64_ftr_set_value(ftrp, val, ftr_safe); + } + + return val; +} + static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) { const struct arm64_ftr_bits *ftrp; =20 + /* Apply the overrides */ + new =3D override_cpu_ftr_reg(reg, new); + for (ftrp =3D reg->ftr_bits; ftrp->width; ftrp++) { s64 ftr_cur =3D arm64_ftr_value(ftrp, reg->sys_val); s64 ftr_new =3D arm64_ftr_value(ftrp, new); @@ -1539,7 +1572,6 @@ EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); */ u64 __read_sysreg_by_encoding(u32 sys_id) { - struct arm64_ftr_reg *regp; u64 val; =20 switch (sys_id) { @@ -1592,13 +1624,7 @@ u64 __read_sysreg_by_encoding(u32 sys_id) return 0; } =20 - regp =3D get_arm64_ftr_reg(sys_id); - if (regp) { - val &=3D ~regp->override->mask; - val |=3D (regp->override->val & regp->override->mask); - } - - return val; + return override_cpu_ftr_reg(get_arm64_ftr_reg(sys_id), val); } =20 #include --=20 2.39.5 From nobody Mon Sep 28 06:37:32 2026 Received: from mta1.migadu.com (out-85.mta1.migadu.com [95.215.58.85]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D48538944E for ; Tue, 25 Aug 2026 16:42:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.85 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787676158; cv=none; b=Te405B13vhItl2gyYOV0rvJI3ThYu8i1Zre0+w4zif5N2U2zbWKiJTO/2s+mvYY5pqMkedMBLmGJSahGZxY+IiRpgnEpaAs2umDkFLpQPI4+NG58tMxZ6XyaLBRdvIelBdHVF1l0k75saueo0zjL29twjabzoA+tiAAF4SMCD48= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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bh=CYocrFWmtpehijgOQcGCt0ml+hOpQBMXbSBN0pxWBYg=; c=simple/simple; d=linux.dev; h=from:to:subject:date:message-id:mime-version:content-type; s=key1; t=1787676154; v=1; x=1788280954; b=h/3l8OqFwZfY77u+/ur1hFq103jfMJ9kpESQwXqjQ/0w8oPXX1QGLKDk5FTdyLD9TqCe5bAI tLIiTIoov8PXdykCWf1yz36O4hJC0rCr+nWfx5nL4JqM0iwr4KKpnvYgHp48JDcHguREISdYIvb Yme+R6F35RrEtxLi2xfmi52o= X-Envelope-To: linux-kernel@vger.kernel.org Received: from claudy.local (2a01:4b00:ad36:1d00:3a05:25ff:fe33:35a9) by smtp.migadu.com with ESMTPS id 5c13a4e79d66ea44; Tue, 25 Aug 2026 16:42:34 +0000 X-Mizu-Trace-ID: 5c13a4e79d66ea44 X-Migadu-Flow: FLOW_OUT From: Fuad Tabba To: Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org Cc: Marc Zyngier , Oliver Upton , Mark Rutland , Suzuki K Poulose , Mark Brown , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, Fuad Tabba Subject: [PATCH v4 2/2] arm64: Don't read GMID_EL1 when MTE is disabled Date: Tue, 25 Aug 2026 17:42:19 +0100 Message-Id: <20260825164219.3347229-3-fuad.tabba@linux.dev> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260825164219.3347229-1-fuad.tabba@linux.dev> References: <20260825164219.3347229-1-fuad.tabba@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" __cpuinfo_store_cpu() gates the GMID_EL1 read on the raw ID_AA64PFR1_EL1, so it reads the register even when the kernel has disabled MTE (CONFIG_ARM64_MTE=3Dn or arm64.nomte). KVM sets HCR_EL2.TID5 in that case, and pKVM injects an UNDEF the host cannot handle: Internal error: Oops - Undefined instruction: 0000000002000000 [#1] SMP pc : __cpuinfo_store_cpu+0xf4/0x264 Kernel panic - not syncing: Attempted to kill the idle task! Only pKVM reaches it, and only after a CPU is offlined and brought back online: its CPU_ON relay sets the host HCR before the CPU enters EL1, while plain nVHE sets it at CPUHP_AP_KVM_ONLINE. Gate the read on __read_sysreg_by_encoding(), which applies the cmdline override, and on CONFIG_ARM64_MTE, which no register reflects. Fixes: f35abcbb8a084 ("KVM: arm64: Trap MTE access and discovery when MTE i= s disabled") Cc: stable@vger.kernel.org # needs "arm64: Apply overrides to CPU local cap= abilities" Signed-off-by: Fuad Tabba Reviewed-by: Catalin Marinas --- arch/arm64/include/asm/cpufeature.h | 9 +++++++++ arch/arm64/kernel/cpufeature.c | 6 ++---- arch/arm64/kernel/cpuinfo.c | 2 +- 3 files changed, 12 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/c= pufeature.h index a57870fa96db5..0b374e938f708 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -1085,6 +1085,15 @@ static inline bool cpu_has_lpa2(void) #endif } =20 +/* No ID register reflects CONFIG_ARM64_MTE. */ +static inline bool gmid_el1_accessible(void) +{ + if (!IS_ENABLED(CONFIG_ARM64_MTE)) + return false; + + return id_aa64pfr1_mte(__read_sysreg_by_encoding(SYS_ID_AA64PFR1_EL1)); +} + #endif /* __ASSEMBLER__ */ =20 #endif diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 88b15b5ef2f7f..23f174b3c4e26 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1228,7 +1228,7 @@ void __init init_cpu_features(struct cpuinfo_arm64 *i= nfo) init_cpu_ftr_reg(SYS_MPAMIDR_EL1, info->reg_mpamidr); } =20 - if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) + if (gmid_el1_accessible()) init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); } =20 @@ -1523,11 +1523,9 @@ void update_cpu_features(int cpu, * they read/write depends on the GMID_EL1.BS field. Check that the * value is the same on all CPUs. */ - if (IS_ENABLED(CONFIG_ARM64_MTE) && - id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { + if (gmid_el1_accessible()) taint |=3D check_update_ftr_reg(SYS_GMID_EL1, cpu, info->reg_gmid, boot->reg_gmid); - } =20 /* * If we don't have AArch32 at all then skip the checks entirely diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index d50e2a9b066b3..389fca84f106b 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -502,7 +502,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *i= nfo) info->reg_id_aa64smfr0 =3D read_cpuid(ID_AA64SMFR0_EL1); info->reg_id_aa64fpfr0 =3D read_cpuid(ID_AA64FPFR0_EL1); =20 - if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) + if (gmid_el1_accessible()) info->reg_gmid =3D read_cpuid(GMID_EL1); =20 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) --=20 2.39.5