From nobody Mon Sep 28 07:18:38 2026 Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A1C2278161 for ; Tue, 25 Aug 2026 07:33:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787643233; cv=none; b=qWXFVX/nngrkYW/VJg02I/xS3l1dcgnCH/ouQJD2Pq8EL3EGDJXix2oyrIHtzqo6dGiiTWtRh3z2Akh905R+5iDF3DQ5ThgEJck4m+hu9rLDfDbKgJ84La+3mAXuiYEc3bKAvunRWLYZMD0QvIRiQD80p15oeel6x60Dghw4qLM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787643233; c=relaxed/simple; bh=zsbrArDZP40Pye7xkcMDrasEPH51UxcCiIUVUko/2sc=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version:Content-Type; b=f+xVy7uKT/eCUVsmSHFEczl5ymqpEmegOxYlLuFvAojbz2ixXVoInZGZzJIWKKmLVmk0AhvekWMGUoQhQwgtlts3wLaW7fuc2UCHCie+ptA8Ica+N/8JnBd5um3pMSZABZkumQmiZUF04WMbs6idx2g67LlQs6JHrmSiaRbHpqA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [111.196.241.250]) by APP-03 (Coremail) with SMTP id rQCowAAXHz1IRY1qO684Bg--.16779S2; Tue, 25 Aug 2026 15:33:29 +0800 (CST) From: Pengpeng Hou To: Thomas Gleixner Cc: Pengpeng Hou , Radu Rendec , Paul Walmsley , Samuel Holland , Charles Mirabile , Lucas Zampieri , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH] irqchip/sifive-plic: Avoid signed shift in interrupt enable mask Date: Tue, 25 Aug 2026 15:33:26 +0800 Message-ID: <20260825151000.1-plic-bit31-caplitmus-rv@iscas.ac.cn> X-Mailer: git-send-email 2.50.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: rQCowAAXHz1IRY1qO684Bg--.16779S2 X-Coremail-Antispam: 1UD129KBjvdXoW7GrykArW7ZFWktF4UuF4fGrg_yoWkWrc_ur yjqwsrGayFyrn3ZFySkFW7ZryrXa4DW3Z7WwsYgFs0qrn0gw48Cr1Sqr15ZayrWr129r1x CrWDurySkw1xCjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJTRUUUb48FF20E14v26r4j6ryUM7CY07I20VC2zVCF04k26cxKx2IYs7xG 6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8w A2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_ Gr1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oV Cq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0 I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r 4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY1x0262kKe7AKxVWU tVW8ZwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14 v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkG c2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI 0_Jr0_Gr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4U MIIF0xvEx4A2jsIEc7CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7VUbGQ6JUUUU U== X-CM-SenderInfo: pshqw1xhqjqxpvfd2hldfou0/ Content-Type: text/plain; charset="utf-8" __plic_toggle() builds a 32-bit enable-register mask from the hardware interrupt number. A valid interrupt whose low five bits are 31 evaluates 1 << 31, which shifts a signed int into its sign bit and is undefined behavior. Use BIT(), matching the equivalent mask construction in plic_irq_eoi(). Fixes: 14ff9e54dd14 ("irqchip/sifive-plic: Cache the interrupt enable state= ") Assisted-by: Codex:gpt-5 Signed-off-by: Pengpeng Hou --- drivers/irqchip/irq-sifive-plic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index 5b0dac104814..d3d4187b96ab 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -108,6 +108,6 @@ static int plic_irq_set_type(struct irq_data *d, unsign= ed int type); static void __plic_toggle(struct plic_handler *handler, int hwirq, int ena= ble) { u32 __iomem *base =3D handler->enable_base; - u32 hwirq_mask =3D 1 << (hwirq % 32); + u32 hwirq_mask =3D BIT(hwirq % 32); int group =3D hwirq / 32; u32 value;