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[92.247.61.126]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6a59e00129fsm17187878a12.1.2026.08.25.07.02.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2026 07:02:35 -0700 (PDT) From: Petko Manolov To: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Petko Manolov Subject: [PATCH v1 1/1] ARM: dts: draeger: Add devicetree files for M48 Intel/Altera SoCFPGA Cyclone Date: Tue, 25 Aug 2026 17:02:22 +0300 Message-ID: <20260825140225.3968019-2-petko.manolov@konsulko.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260825140225.3968019-1-petko.manolov@konsulko.com> References: <20260825140225.3968019-1-petko.manolov@konsulko.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Signed-off-by: Petko Manolov --- arch/arm/boot/dts/intel/socfpga/Makefile | 1 + .../socfpga/socfpga_cyclone5_draeger_m48.dts | 132 ++++++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draege= r_m48.dts diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/i= ntel/socfpga/Makefile index 8df0976da01c..cdcea11abdfa 100644 --- a/arch/arm/boot/dts/intel/socfpga/Makefile +++ b/arch/arm/boot/dts/intel/socfpga/Makefile @@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) +=3D \ socfpga_arria10_mercury_aa1_st1_emmc.dtb \ socfpga_arria10_mercury_aa1_st1_qspi.dtb \ socfpga_arria10_mercury_aa1_st1_sdmmc.dtb \ + socfpga_cyclone5_draeger_m48.dtb \ socfpga_cyclone5_mercury_sa1_pe1_emmc.dtb \ socfpga_cyclone5_mercury_sa1_pe1_qspi.dtb \ socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dtb \ diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.d= ts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts new file mode 100644 index 000000000000..fd597f15c0d8 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2020 Draeger and Licensors, info@draeger.com + */ +#include "socfpga_cyclone5.dtsi" + +/ { + model =3D "Draeger M48 Cyclone V SoC"; + compatible =3D "draeger,M48/socfpga", "altr,socfpga-cyclone5", "altr,socf= pga"; + + chosen { + bootargs =3D "earlyprintk"; + stdout-path =3D "serial0:115200n8"; + }; + + memory@0 { + name =3D "memory"; + device_type =3D "memory"; + reg =3D <0x0 0x40000000>; + + /* 1GB */ + }; + + aliases { + /* this allow the ethaddr uboot environmnet variable contents + * to be added to the gmac1 device tree blob. + */ + ethernet0 =3D &gmac0; + }; + + soc { + gpio3: gpio@0xff202000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0xff202000 0x20>; + status =3D "okay"; + + portd: gpio-controller@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <2>; + reg =3D <0>; + bank-name =3D "SYNC_I"; + }; + }; + + gpio4: gpio@0xff202020 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0xff202020 0x20>; + status =3D "okay"; + + porte: gpio-controller@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <2>; + reg =3D <0>; + bank-name =3D "SYNC_O"; + }; + }; + }; +}; + +&gmac0 { + status =3D "okay"; + phy-mode =3D "rgmii-id"; + rxc-skew-ps =3D <1860>; + rxd0-skew-ps =3D <0>; + rxd1-skew-ps =3D <0>; + rxd2-skew-ps =3D <0>; + rxd3-skew-ps =3D <0>; + rxdv-skew-ps =3D <0>; + txc-skew-ps =3D <900>; + txd0-skew-ps =3D <0>; + txd1-skew-ps =3D <0>; + txd2-skew-ps =3D <0>; + txd3-skew-ps =3D <0>; + txen-skew-ps =3D <0>; +}; + +&gpio0 { + status =3D "okay"; +}; + +&gpio1 { + status =3D "okay"; +}; + +&gpio2 { + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; + clock-frequency =3D <100000>; + + eeprom_mac: eeprom@50 { + compatible =3D "atmel,24c08"; + reg =3D <0x50>; + pagesize =3D <16>; + }; +}; + +&mmc0 { + status =3D "okay"; +}; + +&qspi { + status =3D "okay"; + + flash0: n25q00@0 { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "n25q00"; + reg =3D <0>; + + /* chip select */ + spi-max-frequency =3D <100000000>; + m25p,fast-read; + cdns,page-size =3D <256>; + cdns,block-size =3D <16>; + cdns,read-delay =3D <4>; + cdns,tshsl-ns =3D <50>; + cdns,tsd2d-ns =3D <50>; + cdns,tchsh-ns =3D <4>; + cdns,tslch-ns =3D <4>; + }; +}; --=20 2.47.3 From nobody Mon Sep 28 06:35:37 2026 Received: from mail-ed1-f52.google.com (mail-ed1-f52.google.com [209.85.208.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0160A47ECE8 for ; Tue, 25 Aug 2026 14:02:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787666561; cv=none; b=emw7lOhJmy9pZPdbsOvFi2LOEHIW6MhRQUmZo81xSKoNMhBAG1DxfByDB4gNhtojFTrkIDL9Xmvjb0iSk+vz+hlW2qF69UKAhBJJWfAUkTO7gkGZ0MfobN4nJikTbcbyqhFfOI5laICockh/L+hs2tNZGVGYLrjXvnWbJIzOLxU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787666561; 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[92.247.61.126]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6a59e00129fsm17187878a12.1.2026.08.25.07.02.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2026 07:02:36 -0700 (PDT) From: Petko Manolov To: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Petko Manolov Subject: [PATCH v1 1/1] ARM: dts: draeger: Add devicetree files for M48 on NXP i.MX6(Q) Date: Tue, 25 Aug 2026 17:02:23 +0300 Message-ID: <20260825140225.3968019-3-petko.manolov@konsulko.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260825140225.3968019-1-petko.manolov@konsulko.com> References: <20260825140225.3968019-1-petko.manolov@konsulko.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Signed-off-by: Petko Manolov --- arch/arm/boot/dts/nxp/imx/Makefile | 2 + .../boot/dts/nxp/imx/imx6dl-draeger-m48.dts | 23 ++ .../boot/dts/nxp/imx/imx6q-draeger-m48.dts | 23 ++ .../boot/dts/nxp/imx/imx6qdl-draeger-m48.dtsi | 369 ++++++++++++++++++ .../boot/dts/nxp/imx/imx6qp-draeger-m48.dts | 78 ++++ 5 files changed, 495 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6dl-draeger-m48.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6q-draeger-m48.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6qdl-draeger-m48.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx6qp-draeger-m48.dts diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx= /Makefile index 1a2539fa19b4..44b393256235 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -220,6 +220,8 @@ dtb-$(CONFIG_SOC_IMX6Q) +=3D \ imx6q-dmo-edmqmx6.dtb \ imx6q-dms-ba16.dtb \ imx6q-ds.dtb \ + imx6q-draeger-m48.dtb \ + imx6dl-draeger-m48.dtb \ imx6q-emcon-avari.dtb \ imx6q-evi.dtb \ imx6dl-b105pv2.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-draeger-m48.dts b/arch/arm/bo= ot/dts/nxp/imx/imx6dl-draeger-m48.dts new file mode 100644 index 000000000000..45809770d16f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-draeger-m48.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * (C) Copyright 2020 Draeger and Licensors, info@draeger.com + * Based on work by Russell King + * + * Device Tree file for Drager M48 Board + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +/* PAD config disabled in imx6qdl-draeger-m48.dtsi by setting value to 0x8= 0000000 + * PAD configuration register must not be 0, so it is set to 0xfff + */ +#define MX6QDL_PAD_CTL_GRP_DDR_TYPE_RGMII 0x768 0xfff 0x000 0x000C0= 000 0x0 +#define MX6QDL_PAD_CTL_GRP_RGMII_TERM 0x788 0xfff 0x000 0x00000= 200 0x0 +#include "imx6qdl-draeger-m48.dtsi" + +/ { + model =3D "Draeger M48 i.MX6 DualLite"; + compatible =3D "draeger,imx6dl-m48", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-draeger-m48.dts b/arch/arm/boo= t/dts/nxp/imx/imx6q-draeger-m48.dts new file mode 100644 index 000000000000..1266b8451fa1 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-draeger-m48.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * (C) Copyright 2020 Draeger and Licensors, info@draeger.com + * + * Device Tree file for Drager M48 Board + */ + +/dts-v1/; + +#include "imx6q.dtsi" +/* PAD config disabled in imx6qdl-draeger-m48.dtsi by setting value to 0x8= 0000000 + * PAD configuration register must not be 0, so it is set to 0xfff + */ +#define MX6QDL_PAD_CTL_GRP_DDR_TYPE_RGMII 0x790 0xfff 0x000 0x000C0= 000 0x0 +#define MX6QDL_PAD_CTL_GRP_RGMII_TERM 0x7ac 0xfff 0x000 0x00000= 200 0x0 + +#include "imx6qdl-draeger-m48.dtsi" + +/ { + model =3D "Draeger M48 i.MX6 Quad"; + compatible =3D "draeger,imx6q-m48", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-draeger-m48.dtsi b/arch/arm/= boot/dts/nxp/imx/imx6qdl-draeger-m48.dtsi new file mode 100644 index 000000000000..bcfe7b2556cb --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-draeger-m48.dtsi @@ -0,0 +1,369 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2020 Draeger and Licensors, info@draeger.com + * Based on work by Russell King + * + * Device Tree file for Drager M48 Board + */ +#include +#include +#include + +&iomuxc { + m48 { + pinctrl_m48_uart1: m48-uart1 { + fsl,pins =3D < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b010 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b010 + >; + }; + + pinctrl_m48_hdmi: m48-hdmi { + fsl,pins =3D < + MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x1b0b0 + MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x1b0b0 + >; + }; + + pinctrl_m48_lvds: m48-lvds { + fsl,pins =3D < + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b010 /* DISPLAY_EN */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b010 /* BACKLIGHT_EN */ + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b010 /* DISP0_CONTRAST */ + >; + }; + + pinctrl_m48_i2c2: m48-i2c2 { + fsl,pins =3D < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b820 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b820 + >; + }; + + pinctrl_m48_i2c2_gpio: m48-i2c2_gpio { + fsl,pins =3D < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b820 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b820 + >; +#define GP_I2C2_SCL <&gpio4 12 GPIO_ACTIVE_HIGH> +#define GP_I2C2_SDA <&gpio4 13 GPIO_ACTIVE_HIGH> + }; + + pinctrl_m48_i2c3: m48-i2c3 { + fsl,pins =3D < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b820 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b820 + >; + }; + + pinctrl_m48_i2c3_gpio: m48-i2c3_gpio { + fsl,pins =3D < + MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x1b820 + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b820 + >; +#define GP_I2C3_SCL <&gpio3 17 GPIO_ACTIVE_HIGH> +#define GP_I2C3_SDA <&gpio3 18 GPIO_ACTIVE_HIGH> + }; + + pinctrl_m48_usdhc3: m48-usdhc3 { + fsl,pins =3D < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x1B060 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x1B060 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x1B060 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x1B060 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x1B060 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x1B060 + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x1B060 + >; + }; + + pinctrl_m48_enet: enetgrp { + fsl,pins =3D < + MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x13018 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1B018 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1B018 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1B018 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1B018 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x13018 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x13030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1B030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1B030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1B030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1B030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 + MX6QDL_PAD_CTL_GRP_DDR_TYPE_RGMII 0x80000000 + MX6QDL_PAD_CTL_GRP_RGMII_TERM 0x80000000 + >; + }; + }; +}; + +&i2c2 { + clock-frequency =3D <100000>; + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_m48_i2c2>; + pinctrl-1 =3D <&pinctrl_m48_i2c2_gpio>; + scl-gpios =3D GP_I2C2_SCL; + sda-gpios =3D GP_I2C2_SDA; + status =3D "okay"; + + eeprom_mac: eeprom@50 { + compatible =3D "atmel,24c08"; + reg =3D <0x50>; + pagesize =3D <16>; + }; +}; + +&i2c3 { + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_m48_i2c3>; + pinctrl-1 =3D <&pinctrl_m48_i2c3_gpio>; + scl-gpios =3D GP_I2C3_SCL; + sda-gpios =3D GP_I2C3_SDA; + status =3D "okay"; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_m48_uart1>; + status =3D "okay"; +}; + +&usdhc3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_m48_usdhc3>; + non-removable; + fsl,wp-controller; + status =3D "okay"; +}; + +&fec { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_m48_enet>; + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy>; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy: ethernet-phy@0 { + reg =3D <0>; + rxc-skew-ps =3D <1380>; + rxd0-skew-ps =3D <0>; + rxd1-skew-ps =3D <0>; + rxd2-skew-ps =3D <0>; + rxd3-skew-ps =3D <0>; + rxdv-skew-ps =3D <0>; + txc-skew-ps =3D <1860>; + txd0-skew-ps =3D <0>; + txd1-skew-ps =3D <0>; + txd2-skew-ps =3D <0>; + txd3-skew-ps =3D <0>; + txen-skew-ps =3D <0>; + status =3D "okay"; + }; + }; +}; + +&hdmi { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_m48_hdmi>; + + display-timings { + native-mode =3D <&hdmi0>; + + hdmi0: hdmi { + clock-frequency =3D <65000000>; + hactive =3D <1024>; + vactive =3D <768>; + hback-porch =3D <220>; + hfront-porch =3D <40>; + vback-porch =3D <21>; + vfront-porch =3D <7>; + hsync-len =3D <60>; + vsync-len =3D <10>; + }; + + hdmi1: hdmi-1280x800-24@60 { + clock-frequency =3D <71000000>; + hactive =3D <1280>; + vactive =3D <800>; + hback-porch =3D <80>; + hfront-porch =3D <48>; + vback-porch =3D <14>; + vfront-porch =3D <3>; + hsync-len =3D <32>; + vsync-len =3D <6>; + }; + + hdmi2: hdmi-1366x768-32@60 { + clock-frequency =3D <72000000>; + hactive =3D <1366>; + vactive =3D <768>; + hback-porch =3D <80>; + hfront-porch =3D <48>; + vback-porch =3D <14>; + vfront-porch =3D <3>; + hsync-len =3D <32>; + vsync-len =3D <5>; + }; + }; +}; + +&ldb { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_m48_lvds>; + + lvds-channel@0 { + fsl,data-mapping =3D "spwg"; + fsl,default-data-width =3D <24>; + status =3D "okay"; + + display-timings { + native-mode =3D <&timing0>; + + timing0: 1920x1080-32@60 { + fsl,dual-channel; + + /* LVDS split mode */ + clock-frequency =3D <71190000>; + + /* pixclk /2 */ + hactive =3D <1920>; + vactive =3D <1080>; + hback-porch =3D <60>; + + /* left * 2 */ + hfront-porch =3D <60>; + + /* right * 2 */ + vback-porch =3D <30>; + vfront-porch =3D <3>; + hsync-len =3D <60>; + + /* hsync * 2 */ + vsync-len =3D <17>; + }; + + timing1: 1366x768-32@60 { + clock-frequency =3D <72000000>; + hactive =3D <1366>; + vactive =3D <768>; + hback-porch =3D <80>; + hfront-porch =3D <48>; + vback-porch =3D <14>; + vfront-porch =3D <3>; + hsync-len =3D <32>; + vsync-len =3D <5>; + }; + + timing2: 1280x800-24@60 { + fsl,data-width =3D <18>; + clock-frequency =3D <71000000>; + hactive =3D <1280>; + vactive =3D <800>; + hback-porch =3D <80>; + hfront-porch =3D <48>; + vback-porch =3D <14>; + vfront-porch =3D <3>; + hsync-len =3D <32>; + vsync-len =3D <6>; + }; + + timing3: Tianma_1280x800-24@60 { + fsl,data-width =3D <18>; + clock-frequency =3D <67254000>; + hactive =3D <1280>; + vactive =3D <800>; + hback-porch =3D <5>; + hfront-porch =3D <27>; + vback-porch =3D <2>; + vfront-porch =3D <26>; + hsync-len =3D <32>; + vsync-len =3D <6>; + }; + + timing4: 1024x768-24@60 { + fsl,data-width =3D <18>; + clock-frequency =3D <65000000>; + hactive =3D <1024>; + vactive =3D <768>; + hback-porch =3D <160>; + hfront-porch =3D <24>; + vback-porch =3D <29>; + vfront-porch =3D <3>; + hsync-len =3D <136>; + vsync-len =3D <6>; + }; + + timing5: 800x600-32@60 { + clock-frequency =3D <40000000>; + hactive =3D <800>; + vactive =3D <600>; + hback-porch =3D <120>; + hfront-porch =3D <40>; + vback-porch =3D <28>; + vfront-porch =3D <13>; + hsync-len =3D <80>; + vsync-len =3D <4>; + }; + + timing6: 800x480-32@60 { + clock-frequency =3D <25000000>; + hactive =3D <800>; + vactive =3D <480>; + hback-porch =3D <8>; + hfront-porch =3D <8>; + vback-porch =3D <8>; + vfront-porch =3D <8>; + hsync-len =3D <4>; + vsync-len =3D <4>; + }; + + timing7: 640x480-32@60 { + clock-frequency =3D <25175000>; + hactive =3D <640>; + vactive =3D <480>; + hback-porch =3D <48>; + hfront-porch =3D <16>; + vback-porch =3D <33>; + vfront-porch =3D <10>; + hsync-len =3D <96>; + vsync-len =3D <2>; + }; + }; + }; +}; + +/ { + aliases { + mmc0 =3D &usdhc3; + mmc1 =3D &usdhc4; + eeprom_mac =3D &eeprom_mac; + }; + + /* Will be filled by the bootloader */ + memory@10000000 { + device_type =3D "memory"; + reg =3D <0x10000000 0x80000000>; + }; + + chosen { + stdout-path =3D &uart1; + }; + + config { + #ifdef LEGACY_BOOT + bootcmd =3D "startM48;errorMsg"; + bootcmd =3D "startKernel;errorMsg"; + #endif + + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-draeger-m48.dts b/arch/arm/bo= ot/dts/nxp/imx/imx6qp-draeger-m48.dts new file mode 100644 index 000000000000..ab331596abd9 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-draeger-m48.dts @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2020 Draeger and Licensors, info@draeger.com + * + * Device Tree file for Drager M48 Board + */ + +/dts-v1/; + +#include "imx6q.dtsi" +/* PAD config disabled in imx6qdl-draeger-m48.dtsi by setting value to 0x8= 0000000 + * PAD configuration register must not be 0, so it is set to 0xfff + */ +#define MX6QDL_PAD_CTL_GRP_DDR_TYPE_RGMII 0x790 0xfff 0x000 0x000C0= 000 0x0 +#define MX6QDL_PAD_CTL_GRP_RGMII_TERM 0x7ac 0xfff 0x000 0x00000= 200 0x0 +#define IMX_PAD_SION 0x40000000 /* set SION */ + +#include "imx6qdl-draeger-m48.dtsi" +#include "imx6qdl-draeger-m48-u-boot.dtsi" + +/ { + model =3D "Draeger M48 i.MX6 Quad Plus"; + compatible =3D "draeger,imx6qp-m48", "fsl,imx6qp"; + + vccq_sdhc3: regulator-vccq-sdhc3 { + compatible =3D "regulator-gpio"; + regulator-name =3D "SDHC3 VccQ"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_m48_regulatorvccq_sdhc3>; + gpios =3D <&gpio6 16 GPIO_ACTIVE_HIGH>; + gpios-states =3D <1>; + states =3D <3300000 0>, <1800000 1>; + }; +}; + +&iomuxc { + m48 { + pinctrl_m48_usdhc3_100mhz: m48-usdhc3_100mhz { + fsl,pins =3D < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x1B0E9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x1B0E9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x1B0E9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x1B0E9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x1B0E9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x1B0E9 + >; + }; + pinctrl_m48_usdhc3_200mhz: m48-usdhc3_200mhz { + fsl,pins =3D < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x1B0E9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x1B0E9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x1B0E9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x1B0E9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x1B0E9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x1B0E9 + >; + }; + + pinctrl_m48_regulatorvccq_sdhc3: m48-vccq-sdhc3 { + fsl,pins =3D ; + }; + }; +}; + +&usdhc3 { + compatible =3D "fsl,imx6qp-usdhc"; + vqmmc-supply =3D <&vccq_sdhc3>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_m48_usdhc3>; + pinctrl-1 =3D <&pinctrl_m48_usdhc3_100mhz>; + pinctrl-2 =3D <&pinctrl_m48_usdhc3_200mhz>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; +}; --=20 2.47.3