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Tue, 25 Aug 2026 02:50:52 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Claudiu Beznea , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Rob Herring , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH 1/4] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3L SoC Date: Tue, 25 Aug 2026 10:50:40 +0100 Message-ID: <20260825095047.9971-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260825095047.9971-1-biju.das.jz@bp.renesas.com> References: <20260825095047.9971-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Extend the existing device tree bindings for Renesas RZ/G3S PCIe controller to include support for the RZ/G3L (renesas,r9a08g046-pcie) PCIe controller. The RZ/G3L PCIe controller is similar to RZ/G3S but has some key differences: - Has 3 clocks compared to 2 on other SoCs. - Has a different set of reset signals Add device tree bindings for renesas,r9a08g046-pcie compatible IPs. Signed-off-by: Biju Das --- .../bindings/pci/renesas,r9a08g045-pcie.yaml | 33 ++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.y= aml b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml index 09d78bd1a577..911b1976bf53 100644 --- a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml @@ -13,7 +13,7 @@ description: | PCIe host controller found in Renesas RZ/G3S and similar SoCs complies with PCIe Base Specification 4.0 and supports different link speeds depending on the SoC variant: - - Gen2 (5 GT/s): RZ/G3S + - Gen2 (5 GT/s): RZ/G3{L,S} - Gen3 (8 GT/s): RZ/G3E, RZ/V2H(P), RZ/V2N =20 properties: @@ -21,6 +21,7 @@ properties: oneOf: - enum: - renesas,r9a08g045-pcie # RZ/G3S + - renesas,r9a08g046-pcie # RZ/G3L - renesas,r9a09g047-pcie # RZ/G3E - renesas,r9a09g057-pcie # RZ/V2H(P) - items: @@ -87,14 +88,18 @@ properties: interrupt-controller: true =20 clocks: + minItems: 2 items: - description: System clock - description: PM control clock or clock for L1 substate handling + - description: PM control clock or clock for L1 substate handling =20 clock-names: + minItems: 2 items: - const: aclk - enum: [pm, pmu] + - enum: [pm, pmu] =20 resets: minItems: 1 @@ -215,6 +220,8 @@ allOf: maxItems: 16 interrupt-names: maxItems: 16 + clocks: + maxItems: 2 clock-names: items: - const: aclk @@ -223,6 +230,28 @@ allOf: minItems: 7 reset-names: minItems: 7 + - if: + properties: + compatible: + contains: + const: renesas,r9a08g046-pcie + then: + properties: + interrupts: + maxItems: 16 + interrupt-names: + maxItems: 16 + clocks: + minItems: 3 + clock-names: + items: + - const: aclk + - const: pm + - const: pmu + resets: + maxItems: 1 + reset-names: + maxItems: 1 - if: properties: compatible: @@ -236,6 +265,8 @@ allOf: minItems: 23 interrupt-names: minItems: 23 + clocks: + maxItems: 2 clock-names: items: - const: aclk --=20 2.43.0 From nobody Mon Sep 28 06:35:54 2026 Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F8BB3F410E for ; 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charset="utf-8" From: Biju Das Add the PCIe module clocks (ACLK, CLKL1PM, CLK_PMU) and the PCIe reset signal for the RZ/G3L (R9A08G046) SoC, along with the P8 fixed clock required as the parent for CLKL1PM. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a08g046-cpg.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a0= 8g046-cpg.c index 5878423db151..22821321a1d3 100644 --- a/drivers/clk/renesas/r9a08g046-cpg.c +++ b/drivers/clk/renesas/r9a08g046-cpg.c @@ -335,6 +335,7 @@ static const struct cpg_core_clk r9a08g046_core_clks[] = __initconst =3D { dtable_8_256, 0, 0, 0, NULL), DEF_G3S_DIV("P3", R9A08G046_CLK_P3, CLK_PLL2_DIV2, G3L_DIVPL2A, G3L_DIVPL= 2A_STS, dtable_4_128, 0, 0, 0, NULL), + DEF_FIXED("P8", R9A08G046_CLK_P8, CLK_PLL3_DIV2, 1, 8), DEF_G3S_DIV("P13", R9A08G046_CLK_P13, CLK_SEL_RSCI0, G3L_DIV_RSCI0, G3L_D= IV_RSCI0_STS, dtable_2_16, 0, 100000000UL, 0, NULL), DEF_G3S_DIV("P14", R9A08G046_CLK_P14, CLK_SEL_RSCI1, G3L_DIV_RSCI1, G3L_D= IV_RSCI1_STS, @@ -558,6 +559,12 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[]= =3D { MSTOP(BUS_MCPU2, BIT(0))), DEF_MOD("gpio_hclk", R9A08G046_GPIO_HCLK, R9A08G046_OSCCLK, 0x598, 0, MSTOP(BUS_PERI_CPU, BIT(6))), + DEF_MOD("pci_aclk", R9A08G046_PCI_ACLK, R9A08G046_CLK_P1, 0x608, 0, + MSTOP(BUS_PERI_COM, BIT(10))), + DEF_MOD("pci_clkl1pm", R9A08G046_PCI_CLKL1PM, R9A08G046_CLK_P8, 0x608, 1, + MSTOP(BUS_PERI_COM, BIT(10))), + DEF_MOD("pci_clk_pmu", R9A08G046_PCI_CLK_PMU, R9A08G046_CLK_P1, 0x608, 2, + MSTOP(BUS_PERI_COM, BIT(10))), DEF_MOD("rsci0_pclk", R9A08G046_RSCI0_PCLK, R9A08G046_CLK_P0, 0x618, 0, MSTOP(BUS_MCPU2, BIT(7))), DEF_MOD("rsci1_pclk", R9A08G046_RSCI1_PCLK, R9A08G046_CLK_P0, 0x618, 1, @@ -633,6 +640,7 @@ static const struct rzg2l_reset r9a08g046_resets[] =3D { DEF_RST(R9A08G046_GPIO_RSTN, 0x898, 0), DEF_RST(R9A08G046_GPIO_PORT_RESETN, 0x898, 1), DEF_RST(R9A08G046_GPIO_SPARE_RESETN, 0x898, 2), + DEF_RST(R9A08G046_PCI_ARESETN, 0x908, 0), DEF_RST(R9A08G046_RSCI0_PRESETN, 0x918, 0), DEF_RST(R9A08G046_RSCI1_PRESETN, 0x918, 1), DEF_RST(R9A08G046_RSCI2_PRESETN, 0x918, 2), @@ -671,6 +679,7 @@ static const unsigned int r9a08g046_no_pm_mod_clks[] = =3D { MOD_CLK_BASE + R9A08G046_ETH1_CLK_RMII_I, MOD_CLK_BASE + R9A08G046_ETH1_CLK_TX_I_RMII, MOD_CLK_BASE + R9A08G046_ETH1_CLK_RX_I_RMII, + MOD_CLK_BASE + R9A08G046_PCI_CLKL1PM, }; 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Tue, 25 Aug 2026 02:50:54 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Claudiu Beznea , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Rob Herring , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH 3/4] PCI: rzg3s-host: Add support for RZ/G3L SoC Date: Tue, 25 Aug 2026 10:50:42 +0100 Message-ID: <20260825095047.9971-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260825095047.9971-1-biju.das.jz@bp.renesas.com> References: <20260825095047.9971-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add SoC-specific data for the RZ/G3L (R9A08G046) PCIe controller and register its "renesas,r9a08g046-pcie" compatible string. RZ/G3L reuses the RZ/G3E config init/deinit callbacks and power resets, with its own L1-allow syscon offset and mask. Also increase the timeout in rzg3s_pcie_set_max_link_speed() to fix the "Failed to set max link speed" message seen on RZ/G3L. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- drivers/pci/controller/pcie-rzg3s-host.c | 25 +++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/control= ler/pcie-rzg3s-host.c index b3531468ef38..3dffb85c6a47 100644 --- a/drivers/pci/controller/pcie-rzg3s-host.c +++ b/drivers/pci/controller/pcie-rzg3s-host.c @@ -1165,7 +1165,7 @@ static int rzg3s_pcie_set_max_link_speed(struct rzg3s= _pcie_host *host) FIELD_GET(RZG3S_PCI_PCSTAT1_LTSSM_STATE, tmp) =3D=3D ltssm_state_l0, PCIE_LINK_WAIT_SLEEP_MS * MILLI, PCIE_LINK_WAIT_SLEEP_MS * MILLI * - PCIE_LINK_WAIT_MAX_RETRIES); + PCIE_LINK_WAIT_MAX_RETRIES * 10); if (ret) return ret; =20 @@ -2467,6 +2467,25 @@ static const struct rzg3s_pcie_soc_data rzg3e_soc_da= ta =3D { }, }; =20 +static const struct rzg3s_pcie_soc_data rzg3l_soc_data =3D { + .power_resets =3D rzg3e_soc_power_resets, + .num_power_resets =3D ARRAY_SIZE(rzg3e_soc_power_resets), + .num_pcie_controllers =3D 1, + .config_pre_init =3D rzg3e_pcie_config_pre_init, + .config_post_init =3D rzg3e_pcie_config_post_init, + .config_deinit =3D rzg3e_pcie_config_deinit, + .sysc_info =3D { + [RZG3S_PCIE_CONTROLLER_ID_0] =3D { + .functions =3D { + [RZG3S_SYSC_FUNC_ID_L1_ALLOW] =3D { + .offset =3D 0x3a0, + .mask =3D BIT(8), + }, + }, + }, + }, +}; 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Tue, 25 Aug 2026 02:50:55 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:81d:57c0:e4cb:959c]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c249629929dsm1749320666b.23.2026.08.25.02.50.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2026 02:50:55 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH 4/4] arm64: dts: renesas: r9a08g046: Add PCIe support Date: Tue, 25 Aug 2026 10:50:43 +0100 Message-ID: <20260825095047.9971-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260825095047.9971-1-biju.das.jz@bp.renesas.com> References: <20260825095047.9971-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Populate the previously placeholder PCIe node for the RZ/G3L (R9A08G046) SoC with interrupts, clocks, resets, interrupt-map, and the PCIe root port's vendor/device ID, and enable it on the RZ/G3L SMARC board with the required pin control, CLKREQ# GPIO hog, and 100 MHz reference clock. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 45 ++++++++++++++++++- .../boot/dts/renesas/r9a08g046l48-smarc.dts | 16 +++++++ .../boot/dts/renesas/rzg3l-smarc-som.dtsi | 11 +++++ 3 files changed, 70 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g046.dtsi index f652ad3f1d1a..83e466ec49ff 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -1480,20 +1480,61 @@ hsusb1: usb@11eb0000 { }; =20 pcie: pcie@11e40000 { + compatible =3D "renesas,r9a08g046-pcie"; reg =3D <0 0x11e40000 0 0x10000>; ranges =3D <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>; + /* Map all possible DRAM ranges (4 GB). */ + dma-ranges =3D <0x42000000 0 0x40000000 0 0x40000000 1 0x00000000>; + bus-range =3D <0x0 0xff>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "serr", "serr_cor", "serr_nonfatal", + "serr_fatal", "axi_err", "inta", + "intb", "intc", "intd", "msi", + "link_bandwidth", "pm_pme", "dma", + "pcie_evt", "msg", "all"; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie 0 0 0 0>, /* INTA */ + <0 0 0 2 &pcie 0 0 0 1>, /* INTB */ + <0 0 0 3 &pcie 0 0 0 2>, /* INTC */ + <0 0 0 4 &pcie 0 0 0 3>; /* INTD */ + clocks =3D <&cpg CPG_MOD R9A08G046_PCI_ACLK>, + <&cpg CPG_MOD R9A08G046_PCI_CLKL1PM>, + <&cpg CPG_MOD R9A08G046_PCI_CLK_PMU>; + clock-names =3D "aclk", "pm", "pmu"; + resets =3D <&cpg R9A08G046_PCI_ARESETN>; + reset-names =3D "aresetn"; + power-domains =3D <&cpg>; device_type =3D "pci"; #address-cells =3D <3>; #size-cells =3D <2>; - /* placeholder */ + renesas,sysc =3D <&sysc>; + status =3D "disabled"; =20 pcie_port0: pcie@0,0 { reg =3D <0x0 0x0 0x0 0x0 0x0>; ranges; device_type =3D "pci"; + vendor-id =3D <0x1912>; + device-id =3D <0x0033>; #address-cells =3D <3>; #size-cells =3D <2>; - /* placeholder */ }; }; =20 diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm6= 4/boot/dts/renesas/r9a08g046l48-smarc.dts index 5a8269c06435..a155967e1f68 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts @@ -170,6 +170,11 @@ &ohci1 { status =3D "okay"; }; =20 +&pcie { + pinctrl-0 =3D <&pcie_pins>; + pinctrl-names =3D "default"; +}; + &phyrst { status =3D "okay"; }; @@ -190,6 +195,17 @@ i2c3_pins: i2c3 { ; /* RIIC3_SDA */ }; =20 + pcie-clkreq-n-hog { + gpio-hog; + gpios =3D ; + output-low; + line-name =3D "PCIE_A_CKREQ"; + }; + + pcie_pins: pcie { + pinmux =3D ; /* PCIE_RST_OUT# */ + }; + rsci1_pins: rsci1 { pinmux =3D , /* RSCI1_RXD_MISO_SCL */ , /* RSCI1_TXD_MOSI_SDA */ diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3l-smarc-som.dtsi index c1c2795bda4e..2ee11d54bd58 100644 --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi @@ -51,6 +51,12 @@ memory@48000000 { reg =3D <0x0 0x48000000 0x0 0x78000000>; }; =20 + pcie_refclk: pcie-ref-clock { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <100000000>; + }; + reg_1p0v: regulator-1p0v { compatible =3D "regulator-fixed"; regulator-name =3D "fixed-1.0V"; @@ -190,6 +196,11 @@ phy1: ethernet-phy@7 { }; }; =20 +&pcie_port0 { + clocks =3D <&pcie_refclk>; + clock-names =3D "ref"; +}; + &pinctrl { eth0_pins: eth0 { txc { --=20 2.43.0