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(unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id C4BCD3F7048; Mon, 24 Aug 2026 21:56:29 -0700 (PDT) From: Ratheesh Kannoth To: , , , , CC: , , , , Ratheesh Kannoth Subject: [PATCH v2 net] octeontx2-af: allocate qmem from page allocator to avoid CMA Date: Tue, 25 Aug 2026 10:26:16 +0530 Message-ID: <20260825045616.3723078-1-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI1MDAzOSBTYWx0ZWRfX1p8abKbtOAkO Tk2C+VTJ0HybzHPzD1P4d7X5kYQ864OH2zJksdzjEGzZvV5PGxdQn/U+XveXlukN3M04CIUVILF fQpi0Oum8tLW/SXx5yGgXMtjS0Cem3XZJLSFzUlwZeZLw8hr1sTPUMyuSDKLzWT7uruSIpCya7z 8XT5Tmwc5XwAcjBeVdvRNKVJiSdn40VRIK0W2d6W41N1UmZPoFVo6aXOK/noIkFtMkei2MJgs8p NF1ESYMR4UP8u3SDitxVCOj2aUNBhvHZnryYCh1L/13cNVLVg6LZR43IFtDiRy7H2yfTEZ6a3vN NJU3SWEgtD/O2dp+g9u/e/2hV5fzp6PZM1QiwlUG1WubzMqcpUm3WUz/jZxmgoqls8fULA5GAhi Oy1YsUQ6CaOA84EcgtFAGMFvusZJDwOlzrNoY7LLMhrau99k9ElmcqdtYCkCcEddFd9IW75atxl 3vRuFcHPu4YbBu5oSQg== X-Proofpoint-ORIG-GUID: 1EkdAQL_88yaepTvOVw3YoX_643a3fG_ X-Proofpoint-Spam-Info: AW1haW4tMjYwODI1MDAzOSBTYWx0ZWRfX4aElZ/nB/az9 3NDrvypT+/4DEfWkxU5EN6zvUZPypsJdPgvgh9ui+Cle3AxyA84CmkLm/5M5dvPqQsc7Vi31QAG OsKuoVgwxLORI3jtHdXGEspMycKibFw= X-Proofpoint-GUID: 1EkdAQL_88yaepTvOVw3YoX_643a3fG_ X-Authority-Analysis: v=2.4 cv=A95c+aWG c=1 sm=1 tr=0 ts=6a8d2081 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=qit2iCtTFQkLgVSMPQTB:22 a=M5GUcnROAAAA:8 a=JB0Lc2itZwj43V2tWJ8A:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-25_01,2026-08-24_01,2025-10-01_01 Content-Type: text/plain; charset="utf-8" qmem_alloc() uses dma_alloc_attrs() with DMA_ATTR_FORCE_CONTIGUOUS so CN10K LMTST regions get physically contiguous DMA memory across page boundaries. On platforms with CMA enabled, that attribute causes allocations to be drawn from the CMA pool. qmem is used for NIX and NPA queue contexts, admin queues, and LMTST regions, so the footprint grows with the number of enabled interfaces and is difficult to provision in CMA. Add otx2_dma_alloc_coherent() and otx2_dma_free_coherent() helpers that allocate compound pages with __get_free_pages(__GFP_COMP), DMA-map them with dma_map_page(), and retry with GFP_DMA32 when the physical address exceeds the device DMA mask. Switch qmem_alloc() and qmem_free() to use them instead of dma_alloc_attrs()/dma_free_attrs(). Fixes: 73d33dbc0723 ("octeontx2-af: Use DMA_ATTR_FORCE_CONTIGUOUS attribute= in DMA alloc") Signed-off-by: Ratheesh Kannoth --- .../ethernet/marvell/octeontx2/af/common.h | 79 +++++++++++++++++-- 1 file changed, 73 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/common.h b/drivers/n= et/ethernet/marvell/octeontx2/af/common.h index 779413a383b7..30dd882a0149 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/common.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/common.h @@ -7,6 +7,10 @@ #ifndef COMMON_H #define COMMON_H =20 +#include +#include +#include + #include "rvu_struct.h" =20 #define OTX2_ALIGN 128 /* Align to cacheline */ @@ -44,6 +48,70 @@ struct qmem { u32 qsize; }; =20 +/* dma_alloc_coherent()/dma_free_coherent() equivalents backed by + * __get_free_pages(). The region is mapped for DMA with + * dma_map_page()/dma_unmap_page(). + */ +static inline void *otx2_dma_alloc_coherent(struct device *dev, size_t siz= e, + dma_addr_t *dma_handle, gfp_t gfp) +{ + dma_addr_t dma_addr; + unsigned int order; + phys_addr_t paddr; + struct page *page; + void *vaddr; + u64 mask; + + if (!dev || !dma_handle || !size) + return NULL; + + size =3D PAGE_ALIGN(size); + order =3D get_order(size); + if (order > MAX_PAGE_ORDER) + return NULL; + + gfp |=3D __GFP_COMP | __GFP_ZERO | __GFP_RECLAIM; + vaddr =3D (void *)__get_free_pages(gfp, order); + if (!vaddr) + return NULL; + + paddr =3D virt_to_phys((void *)vaddr); + mask =3D dma_get_required_mask(dev); + if (paddr + size > mask) { + free_pages((unsigned long)vaddr, order); + gfp |=3D GFP_DMA32; + + vaddr =3D (void *)__get_free_pages(gfp, order); + if (!vaddr) + return NULL; + } + + page =3D virt_to_page(vaddr); + dma_addr =3D dma_map_page(dev, page, 0, size, DMA_BIDIRECTIONAL); + if (dma_mapping_error(dev, dma_addr)) { + free_pages((unsigned long)vaddr, order); + return NULL; + } + + *dma_handle =3D dma_addr; + return vaddr; +} + +static inline void otx2_dma_free_coherent(struct device *dev, size_t size, + void *vaddr, dma_addr_t dma_handle) +{ + unsigned int order; + + if (!dev || !vaddr) + return; + + size =3D PAGE_ALIGN(size); + order =3D get_order(size); + + dma_unmap_page(dev, dma_handle, size, DMA_BIDIRECTIONAL); + free_pages((unsigned long)vaddr, order); +} + static inline int qmem_alloc(struct device *dev, struct qmem **q, int qsize, int entry_sz) { @@ -60,8 +128,8 @@ static inline int qmem_alloc(struct device *dev, struct = qmem **q, =20 qmem->entry_sz =3D entry_sz; qmem->alloc_sz =3D (qsize * entry_sz) + OTX2_ALIGN; - qmem->base =3D dma_alloc_attrs(dev, qmem->alloc_sz, &qmem->iova, - GFP_KERNEL, DMA_ATTR_FORCE_CONTIGUOUS); + qmem->base =3D otx2_dma_alloc_coherent(dev, qmem->alloc_sz, &qmem->iova, + GFP_KERNEL); if (!qmem->base) return -ENOMEM; =20 @@ -80,10 +148,9 @@ static inline void qmem_free(struct device *dev, struct= qmem *qmem) return; =20 if (qmem->base) - dma_free_attrs(dev, qmem->alloc_sz, - qmem->base - qmem->align, - qmem->iova - qmem->align, - DMA_ATTR_FORCE_CONTIGUOUS); + otx2_dma_free_coherent(dev, qmem->alloc_sz, + qmem->base - qmem->align, + qmem->iova - qmem->align); devm_kfree(dev, qmem); } =20 --=20 2.43.0