From nobody Mon Sep 28 07:19:28 2026 Received: from mailgw.kylinos.cn (mailgw.kylinos.cn [124.126.103.232]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A154431E83D; Tue, 25 Aug 2026 03:04:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=124.126.103.232 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787627084; cv=none; b=Ir+kZFpF3iJdb1F/BPcFHYN4ODbxuaFYYNnxvLo0QZWlmsM6fFgwS0uT3SsNW6KxnFudbr40kMAECvIjr6UNa9xfctly6KwNJVdEDT0/85eeybKucOrv3XY07alrHZiCj5FUCT2AhctZgJ0L1bwbXH6PMxhdh7Is1jdYNReuVV0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787627084; c=relaxed/simple; bh=LDVKCl9xnRdaHD0QyE89Auqs9r1GM3GUFHBCM1tYarI=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=lhbFUVJETKos+lkrhvHa2DT1yizCzfMnBS3SmancaA+/YBN5OrZ28yDarp0/A7vKsZxgu3pq6b330qaY+cnh/kIKKWZEiotQ9QfdgtBj+i4b2ehJnO5vhfA1wvurz+n/GzV+c+bxUSebv8QT+0zULYAVtN9RoawQ0G/MJpsnc2s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=kylinos.cn; spf=pass smtp.mailfrom=kylinos.cn; arc=none smtp.client-ip=124.126.103.232 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=kylinos.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=kylinos.cn X-UUID: b3278c24a03111f19a56ed5b684f684d-20260825 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.19,REQID:2d521c89-581e-4123-a5a2-2f518536c277,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:7db8b62,CLOUDID:f06b2223ccfdcd4bff206c0a831a7e0c,BulkI D:nil,BulkQuantity:0,SF:102|850|865|898,TC:nil,Content:0|15|50,EDM:-3,IP:n il,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LE S:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: b3278c24a03111f19a56ed5b684f684d-20260825 X-User: gonglinkai@kylinos.cn Received: from localhost.localdomain [(10.44.16.150)] by mailgw.kylinos.cn (envelope-from ) (Generic MTA with TLSv1.3 TLS_AES_256_GCM_SHA384 256/256) with ESMTP id 1991166085; Tue, 25 Aug 2026 11:04:34 +0800 From: Linkai Gong To: Basavaraj Natikar , Shyam Sundar S K , Linus Walleij Cc: Daniel Kurtz , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, gonglinkai@kylinos.cn Subject: [PATCH] pinctrl: amd: add timeout to irq-enable readback Date: Tue, 25 Aug 2026 11:04:28 +0800 Message-Id: <20260825030428.1685182-1-gonglinkai@kylinos.cn> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" amd_gpio_irq_set_type() polls INTERRUPT_ENABLE with IRQs off and no timeout. Use readl_poll_timeout_atomic() and return -ETIMEDOUT. Fixes: b85bfa246efd ("pinctrl/amd: poll InterruptEnable bits in amd_gpio_ir= q_set_type") Signed-off-by: Linkai Gong --- drivers/pinctrl/pinctrl-amd.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 15a398bb3be2..65728b590999 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -494,7 +495,7 @@ static void amd_gpio_irq_eoi(struct irq_data *d) static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) { int ret =3D 0; - u32 pin_reg, pin_reg_irq_en, mask; + u32 pin_reg, pin_reg_irq_en, mask, reg; unsigned long flags; struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct amd_gpio *gpio_dev =3D gpiochip_get_data(gc); @@ -568,8 +569,9 @@ static int amd_gpio_irq_set_type(struct irq_data *d, un= signed int type) pin_reg_irq_en |=3D mask; pin_reg_irq_en &=3D ~BIT(INTERRUPT_MASK_OFF); writel(pin_reg_irq_en, gpio_dev->base + hwirq * 4); - while ((readl(gpio_dev->base + hwirq * 4) & mask) !=3D mask) - continue; + if (readl_poll_timeout_atomic(gpio_dev->base + hwirq * 4, reg, + (reg & mask) =3D=3D mask, 1, 1000)) + ret =3D -ETIMEDOUT; writel(pin_reg, gpio_dev->base + hwirq * 4); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); =20 --=20 2.25.1