From nobody Mon Sep 28 06:35:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C456442FCE; Tue, 25 Aug 2026 12:37:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787661454; cv=none; b=I3RCjwyZSXIcO/rwasfSiYYWelWPvWjJJ8U8/+XW4iVsF0hmFKJXZHEY/w9Buc6i+4mtTT8VZ/OaWNeXp1lkZFhgoKa+OYuKa7daSYqhyW/18sqfWLbVTT3KRiwop+Scd9DUiW63dYqy6WEdP9GlPUUh6twW3Kn7n9EMXGKxKls= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787661454; c=relaxed/simple; bh=Fvem3S/s8weQhv29yD3FxDRPYmYvuo32XVi3h1fP+i8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HeOij0Lp6n3QAlzLAHxTsHYv4mcwmD+uLWFJhgZVTp5F4lmVYOfP9KJPBw3DzYCfVAkxRJlOeng3hUk8jU3gogLp9QpZ0j3L58te3ldjnyRS+0DIhiET5sZUsrk+3FLyTbBb493XXWKO/8cTgSRMQ7OqqaHLxgGP0cCCol1icIA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=LGJEMGcL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LGJEMGcL" Received: by smtp.kernel.org (Postfix) with ESMTPS id ED453C2BCFA; Tue, 25 Aug 2026 12:37:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787661453; bh=Fvem3S/s8weQhv29yD3FxDRPYmYvuo32XVi3h1fP+i8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=LGJEMGcLvFnb2sWI3ScamBYhxIKBZIeO8RQMXXDvVla0rlMMg6ndPGJchGdulAvV/ 29tF0wbL3+VGHSSP/znHy8UTiQL6DOA6IHzWd+RtXyp+MJxFjU1oSOnLXd/ftfQpG6 X7gRglMz14dEn73A53UwyxfLvYM2twbpXxsxB+qIQeKJuZ1/xpQzxb/bTCaLLEftRj 5BpX67shz6oEKijv2kxVuCPOTcF5bqpamd1CReCGo2M0BsXv2hxxm8RmL7xaAjGj2z liorQJOE0Ud62smvPDM5U0OrxBCoXh/33OxSebAp7FF5E0MDyRWZF9cyHhQ0wGvcpZ LDT4XsZ+ASJMQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C71D0C61DBE; Tue, 25 Aug 2026 12:37:32 +0000 (UTC) From: George Moussalem via B4 Relay Date: Tue, 25 Aug 2026 16:37:18 +0400 Subject: [PATCH v3 01/12] dt-bindings: phy: qcom,ipq5332-uniphy-pcie: Change to PCIe/USB3 combo PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260825-ipq5018-usb3-v3-1-39be0955a6aa@outlook.com> References: <20260825-ipq5018-usb3-v3-0-39be0955a6aa@outlook.com> In-Reply-To: <20260825-ipq5018-usb3-v3-0-39be0955a6aa@outlook.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Praveenkumar I , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Varadarajan Narayanan , Nitheesh Sekar , Wesley Cheng , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787661450; l=7815; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=+Cf/fEtBtS5hTFBthO9VA7YZ1YWg8gWCwEnzEp4khVM=; b=QGGfI18EJcCkeq6dGsPRHELd+S+u0Bap8yJuo3Usxev29C+KAZjyFt6yCCH42rU4HfmnLTrZQ Zm1NGidRlWKBLCvqHcJEfXreuM8iKzPctnwCtAd33ndnJnw2hNhznnz X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem This PHY is a PCIE/USB3 multi-purpose PHY. Initial support was added for PCIe only, so rename the binding and add support for USB3 PHY mode. The PCIe and USB physical pads are muxed and selection is done via a control register in TCSR. Add a new property to the binding to enable switching the default PCIe mux selection to USB3 mode. In addition, USB3 mode requires a 5V supply, so add a vdd-supply property for it. Signed-off-by: George Moussalem Tested-by: Stanislaw Pal --- .../bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml | 109 ---------------- .../phy/qcom,ipq5332-uniphy-pcie-usb3-phy.yaml | 141 +++++++++++++++++= ++++ include/dt-bindings/phy/phy-qcom-qmp.h | 4 + 3 files changed, 145 insertions(+), 109 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie= -phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-= phy.yaml deleted file mode 100644 index 6e9df81441e9..000000000000 --- a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.ya= ml +++ /dev/null @@ -1,109 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-pcie-phy.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm UNIPHY PCIe 28LP PHY - -maintainers: - - Nitheesh Sekar - - Varadarajan Narayanan - -description: - PCIe and USB combo PHY found in Qualcomm IPQ5018 & IPQ5332 SoCs - -properties: - compatible: - enum: - - qcom,ipq5018-uniphy-pcie-phy - - qcom,ipq5332-uniphy-pcie-phy - - reg: - maxItems: 1 - - clocks: - minItems: 1 - maxItems: 2 - - resets: - minItems: 2 - maxItems: 3 - - "#phy-cells": - const: 0 - - "#clock-cells": - const: 0 - - num-lanes: - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [1, 2] - -required: - - compatible - - reg - - clocks - - resets - - "#phy-cells" - - "#clock-cells" - - num-lanes - -additionalProperties: false - -allOf: - - if: - properties: - compatible: - contains: - enum: - - qcom,ipq5018-uniphy-pcie-phy - then: - properties: - clocks: - items: - - description: pcie pipe clock - resets: - items: - - description: phy reset - - description: cfg reset - - - if: - properties: - compatible: - contains: - enum: - - qcom,ipq5332-uniphy-pcie-phy - then: - properties: - clocks: - items: - - description: pcie pipe clock - - description: pcie ahb clock - resets: - items: - - description: phy reset - - description: ahb reset - - description: cfg reset - -examples: - - | - #include - - pcie0_phy: phy@4b0000 { - compatible =3D "qcom,ipq5332-uniphy-pcie-phy"; - reg =3D <0x004b0000 0x800>; - - clocks =3D <&gcc GCC_PCIE3X1_0_PIPE_CLK>, - <&gcc GCC_PCIE3X1_PHY_AHB_CLK>; - - resets =3D <&gcc GCC_PCIE3X1_0_PHY_BCR>, - <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>, - <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>; - - #clock-cells =3D <0>; - - #phy-cells =3D <0>; - - num-lanes =3D <1>; - }; diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie= -usb3-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-= pcie-usb3-phy.yaml new file mode 100644 index 000000000000..0d9d0fb405b6 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-usb3-p= hy.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-pcie-usb3-phy.y= aml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ5332 UNIPHY PCIe/USB3 28LP PHY controller + +maintainers: + - Nitheesh Sekar + - Varadarajan Narayanan + +description: + The QMP PHY controller supports physical layer functionality for PCIe an= d USB + controllers on Qualcomm IPQ5018 & IPQ5332 chipsets. + +properties: + compatible: + enum: + - qcom,ipq5018-uniphy-pcie-phy + - qcom,ipq5332-uniphy-pcie-phy + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + maxItems: 4 + + resets: + minItems: 1 + maxItems: 4 + + reset-names: + maxItems: 4 + + num-lanes: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2] + + vdd-supply: + description: + Phandle to 5V regulator supply to PHY digital circuit. + + qcom,phy-usb-mux-sel: + description: + TCSR register address for mux selection control for PCIe / USB3 mode. + If the property is set, the driver will configure USB3 mux selection. + If not set, the setting defaults to PCIe mux selection (BIT(0) =3D 0= ). + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle of TCSR syscon + - description: offset of PHY mux selection register + + "#clock-cells": + enum: [0, 1] + + "#phy-cells": + enum: [0, 1] + +required: + - compatible + - reg + - clocks + - resets + - "#clock-cells" + - "#phy-cells" + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5018-uniphy-pcie-phy + then: + properties: + clocks: + items: + - description: pcie pipe clock + resets: + items: + - description: pcie phy reset + - description: pcie cfg reset + "#clock-cells": + const: 0 + "#phy-cells": + const: 0 + required: + - num-lanes + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5332-uniphy-pcie-phy + then: + properties: + clocks: + items: + - description: pcie pipe clock + - description: pcie ahb clock + resets: + items: + - description: pcie phy reset + - description: pcie ahb reset + - description: pcie cfg reset + "#clock-cells": + const: 0 + "#phy-cells": + const: 0 + required: + - num-lanes + +additionalProperties: false + +examples: + - | + #include + + pcie1_phy: phy@4b1000 { + compatible =3D "qcom,ipq5332-uniphy-pcie-phy"; + reg =3D <0x004b1000 0x800>; + + clocks =3D <&gcc GCC_PCIE3X2_PIPE_CLK>, + <&gcc GCC_PCIE3X2_PHY_AHB_CLK>; + + resets =3D <&gcc GCC_PCIE3X2_PHY_BCR>, + <&gcc GCC_PCIE3X2_PHY_AHB_CLK_ARES>, + <&gcc GCC_PCIE3X2PHY_PHY_BCR>; + + #clock-cells =3D <0>; + #phy-cells =3D <0>; + + num-lanes =3D <2>; + }; diff --git a/include/dt-bindings/phy/phy-qcom-qmp.h b/include/dt-bindings/p= hy/phy-qcom-qmp.h index 6b43ea9e0051..a19f7376b15e 100644 --- a/include/dt-bindings/phy/phy-qcom-qmp.h +++ b/include/dt-bindings/phy/phy-qcom-qmp.h @@ -21,4 +21,8 @@ #define QMP_PCIE_PIPE_CLK 0 #define QMP_PCIE_PHY_AUX_CLK 1 =20 +/* QMP PHY MUX */ +#define QMP_PHY_MUX_PCIE 0 +#define QMP_PHY_MUX_USB3 1 + #endif /* _DT_BINDINGS_PHY_QMP */ --=20 2.53.0 From nobody Mon Sep 28 06:35:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EAD5445AF7; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260825-ipq5018-usb3-v3-2-39be0955a6aa@outlook.com> References: <20260825-ipq5018-usb3-v3-0-39be0955a6aa@outlook.com> In-Reply-To: <20260825-ipq5018-usb3-v3-0-39be0955a6aa@outlook.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Praveenkumar I , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Varadarajan Narayanan , Nitheesh Sekar , Wesley Cheng , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787661450; l=1847; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=X92ejnhwDPtga79pHvMyqYjnXONSziO0EJioVCS0ABA=; b=m2T5qx7FPQMNTLk6lhedEpBLyrSqTSMrw5CpPDaxTCtZaJUi54zkvLB+c4zokXIz766afBBvE 7EenPiSHMiUCWe/aRlPY1IDzvQQ59R5jdMNVESIXmlesBZs0nsu2Y2F X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Describe the USB3 PHY found in the IPQ5018 SoC so add the compatible string for it as well as the required resources (clocks and resets). The PCIe and USB physical pads are muxed and selection is done via a control register in TCSR. By default, PCIe mode is selected, hence make the property for USB mux selection required. In addition, the PHY requires a 5V supply for USB3 mode operation. Signed-off-by: George Moussalem Tested-by: Stanislaw Pal --- .../phy/qcom,ipq5332-uniphy-pcie-usb3-phy.yaml | 24 ++++++++++++++++++= ++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie= -usb3-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-= pcie-usb3-phy.yaml index 0d9d0fb405b6..1cd5392a1a0f 100644 --- a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-usb3-p= hy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-usb3-p= hy.yaml @@ -18,6 +18,7 @@ properties: compatible: enum: - qcom,ipq5018-uniphy-pcie-phy + - qcom,ipq5018-uniphy-usb3-phy - qcom,ipq5332-uniphy-pcie-phy =20 reg: @@ -93,6 +94,29 @@ allOf: required: - num-lanes =20 + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5018-uniphy-usb3-phy + then: + properties: + clocks: + items: + - description: usb3 pipe clock + - description: usb3 cfg ahb clock + resets: + items: + - description: usb3 phy reset + "#clock-cells": + const: 0 + "#phy-cells": + const: 0 + required: + - vdd-supply + - qcom,phy-usb-mux-sel + - if: properties: compatible: --=20 2.53.0 From nobody Mon Sep 28 06:35:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9AD44426D0C; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WSgOEFaS" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1A531C32786; Tue, 25 Aug 2026 12:37:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787661453; bh=j5WGDZq4JFhhRkNnOtlgnMroG1FmpIpiWmK2eo2bQ9Y=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=WSgOEFaSpM/OMAjeXY1/ebR/c20kAD/M996R04ZPZ/+5Y8IbROI4wMZzcVA7XJotk k9DVTBfVxouhe3Dl4rz/ScZ6PBx+Pgdvlj75t2Hd+5BTRSuKJRu1YO0zESoO1jLEtH Km/uNDHiZnUwy1fTPEGDajf8uiwDA9KSkTJIgMinhw3br8+tcBqEAv366SHT29Dy/r sBn+BEe5ZGD2yNx1QS9m8/1uPb7+cf26Bq4jVd2qXVkGd1rU5ZewJa8NwcuRF+ATcr XhKM4A8b/wptMB0Tx+VSYZADqQAXcpa83YzTvqYQm76k1LE/FLnrVgxGUUEjK2mttf bHvGWVFf4W1Gg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E94DCC61DC6; Tue, 25 Aug 2026 12:37:32 +0000 (UTC) From: George Moussalem via B4 Relay Date: Tue, 25 Aug 2026 16:37:20 +0400 Subject: [PATCH v3 03/12] phy: qualcomm: qcom-uniphy-pcie-28lp: Convert to PCIe/USB3 combo PHY driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260825-ipq5018-usb3-v3-3-39be0955a6aa@outlook.com> References: <20260825-ipq5018-usb3-v3-0-39be0955a6aa@outlook.com> In-Reply-To: <20260825-ipq5018-usb3-v3-0-39be0955a6aa@outlook.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Praveenkumar I , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Varadarajan Narayanan , Nitheesh Sekar , Wesley Cheng , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787661450; l=10621; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=0yuZk82tzQfyVclB/GgiAcNvs78YUKjs9vvJMW3iyVM=; b=/pmvVrLJ6Un6MrwUYxtGn6H/WfZktRg6pUnH0HzlKDelB0n7Do30f5r+ZJRdrLKEBeGwIUm6r JWShDzGzv7WApInEnTaKFCHgKE38Y1i7fc5vKgvvSIT9Lfq0oG9vbnU X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem This PHY found in IPQ5332 and IPQ5018 SoCs is actually a multi-purpose PCIe/USB3 combo PHY. The driver was initially created for PCIe PHY support only. As such, rename the driver and generalize function and struct names to reflect that it is a PCIe and USB3 combo PHY driver so that USB3 support can be added in subsequent patches. Signed-off-by: George Moussalem Reviewed-by: Konrad Dybcio Tested-by: Stanislaw Pal --- drivers/phy/qualcomm/Kconfig | 24 +++--- drivers/phy/qualcomm/Makefile | 2 +- ...cie-28lp.c =3D> phy-qcom-uniphy-pcie-usb3-28lp.c} | 87 +++++++++++-----= ------ 3 files changed, 55 insertions(+), 58 deletions(-) diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index d910a5d1a1ac..6872aa919cf2 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -155,19 +155,6 @@ config PHY_QCOM_M31_USB management. This driver is required even for peripheral only or host only mode configurations. =20 -config PHY_QCOM_UNIPHY_PCIE_28LP - bool "PCIE UNIPHY 28LP PHY driver" - depends on ARCH_QCOM - depends on COMMON_CLK - depends on HAS_IOMEM - depends on OF - select GENERIC_PHY - help - Enable this to support the PCIe UNIPHY 28LP phy transceiver that - is used with PCIe controllers on Qualcomm IPQ5332 chips. It - handles PHY initialization, clock management required after - resetting the hardware and power management. - config PHY_QCOM_M31_EUSB tristate "Qualcomm M31 eUSB2 PHY driver support" depends on USB && (ARCH_QCOM || COMPILE_TEST) @@ -178,6 +165,17 @@ config PHY_QCOM_M31_EUSB up of the associated USB repeater that is paired with the eUSB2 PHY. =20 +config PHY_QCOM_UNIPHY_PCIE_USB3_28LP + bool "Qualcomm IPQ5332 UNIPHY PCIe USB3 28LP PHY driver" + depends on OF && (ARCH_QCOM || COMPILE_TEST) + select GENERIC_PHY + select MFD_SYSCON + help + Enable this to support the Qualcomm USB Super-Speed UNIPHY transceiver + that is used on Qualcomm IPQ5018 and IPQ5332 SoCs with DWC3 USB core. + It handles PHY initialization, clock management required after + resetting the hardware and power management. + config PHY_QCOM_USB_HS tristate "Qualcomm USB HS PHY module" depends on USB_ULPI_BUS diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index 8bf887d58ee4..6e2e9737e387 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -18,7 +18,7 @@ obj-$(CONFIG_PHY_QCOM_QMP_USB_LEGACY) +=3D phy-qcom-qmp-u= sb-legacy.o =20 obj-$(CONFIG_PHY_QCOM_QUSB2) +=3D phy-qcom-qusb2.o obj-$(CONFIG_PHY_QCOM_EUSB2_REPEATER) +=3D phy-qcom-eusb2-repeater.o -obj-$(CONFIG_PHY_QCOM_UNIPHY_PCIE_28LP) +=3D phy-qcom-uniphy-pcie-28lp.o +obj-$(CONFIG_PHY_QCOM_UNIPHY_PCIE_USB3_28LP) +=3D phy-qcom-uniphy-pcie-usb= 3-28lp.o obj-$(CONFIG_PHY_QCOM_USB_HS) +=3D phy-qcom-usb-hs.o obj-$(CONFIG_PHY_QCOM_USB_HSIC) +=3D phy-qcom-usb-hsic.o obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) +=3D phy-qcom-usb-hs-28nm.o diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c b/drivers/phy= /qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c similarity index 75% rename from drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c rename to drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c index 324c0a5d658e..aeb8f7ddbd7a 100644 --- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c +++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c @@ -43,29 +43,29 @@ #define PHY_CFG_EIOS_DTCT_REG 0x3e4 #define PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME 0x3e8 =20 -enum qcom_uniphy_pcie_type { +enum qcom_uniphy_type { PHY_TYPE_PCIE =3D 1, PHY_TYPE_PCIE_GEN2, PHY_TYPE_PCIE_GEN3, }; =20 -struct qcom_uniphy_pcie_regs { +struct qcom_uniphy_regs { u32 offset; u32 val; }; =20 -struct qcom_uniphy_pcie_data { +struct qcom_uniphy_data { int lane_offset; /* offset between the lane register bases */ u32 phy_type; - const struct qcom_uniphy_pcie_regs *init_seq; + const struct qcom_uniphy_regs *init_seq; u32 init_seq_num; u32 pipe_clk_rate; }; =20 -struct qcom_uniphy_pcie { +struct qcom_uniphy { struct phy phy; struct device *dev; - const struct qcom_uniphy_pcie_data *data; + const struct qcom_uniphy_data *data; struct clk_bulk_data *clks; int num_clks; struct reset_control *resets; @@ -73,9 +73,9 @@ struct qcom_uniphy_pcie { int lanes; }; =20 -#define phy_to_dw_phy(x) container_of((x), struct qca_uni_pcie_phy, phy) +#define phy_to_dw_phy(x) container_of((x), struct qcom_uniphy, phy) =20 -static const struct qcom_uniphy_pcie_regs ipq5018_regs[] =3D { +static const struct qcom_uniphy_regs ipq5018_pcie_regs[] =3D { { .offset =3D SSCG_CTRL_REG_4, .val =3D 0x1cb9, @@ -109,7 +109,7 @@ static const struct qcom_uniphy_pcie_regs ipq5018_regs[= ] =3D { }, }; =20 -static const struct qcom_uniphy_pcie_regs ipq5332_regs[] =3D { +static const struct qcom_uniphy_regs ipq5332_pcie_regs[] =3D { { .offset =3D PHY_CFG_PLLCFG, .val =3D 0x30, @@ -122,26 +122,26 @@ static const struct qcom_uniphy_pcie_regs ipq5332_reg= s[] =3D { }, }; =20 -static const struct qcom_uniphy_pcie_data ipq5018_data =3D { +static const struct qcom_uniphy_data ipq5018_data =3D { .lane_offset =3D 0x800, .phy_type =3D PHY_TYPE_PCIE_GEN2, - .init_seq =3D ipq5018_regs, - .init_seq_num =3D ARRAY_SIZE(ipq5018_regs), + .init_seq =3D ipq5018_pcie_regs, + .init_seq_num =3D ARRAY_SIZE(ipq5018_pcie_regs), .pipe_clk_rate =3D 125 * MEGA, }; =20 -static const struct qcom_uniphy_pcie_data ipq5332_data =3D { +static const struct qcom_uniphy_data ipq5332_data =3D { .lane_offset =3D 0x800, .phy_type =3D PHY_TYPE_PCIE_GEN3, - .init_seq =3D ipq5332_regs, - .init_seq_num =3D ARRAY_SIZE(ipq5332_regs), + .init_seq =3D ipq5332_pcie_regs, + .init_seq_num =3D ARRAY_SIZE(ipq5332_pcie_regs), .pipe_clk_rate =3D 250 * MEGA, }; =20 -static void qcom_uniphy_pcie_init(struct qcom_uniphy_pcie *phy) +static void qcom_uniphy_pcie_usb3_init(struct qcom_uniphy *phy) { - const struct qcom_uniphy_pcie_data *data =3D phy->data; - const struct qcom_uniphy_pcie_regs *init_seq; + const struct qcom_uniphy_data *data =3D phy->data; + const struct qcom_uniphy_regs *init_seq; void __iomem *base =3D phy->base; int lane, i; =20 @@ -155,18 +155,18 @@ static void qcom_uniphy_pcie_init(struct qcom_uniphy_= pcie *phy) } } =20 -static int qcom_uniphy_pcie_power_off(struct phy *x) +static int qcom_uniphy_pcie_usb3_power_off(struct phy *x) { - struct qcom_uniphy_pcie *phy =3D phy_get_drvdata(x); + struct qcom_uniphy *phy =3D phy_get_drvdata(x); =20 clk_bulk_disable_unprepare(phy->num_clks, phy->clks); =20 return reset_control_assert(phy->resets); } =20 -static int qcom_uniphy_pcie_power_on(struct phy *x) +static int qcom_uniphy_pcie_usb3_power_on(struct phy *x) { - struct qcom_uniphy_pcie *phy =3D phy_get_drvdata(x); + struct qcom_uniphy *phy =3D phy_get_drvdata(x); int ret; =20 ret =3D reset_control_assert(phy->resets); @@ -193,13 +193,13 @@ static int qcom_uniphy_pcie_power_on(struct phy *x) =20 usleep_range(CLK_EN_DELAY_MIN_US, CLK_EN_DELAY_MAX_US); =20 - qcom_uniphy_pcie_init(phy); + qcom_uniphy_pcie_usb3_init(phy); =20 return 0; } =20 -static inline int qcom_uniphy_pcie_get_resources(struct platform_device *p= dev, - struct qcom_uniphy_pcie *phy) +static inline int qcom_uniphy_pcie_usb3_get_resources(struct platform_devi= ce *pdev, + struct qcom_uniphy *phy) { struct resource *res; =20 @@ -236,9 +236,9 @@ static inline int qcom_uniphy_pcie_get_resources(struct= platform_device *pdev, * clk | +-------+ | +-----+ * +---------------+ */ -static inline int phy_pipe_clk_register(struct qcom_uniphy_pcie *phy, int = id) +static inline int phy_pipe_clk_register(struct qcom_uniphy *phy, int id) { - const struct qcom_uniphy_pcie_data *data =3D phy->data; + const struct qcom_uniphy_data *data =3D phy->data; struct clk_hw *hw; char name[64]; =20 @@ -252,30 +252,29 @@ static inline int phy_pipe_clk_register(struct qcom_u= niphy_pcie *phy, int id) return devm_of_clk_add_hw_provider(phy->dev, of_clk_hw_simple_get, hw); } =20 -static const struct of_device_id qcom_uniphy_pcie_id_table[] =3D { +static const struct of_device_id qcom_uniphy_pcie_usb3_id_table[] =3D { { .compatible =3D "qcom,ipq5018-uniphy-pcie-phy", .data =3D &ipq5018_data, }, { .compatible =3D "qcom,ipq5332-uniphy-pcie-phy", .data =3D &ipq5332_data, - }, { - /* Sentinel */ }, + { }, }; -MODULE_DEVICE_TABLE(of, qcom_uniphy_pcie_id_table); +MODULE_DEVICE_TABLE(of, qcom_uniphy_pcie_usb3_id_table); =20 -static const struct phy_ops pcie_ops =3D { - .power_on =3D qcom_uniphy_pcie_power_on, - .power_off =3D qcom_uniphy_pcie_power_off, +static const struct phy_ops qcom_uniphy_ops =3D { + .power_on =3D qcom_uniphy_pcie_usb3_power_on, + .power_off =3D qcom_uniphy_pcie_usb3_power_off, .owner =3D THIS_MODULE, }; =20 -static int qcom_uniphy_pcie_probe(struct platform_device *pdev) +static int qcom_uniphy_pcie_usb3_probe(struct platform_device *pdev) { struct phy_provider *phy_provider; struct device *dev =3D &pdev->dev; - struct qcom_uniphy_pcie *phy; + struct qcom_uniphy *phy; struct phy *generic_phy; int ret; =20 @@ -294,12 +293,12 @@ static int qcom_uniphy_pcie_probe(struct platform_dev= ice *pdev) if (ret) return dev_err_probe(dev, ret, "Couldn't read num-lanes\n"); =20 - ret =3D qcom_uniphy_pcie_get_resources(pdev, phy); + ret =3D qcom_uniphy_pcie_usb3_get_resources(pdev, phy); if (ret < 0) return dev_err_probe(&pdev->dev, ret, "failed to get resources: %d\n", ret); =20 - generic_phy =3D devm_phy_create(phy->dev, NULL, &pcie_ops); + generic_phy =3D devm_phy_create(phy->dev, NULL, &qcom_uniphy_ops); if (IS_ERR(generic_phy)) return PTR_ERR(generic_phy); =20 @@ -317,15 +316,15 @@ static int qcom_uniphy_pcie_probe(struct platform_dev= ice *pdev) return 0; } =20 -static struct platform_driver qcom_uniphy_pcie_driver =3D { - .probe =3D qcom_uniphy_pcie_probe, +static struct platform_driver qcom_uniphy_pcie_usb3_driver =3D { + .probe =3D qcom_uniphy_pcie_usb3_probe, .driver =3D { - .name =3D "qcom-uniphy-pcie", - .of_match_table =3D qcom_uniphy_pcie_id_table, + .name =3D "qcom-uniphy-pcie-usb3-28lp", + .of_match_table =3D qcom_uniphy_pcie_usb3_id_table, }, }; =20 -module_platform_driver(qcom_uniphy_pcie_driver); +module_platform_driver(qcom_uniphy_pcie_usb3_driver); =20 -MODULE_DESCRIPTION("PCIE QCOM UNIPHY driver"); +MODULE_DESCRIPTION("Qualcomm IPQ5332 UNIPHY PCIe USB3 28LP PHY driver"); MODULE_LICENSE("GPL"); --=20 2.53.0 From nobody Mon Sep 28 06:35:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C32E42AFAC; Tue, 25 Aug 2026 12:37:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787661454; cv=none; b=qrqk9uYnK34lOiGikneAojOe6oWmYlhqtmcrYw7abXKOCASaHF2855HuFYQPIEFoFRvHGl5ejWUFTu6MFSRQPtrI3v9N72HYFAvEoexJ7ynSEb9RXG1jADJdCkF1QNGqAWq71F6RPMx2PGRwIRHrgRLZ9NPHmxQv77Xc/q3anUc= ARC-Message-Signature: i=1; a=rsa-sha256; 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b=C22P4iqxvGv+DRv0oRYrskllnfgn/X8ZGr296+k6MS5zp0/0G3e1wo/Cf17zjQA80 tW0uqu05DD86JVHqJntzN1ZXxhp68amTUw9YSbhu4WTl+GXyJt1o+xe4VALtHoDms5 DWYUi9tD26Pdw7WSpYBZPKYVQdbX1ADi+A6LonVmRkJfJymi8D/Ju14c80vy2ff6sE 1YttUn0B7i+ahz7uilItBvIMQFSukjCDBoicnGyTmloij2eoD4YcKtpeM9X5u2tJ/n JfbLseSz4FDgoeWKBICAHz7UKFJ03Tnba4qrjl7F/HZt6tmBjGkhhov8oFNwaL9RJJ UTX6363oEmOGg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04D62C61DC4; Tue, 25 Aug 2026 12:37:33 +0000 (UTC) From: George Moussalem via B4 Relay Date: Tue, 25 Aug 2026 16:37:21 +0400 Subject: [PATCH v3 04/12] phy: qualcomm: qcom-uniphy-pcie-usb3-28lp: Refactor init regs table definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260825-ipq5018-usb3-v3-4-39be0955a6aa@outlook.com> References: <20260825-ipq5018-usb3-v3-0-39be0955a6aa@outlook.com> In-Reply-To: <20260825-ipq5018-usb3-v3-0-39be0955a6aa@outlook.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Praveenkumar I , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Varadarajan Narayanan , Nitheesh Sekar , Wesley Cheng , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787661450; l=4215; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=KPA9nos1wOXZZh3JS71ONF0Nr0uo+3X8zKZyQLdCnWs=; b=7QikhM252gw6zGC4x2fdMyYaRgbnTtJNJTiJWD+EWysIZptZkghI1foJHk+nIJxkd3sPjIo7K FY5btJCbNN6CfIDnmPBkPn5h333+ZfFOWu4e/8tu7URbp5fGfvjuT61 X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Refactor the IPQ5018/IPQ5332 UNIPHY PCIe init data by introducing a helper macro for register/value entries and converting open-coded struct initializers to the compact form. Also remove an unused include, drop unused macro register definitions, and rename the IPQ5332-specific PHY CFG register macros to make their combo PCIe/USB3 scope explicit. No functional change intended. Signed-off-by: George Moussalem Reviewed-by: Konrad Dybcio Tested-by: Stanislaw Pal --- .../phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c | 94 ++++++++----------= ---- 1 file changed, 33 insertions(+), 61 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c b/driver= s/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c index aeb8f7ddbd7a..44ab8f440b8a 100644 --- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c +++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -24,24 +23,21 @@ #define PIPE_CLK_DELAY_MAX_US 5100 #define CLK_EN_DELAY_MIN_US 30 #define CLK_EN_DELAY_MAX_US 50 -#define CDR_CTRL_REG_1 0x80 -#define CDR_CTRL_REG_2 0x84 -#define CDR_CTRL_REG_3 0x88 -#define CDR_CTRL_REG_4 0x8c -#define CDR_CTRL_REG_5 0x90 -#define CDR_CTRL_REG_6 0x94 -#define CDR_CTRL_REG_7 0x98 -#define SSCG_CTRL_REG_1 0x9c -#define SSCG_CTRL_REG_2 0xa0 -#define SSCG_CTRL_REG_3 0xa4 -#define SSCG_CTRL_REG_4 0xa8 -#define SSCG_CTRL_REG_5 0xac -#define SSCG_CTRL_REG_6 0xb0 -#define PCS_INTERNAL_CONTROL_2 0x2d8 - -#define PHY_CFG_PLLCFG 0x220 -#define PHY_CFG_EIOS_DTCT_REG 0x3e4 -#define PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME 0x3e8 + +#define CDR_CTRL_REG_1 0x80 +#define CDR_CTRL_REG_2 0x84 +#define CDR_CTRL_REG_4 0x8c +#define CDR_CTRL_REG_5 0x90 +#define SSCG_CTRL_REG_1 0x9c +#define SSCG_CTRL_REG_2 0xa0 +#define SSCG_CTRL_REG_3 0xa4 +#define SSCG_CTRL_REG_4 0xa8 +#define SSCG_CTRL_REG_5 0xac + +#define PCIE_USB_COMBO_PHY_CFG_PLLCFG 0x220 +#define PCIE_USB_COMBO_PHY_CFG_PCS_INTERNAL_CONTROL_2 0x2d8 +#define PCIE_USB_COMBO_PHY_CFG_EIOS_DTCT_REG 0x3e4 +#define PCIE_USB_COMBO_PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME 0x3e8 =20 enum qcom_uniphy_type { PHY_TYPE_PCIE =3D 1, @@ -73,53 +69,29 @@ struct qcom_uniphy { int lanes; }; =20 -#define phy_to_dw_phy(x) container_of((x), struct qcom_uniphy, phy) +#define PHY_INIT_CFG(o, v) \ + { \ + .offset =3D o, \ + .val =3D v, \ + } =20 static const struct qcom_uniphy_regs ipq5018_pcie_regs[] =3D { - { - .offset =3D SSCG_CTRL_REG_4, - .val =3D 0x1cb9, - }, { - .offset =3D SSCG_CTRL_REG_5, - .val =3D 0x023a, - }, { - .offset =3D SSCG_CTRL_REG_3, - .val =3D 0xd360, - }, { - .offset =3D SSCG_CTRL_REG_1, - .val =3D 0x1, - }, { - .offset =3D SSCG_CTRL_REG_2, - .val =3D 0xeb, - }, { - .offset =3D CDR_CTRL_REG_4, - .val =3D 0x3f9, - }, { - .offset =3D CDR_CTRL_REG_5, - .val =3D 0x1c9, - }, { - .offset =3D CDR_CTRL_REG_2, - .val =3D 0x419, - }, { - .offset =3D CDR_CTRL_REG_1, - .val =3D 0x200, - }, { - .offset =3D PCS_INTERNAL_CONTROL_2, - .val =3D 0xf101, - }, + PHY_INIT_CFG(SSCG_CTRL_REG_4, 0x1cb9), + PHY_INIT_CFG(SSCG_CTRL_REG_5, 0x023a), + PHY_INIT_CFG(SSCG_CTRL_REG_3, 0xd360), + PHY_INIT_CFG(SSCG_CTRL_REG_1, 0x1), + PHY_INIT_CFG(SSCG_CTRL_REG_2, 0xeb), + PHY_INIT_CFG(CDR_CTRL_REG_4, 0x3f9), + PHY_INIT_CFG(CDR_CTRL_REG_5, 0x1c9), + PHY_INIT_CFG(CDR_CTRL_REG_2, 0x419), + PHY_INIT_CFG(CDR_CTRL_REG_1, 0x200), + PHY_INIT_CFG(PCIE_USB_COMBO_PHY_CFG_PCS_INTERNAL_CONTROL_2, 0xf101), }; =20 static const struct qcom_uniphy_regs ipq5332_pcie_regs[] =3D { - { - .offset =3D PHY_CFG_PLLCFG, - .val =3D 0x30, - }, { - .offset =3D PHY_CFG_EIOS_DTCT_REG, - .val =3D 0x53ef, - }, { - .offset =3D PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME, - .val =3D 0xcf, - }, + PHY_INIT_CFG(PCIE_USB_COMBO_PHY_CFG_PLLCFG, 0x30), + PHY_INIT_CFG(PCIE_USB_COMBO_PHY_CFG_EIOS_DTCT_REG, 0x53ef), + PHY_INIT_CFG(PCIE_USB_COMBO_PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME, 0xcf), }; =20 static const struct qcom_uniphy_data ipq5018_data =3D { --=20 2.53.0 From nobody Mon Sep 28 06:35:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27465448380; Tue, 25 Aug 2026 12:37:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260825-ipq5018-usb3-v3-5-39be0955a6aa@outlook.com> References: <20260825-ipq5018-usb3-v3-0-39be0955a6aa@outlook.com> In-Reply-To: <20260825-ipq5018-usb3-v3-0-39be0955a6aa@outlook.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Praveenkumar I , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Varadarajan Narayanan , Nitheesh Sekar , Wesley Cheng , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787661450; l=3269; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=anmYpL4XdHm2CePMeEnW1kc8uD6kV9bQvtwXZhei8sQ=; b=J/54879naA7qYSLWrsAljr2kFOCd8PXFxuQZhTFXpXZSDCASzOr2ohHCctLia9y5e4PFreiOv W9jI3yXpHu2CX48WxUKgACuYEyuA5RRzsUgucw2v2HvG1k11WUEmL+L X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Switch to using bulk reset_control functions to prepare the driver for managing multiple resets, acquiring reset controls by name, and uniformly storing resets in the private data structure to enable support for future combo PHY functionality requiring multiple resets. Signed-off-by: George Moussalem Reviewed-by: Manivannan Sadhasivam Tested-by: Stanislaw Pal --- .../phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c | 31 ++++++++++++++++--= ---- 1 file changed, 23 insertions(+), 8 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c b/driver= s/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c index 44ab8f440b8a..671bb805057f 100644 --- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c +++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c @@ -64,7 +64,8 @@ struct qcom_uniphy { const struct qcom_uniphy_data *data; struct clk_bulk_data *clks; int num_clks; - struct reset_control *resets; + struct reset_control_bulk_data *resets; + int num_resets; void __iomem *base; int lanes; }; @@ -133,7 +134,7 @@ static int qcom_uniphy_pcie_usb3_power_off(struct phy *= x) =20 clk_bulk_disable_unprepare(phy->num_clks, phy->clks); =20 - return reset_control_assert(phy->resets); + return reset_control_bulk_assert(phy->num_resets, phy->resets); } =20 static int qcom_uniphy_pcie_usb3_power_on(struct phy *x) @@ -141,7 +142,7 @@ static int qcom_uniphy_pcie_usb3_power_on(struct phy *x) struct qcom_uniphy *phy =3D phy_get_drvdata(x); int ret; =20 - ret =3D reset_control_assert(phy->resets); + ret =3D reset_control_bulk_assert(phy->num_resets, phy->resets); if (ret) { dev_err(phy->dev, "reset assert failed (%d)\n", ret); return ret; @@ -149,7 +150,7 @@ static int qcom_uniphy_pcie_usb3_power_on(struct phy *x) =20 usleep_range(RST_ASSERT_DELAY_MIN_US, RST_ASSERT_DELAY_MAX_US); =20 - ret =3D reset_control_deassert(phy->resets); + ret =3D reset_control_bulk_deassert(phy->num_resets, phy->resets); if (ret) { dev_err(phy->dev, "reset deassert failed (%d)\n", ret); return ret; @@ -173,19 +174,33 @@ static int qcom_uniphy_pcie_usb3_power_on(struct phy = *x) static inline int qcom_uniphy_pcie_usb3_get_resources(struct platform_devi= ce *pdev, struct qcom_uniphy *phy) { + struct device *dev =3D phy->dev; struct resource *res; + int i, count; =20 phy->base =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(phy->base)) return PTR_ERR(phy->base); =20 - phy->num_clks =3D devm_clk_bulk_get_all(phy->dev, &phy->clks); + phy->num_clks =3D devm_clk_bulk_get_all(dev, &phy->clks); if (phy->num_clks < 0) return phy->num_clks; =20 - phy->resets =3D devm_reset_control_array_get_exclusive(phy->dev); - if (IS_ERR(phy->resets)) - return PTR_ERR(phy->resets); + count =3D of_count_phandle_with_args(dev->of_node, "resets", "#reset-cell= s"); + if (count < 0) + return count; + + phy->resets =3D devm_kcalloc(dev, count, sizeof(*phy->resets), GFP_KERNEL= ); + if (!phy->resets) + return -ENOMEM; + + for (i =3D 0; i < count; i++) { + phy->resets[i].rstc =3D devm_reset_control_get_exclusive_by_index(dev, i= ); + if (IS_ERR(phy->resets[i].rstc)) + return PTR_ERR(phy->resets[i].rstc); + } + + phy->num_resets =3D count; =20 return 0; } --=20 2.53.0 From nobody Mon Sep 28 06:35:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26EA5447818; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260825-ipq5018-usb3-v3-6-39be0955a6aa@outlook.com> References: <20260825-ipq5018-usb3-v3-0-39be0955a6aa@outlook.com> In-Reply-To: <20260825-ipq5018-usb3-v3-0-39be0955a6aa@outlook.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Praveenkumar I , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Varadarajan Narayanan , Nitheesh Sekar , Wesley Cheng , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787661450; l=2016; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=7wBK4ADEhWBDqDww6gxmOEnN2/BlTdDKW1nGKMr0m+o=; b=C/MYQL7TG7DA7JcFLXibus27QkTlcnmxhzu7Vca3khVoAlzNRyJCTtlSZizM71/jTyiIZbUpo j5fKhLDbh4cDHNCctklnY94gRgK3ukpF3JbMkogPcOlKt+EED1pT4yo X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem When the PHY fails the enable clocks, it leaves the PHY out of reset. Fix this by asserting the reset before returning the error. In addition, language correct the error messages. Signed-off-by: George Moussalem Tested-by: Stanislaw Pal --- drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c b/driver= s/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c index 671bb805057f..d25ae9d8b9e7 100644 --- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c +++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c @@ -144,7 +144,7 @@ static int qcom_uniphy_pcie_usb3_power_on(struct phy *x) =20 ret =3D reset_control_bulk_assert(phy->num_resets, phy->resets); if (ret) { - dev_err(phy->dev, "reset assert failed (%d)\n", ret); + dev_err(phy->dev, "failed to assert reset: %d\n", ret); return ret; } =20 @@ -152,7 +152,7 @@ static int qcom_uniphy_pcie_usb3_power_on(struct phy *x) =20 ret =3D reset_control_bulk_deassert(phy->num_resets, phy->resets); if (ret) { - dev_err(phy->dev, "reset deassert failed (%d)\n", ret); + dev_err(phy->dev, "failed to deassert reset: %d\n", ret); return ret; } =20 @@ -160,8 +160,8 @@ static int qcom_uniphy_pcie_usb3_power_on(struct phy *x) =20 ret =3D clk_bulk_prepare_enable(phy->num_clks, phy->clks); if (ret) { - dev_err(phy->dev, "clk prepare and enable failed %d\n", ret); - return ret; + dev_err(phy->dev, "failed to enable clocks: %d\n", ret); + goto err_assert_resets; } =20 usleep_range(CLK_EN_DELAY_MIN_US, CLK_EN_DELAY_MAX_US); @@ -169,6 +169,11 @@ static int qcom_uniphy_pcie_usb3_power_on(struct phy *= x) qcom_uniphy_pcie_usb3_init(phy); =20 return 0; + +err_assert_resets: + reset_control_bulk_assert(phy->num_resets, phy->resets); + + return ret; } =20 static inline int qcom_uniphy_pcie_usb3_get_resources(struct platform_devi= ce *pdev, --=20 2.53.0 From nobody Mon Sep 28 06:35:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E06A44838A; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TGSHgOJX" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4E6EEC4AF64; Tue, 25 Aug 2026 12:37:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787661453; bh=avzmWwQpX0JSkmRzAWMW0/YG33J6q0FexnlR/eMZTQY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=TGSHgOJXlRia8CsEkiTGLJuif2wqmmFGpq97SzMK6Ki/T/3OY7dJZAah0+pEnHSe9 grcy6/GSMUxG7Fg9fkU5pYgpQNYITV/EwY24p+prLUXaubYLjJgj14KL8E0vGfp92B 6GLncB2eRRt2Yv0oDQWvt/LH7xMeeLRzWKGAQ2Y+7Az1gX7ifWM4cJFfiHA04wnff+ iC8wvET1djwW1+3HotdaFjthjrLzyXeiEj6WOsLDLKluhOK6oZnnIJrESprt/ISWyW WDtkeVv738e62yyLRINy0p6ksTAvP+ZpFqoGB4RVwcRrXdddJEt5GcihGnKGoB1T3B 3nR8l406/vscg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 354D8C61DC2; Tue, 25 Aug 2026 12:37:33 +0000 (UTC) From: George Moussalem via B4 Relay Date: Tue, 25 Aug 2026 16:37:24 +0400 Subject: [PATCH v3 07/12] phy: qualcomm: qcom-uniphy-pcie-usb3-28lp: Add support for USB3 PHY on IPQ5018 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260825-ipq5018-usb3-v3-7-39be0955a6aa@outlook.com> References: <20260825-ipq5018-usb3-v3-0-39be0955a6aa@outlook.com> In-Reply-To: <20260825-ipq5018-usb3-v3-0-39be0955a6aa@outlook.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Praveenkumar I , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Varadarajan Narayanan , Nitheesh Sekar , Wesley Cheng , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787661450; l=10092; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=+boAC526ClvI2owwAskgOQvw3WQqb1ch8EZ15tcbsa0=; b=wb4Zy3IYXRKG7jetKeaIyXYC3CAq5Eyk9bsdmorAhskRYGNvC5CoviJeby7BMS1mZkBU7WUur 1m630mR+2N+B5/q//kdCzSokaJZOFelk1eKA6pVfVgPBglcaI9hpMBE X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Add support for the USB3 PHY on IPQ5018 chipsets. The PHY outputs a 250MHz PIPE clock routed to and gated by the GCC, so register a fixed rate clock. In addition, add the register/value pairs for the PHY initialization sequence. The PHY requires a 5V supply, so acquire the regulator from the devicetree and enable it on power on and disable it on power off. The code to acquire clocks and resets is the same as for PCIe so no changes are needed. Power on/off sequences for PCIE and USB3 are similar except for the delay timings and USB3 requirement for the PHY supply. Lastly, the PCIe and USB3 pads are muxed so select USB3 mode in TCSR which needs to occur before the DWC3 USB3 controller resets. Otherwise, the SS link doesn't train and remains stuck in RX.Detect. Signed-off-by: George Moussalem Tested-by: Stanislaw Pal --- .../phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c | 154 +++++++++++++++++= ---- 1 file changed, 127 insertions(+), 27 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c b/driver= s/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c index d25ae9d8b9e7..84df331fce74 100644 --- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c +++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c @@ -14,15 +14,21 @@ #include #include #include +#include #include #include =20 -#define RST_ASSERT_DELAY_MIN_US 100 -#define RST_ASSERT_DELAY_MAX_US 150 -#define PIPE_CLK_DELAY_MIN_US 5000 -#define PIPE_CLK_DELAY_MAX_US 5100 -#define CLK_EN_DELAY_MIN_US 30 -#define CLK_EN_DELAY_MAX_US 50 +#define PCIE_RST_ASSERT_DELAY_MIN_US 100 +#define PCIE_RST_ASSERT_DELAY_MAX_US 150 +#define PCIE_PIPE_CLK_DELAY_MIN_US 5000 +#define PCIE_PIPE_CLK_DELAY_MAX_US 5100 +#define PCIE_CLK_EN_DELAY_MIN_US 30 +#define PCIE_CLK_EN_DELAY_MAX_US 50 + +#define USB3_RST_ASSERT_DELAY_MIN_US 1 +#define USB3_RST_ASSERT_DELAY_MAX_US 5 +#define USB3_CLK_EN_DELAY_MIN_US 35 +#define USB3_CLK_EN_DELAY_MAX_US 40 =20 #define CDR_CTRL_REG_1 0x80 #define CDR_CTRL_REG_2 0x84 @@ -39,10 +45,13 @@ #define PCIE_USB_COMBO_PHY_CFG_EIOS_DTCT_REG 0x3e4 #define PCIE_USB_COMBO_PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME 0x3e8 =20 +#define TCSR_USB_MUX_SEL BIT(0) + +#define PHY_IS_USB3(phy) ((phy)->data->phy_type =3D=3D PHY_TYPE_USB3) + enum qcom_uniphy_type { PHY_TYPE_PCIE =3D 1, - PHY_TYPE_PCIE_GEN2, - PHY_TYPE_PCIE_GEN3, + PHY_TYPE_USB3, }; =20 struct qcom_uniphy_regs { @@ -68,6 +77,9 @@ struct qcom_uniphy { int num_resets; void __iomem *base; int lanes; + struct regulator *vreg; + struct regmap *tcsr; + unsigned int mux_offset; }; =20 #define PHY_INIT_CFG(o, v) \ @@ -89,23 +101,39 @@ static const struct qcom_uniphy_regs ipq5018_pcie_regs= [] =3D { PHY_INIT_CFG(PCIE_USB_COMBO_PHY_CFG_PCS_INTERNAL_CONTROL_2, 0xf101), }; =20 +static const struct qcom_uniphy_regs ipq5018_usb_regs[] =3D { + PHY_INIT_CFG(SSCG_CTRL_REG_4, 0x1cb9), + PHY_INIT_CFG(SSCG_CTRL_REG_5, 0x023a), + PHY_INIT_CFG(SSCG_CTRL_REG_3, 0xd360), + PHY_INIT_CFG(SSCG_CTRL_REG_1, 0x1), + PHY_INIT_CFG(SSCG_CTRL_REG_2, 0xeb), +}; + static const struct qcom_uniphy_regs ipq5332_pcie_regs[] =3D { PHY_INIT_CFG(PCIE_USB_COMBO_PHY_CFG_PLLCFG, 0x30), PHY_INIT_CFG(PCIE_USB_COMBO_PHY_CFG_EIOS_DTCT_REG, 0x53ef), PHY_INIT_CFG(PCIE_USB_COMBO_PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME, 0xcf), }; =20 -static const struct qcom_uniphy_data ipq5018_data =3D { +static const struct qcom_uniphy_data ipq5018_pcie_data =3D { .lane_offset =3D 0x800, - .phy_type =3D PHY_TYPE_PCIE_GEN2, + .phy_type =3D PHY_TYPE_PCIE, .init_seq =3D ipq5018_pcie_regs, .init_seq_num =3D ARRAY_SIZE(ipq5018_pcie_regs), .pipe_clk_rate =3D 125 * MEGA, }; =20 -static const struct qcom_uniphy_data ipq5332_data =3D { +static const struct qcom_uniphy_data ipq5018_usb_data =3D { .lane_offset =3D 0x800, - .phy_type =3D PHY_TYPE_PCIE_GEN3, + .phy_type =3D PHY_TYPE_USB3, + .init_seq =3D ipq5018_usb_regs, + .init_seq_num =3D ARRAY_SIZE(ipq5018_usb_regs), + .pipe_clk_rate =3D 250 * MEGA, +}; + +static const struct qcom_uniphy_data ipq5332_pcie_data =3D { + .lane_offset =3D 0x800, + .phy_type =3D PHY_TYPE_PCIE, .init_seq =3D ipq5332_pcie_regs, .init_seq_num =3D ARRAY_SIZE(ipq5332_pcie_regs), .pipe_clk_rate =3D 250 * MEGA, @@ -134,29 +162,49 @@ static int qcom_uniphy_pcie_usb3_power_off(struct phy= *x) =20 clk_bulk_disable_unprepare(phy->num_clks, phy->clks); =20 - return reset_control_bulk_assert(phy->num_resets, phy->resets); + reset_control_bulk_assert(phy->num_resets, phy->resets); + + if (PHY_IS_USB3(phy)) + regulator_disable(phy->vreg); + + return 0; } =20 static int qcom_uniphy_pcie_usb3_power_on(struct phy *x) { struct qcom_uniphy *phy =3D phy_get_drvdata(x); + bool is_usb3 =3D PHY_IS_USB3(phy); int ret; =20 + if (is_usb3) { + ret =3D regulator_enable(phy->vreg); + if (ret) { + dev_err(phy->dev, "failed to enable regulator: %d\n", ret); + return ret; + } + } + ret =3D reset_control_bulk_assert(phy->num_resets, phy->resets); if (ret) { dev_err(phy->dev, "failed to assert reset: %d\n", ret); - return ret; + goto err_disable_regulator; } =20 - usleep_range(RST_ASSERT_DELAY_MIN_US, RST_ASSERT_DELAY_MAX_US); + if (is_usb3) + usleep_range(USB3_RST_ASSERT_DELAY_MIN_US, + USB3_RST_ASSERT_DELAY_MAX_US); + else + usleep_range(PCIE_RST_ASSERT_DELAY_MIN_US, + PCIE_RST_ASSERT_DELAY_MAX_US); =20 ret =3D reset_control_bulk_deassert(phy->num_resets, phy->resets); if (ret) { dev_err(phy->dev, "failed to deassert reset: %d\n", ret); - return ret; + goto err_disable_regulator; } =20 - usleep_range(PIPE_CLK_DELAY_MIN_US, PIPE_CLK_DELAY_MAX_US); + if (!is_usb3) + usleep_range(PCIE_PIPE_CLK_DELAY_MIN_US, PCIE_PIPE_CLK_DELAY_MAX_US); =20 ret =3D clk_bulk_prepare_enable(phy->num_clks, phy->clks); if (ret) { @@ -164,7 +212,10 @@ static int qcom_uniphy_pcie_usb3_power_on(struct phy *= x) goto err_assert_resets; } =20 - usleep_range(CLK_EN_DELAY_MIN_US, CLK_EN_DELAY_MAX_US); + if (is_usb3) + usleep_range(USB3_CLK_EN_DELAY_MIN_US, USB3_CLK_EN_DELAY_MAX_US); + else + usleep_range(PCIE_CLK_EN_DELAY_MIN_US, PCIE_CLK_EN_DELAY_MAX_US); =20 qcom_uniphy_pcie_usb3_init(phy); =20 @@ -172,6 +223,9 @@ static int qcom_uniphy_pcie_usb3_power_on(struct phy *x) =20 err_assert_resets: reset_control_bulk_assert(phy->num_resets, phy->resets); +err_disable_regulator: + if (is_usb3) + regulator_disable(phy->vreg); =20 return ret; } @@ -181,7 +235,7 @@ static inline int qcom_uniphy_pcie_usb3_get_resources(s= truct platform_device *pd { struct device *dev =3D phy->dev; struct resource *res; - int i, count; + int i, count, ret; =20 phy->base =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(phy->base)) @@ -207,6 +261,33 @@ static inline int qcom_uniphy_pcie_usb3_get_resources(= struct platform_device *pd =20 phy->num_resets =3D count; =20 + if (PHY_IS_USB3(phy)) { + phy->vreg =3D devm_regulator_get(dev, "vdd"); + if (IS_ERR(phy->vreg)) { + dev_err(dev, "failed to get regulator: %ld\n", + PTR_ERR(phy->vreg)); + return PTR_ERR(phy->vreg); + } + + phy->tcsr =3D syscon_regmap_lookup_by_phandle_args(dev->of_node, + "qcom,phy-usb-mux-sel", + 1, &phy->mux_offset); + if (IS_ERR(phy->tcsr)) { + ret =3D PTR_ERR(phy->tcsr); + dev_err(dev, "failed to get regmap: %d\n", ret); + return ret; + } + + phy->lanes =3D 1; + } else { + ret =3D of_property_read_u32(dev_of_node(dev), "num-lanes", + &phy->lanes); + if (ret) { + dev_err(dev, "Couldn't read num-lanes: %d\n", ret); + return ret; + } + } + return 0; } =20 @@ -234,7 +315,8 @@ static inline int phy_pipe_clk_register(struct qcom_uni= phy *phy, int id) struct clk_hw *hw; char name[64]; =20 - snprintf(name, sizeof(name), "phy%d_pipe_clk_src", id); + snprintf(name, sizeof(name), "%sphy%d_pipe_clk_src", + (PHY_IS_USB3(phy)) ? "usb" : "", id); hw =3D devm_clk_hw_register_fixed_rate(phy->dev, name, NULL, 0, data->pipe_clk_rate); if (IS_ERR(hw)) @@ -244,15 +326,25 @@ static inline int phy_pipe_clk_register(struct qcom_u= niphy *phy, int id) return devm_of_clk_add_hw_provider(phy->dev, of_clk_hw_simple_get, hw); } =20 +static int qcom_uniphy_usb_mux_select(struct qcom_uniphy *phy, bool enable) +{ + return regmap_update_bits(phy->tcsr, phy->mux_offset, + TCSR_USB_MUX_SEL, + enable ? TCSR_USB_MUX_SEL : 0); +} + static const struct of_device_id qcom_uniphy_pcie_usb3_id_table[] =3D { { .compatible =3D "qcom,ipq5018-uniphy-pcie-phy", - .data =3D &ipq5018_data, + .data =3D &ipq5018_pcie_data, + }, { + .compatible =3D "qcom,ipq5018-uniphy-usb3-phy", + .data =3D &ipq5018_usb_data, }, { .compatible =3D "qcom,ipq5332-uniphy-pcie-phy", - .data =3D &ipq5332_data, + .data =3D &ipq5332_pcie_data, }, - { }, + { } }; MODULE_DEVICE_TABLE(of, qcom_uniphy_pcie_usb3_id_table); =20 @@ -281,10 +373,6 @@ static int qcom_uniphy_pcie_usb3_probe(struct platform= _device *pdev) if (!phy->data) return -EINVAL; =20 - ret =3D of_property_read_u32(dev_of_node(dev), "num-lanes", &phy->lanes); - if (ret) - return dev_err_probe(dev, ret, "Couldn't read num-lanes\n"); - ret =3D qcom_uniphy_pcie_usb3_get_resources(pdev, phy); if (ret < 0) return dev_err_probe(&pdev->dev, ret, @@ -305,6 +393,18 @@ static int qcom_uniphy_pcie_usb3_probe(struct platform= _device *pdev) if (IS_ERR(phy_provider)) return PTR_ERR(phy_provider); =20 + /* + * Select USB mux before the controller comes out of reset. Selecting it + * later in .power_on leaves the SuperSpeed pads muxed away while the + * controller resets, and the SS link training remains in Rx.Detect + */ + if (PHY_IS_USB3(phy)) { + ret =3D qcom_uniphy_usb_mux_select(phy, true); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "failed to select usb mux\n"); + } + return 0; } =20 --=20 2.53.0 From nobody Mon Sep 28 06:35:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0456E447800; Tue, 25 Aug 2026 12:37:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787661456; cv=none; b=gFtsQEPaFNwA3EaXIwQg/yDeE7VpRbD0fNn0qMxt9zsnjNWs6RkNZ0VQNJrDUN6+ekElb3fqg2E7JCnpw7SZA335hpu8KThmfBMwP5MZNm21554rNbXL73oe+n/NqT1FQMMwowI/knKIl6H8nOF9wx3GQHW7K7FdWdbaAP6qFU8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787661456; c=relaxed/simple; bh=xEZbjkRSjge3V1gBlRIEkTNYuMWY3j9/vqhEVfhgLQ0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MZEhVB1vit5rH3gL6cXmrPbALsd94liTYIaV4bNntM+gKYb2a12oPlZmmAT+YtWJhsj8VQjo2rV1ZUorb0OZk26rnDzUfRWayY+Bxsc80jyYLQRWUJXNl+J7p3jPM3yQxczUhKFJjw+RYXjaLLdhZqqsMiOrccGqon0CXgGokrI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HiXfKtuP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HiXfKtuP" Received: by smtp.kernel.org (Postfix) with ESMTPS id 58B6EC4DDE5; Tue, 25 Aug 2026 12:37:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787661453; bh=xEZbjkRSjge3V1gBlRIEkTNYuMWY3j9/vqhEVfhgLQ0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=HiXfKtuPdCF1l6d5U/dzVLaapcmzHGu+PvPjLvqwrlOO5iQ/AzKMXLrF1Rlwgdb26 551kf0fS3+RwgemgxP6XG3Y2oKukoJGPSupWnoEfmRY1d54/LK+9WfDKU40W4c7wJa q+CKYY4mu7Trs3TphoNJGH9uVRReYVGmIhA7vWfsezHEz1xVeOITEB7ftQhMbKrVHm O1IPLO3GlRPoU7ur+pkLWlgtI1p5jyPLkH/6fmwrUwj1mXZL5AYulVQ0Xpq2JmWkf8 zufJ1ZpYA4SXys9qEtoH/M3W48CjFsauC+sIY78bOWERHzJ6l9dZMGXDBwQRGWPdfa zWVBkj4755cfg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 442D7C61DBD; Tue, 25 Aug 2026 12:37:33 +0000 (UTC) From: George Moussalem via B4 Relay Date: Tue, 25 Aug 2026 16:37:25 +0400 Subject: [PATCH v3 08/12] arm64: dts: qcom: ipq5018: Add USB Super-Speed PHY node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260825-ipq5018-usb3-v3-8-39be0955a6aa@outlook.com> References: <20260825-ipq5018-usb3-v3-0-39be0955a6aa@outlook.com> In-Reply-To: <20260825-ipq5018-usb3-v3-0-39be0955a6aa@outlook.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Praveenkumar I , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Varadarajan Narayanan , Nitheesh Sekar , Wesley Cheng , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787661450; l=1320; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=3gnMuvdkhkSVCiECSjDDLV0IaEe/Z6xvImu3EIsvXdQ=; b=Cknj3brONBxs/fkWzuFYk+noU2/5hU46dPVVx7B3IKjGcQqW/s4Vkd1ihFhRVK/WAOdVNL46K zO0iGzB9aGdDsirSHzKDD7mgIJjv3NzyIYU3YVMs5Nq49wCwyCE7gJI X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Add the USB3 PHY node and populate the USB DT clock on the GCC node for the GCC to gate the PIPE clock supplied by the USB3 PHY. Signed-off-by: George Moussalem Tested-by: Stanislaw Pal --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qc= om/ipq5018.dtsi index 71834606535e..7638299671d8 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -179,6 +179,23 @@ usbphy0: phy@5b000 { status =3D "disabled"; }; =20 + usbphy1: phy@5d000 { + compatible =3D "qcom,ipq5018-uniphy-usb3-phy"; + reg =3D <0x0005d000 0x800>; + + clocks =3D <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB0_PIPE_CLK>; + + resets =3D <&gcc GCC_USB0_PHY_BCR>; + + #clock-cells =3D <0>; + #phy-cells =3D <0>; + + qcom,phy-usb-mux-sel =3D <&tcsr 0x10540>; + + status =3D "disabled"; + }; + pcie1_phy: phy@7e000 { compatible =3D "qcom,ipq5018-uniphy-pcie-phy"; reg =3D <0x0007e000 0x800>; @@ -436,7 +453,7 @@ gcc: clock-controller@1800000 { <&sleep_clk>, <&pcie0_phy>, <&pcie1_phy>, - <0>, + <&usbphy1>, <&gephy_rx_clk>, <&gephy_tx_clk>, <0>, --=20 2.53.0 From nobody Mon Sep 28 06:35:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 25DFA447817; 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These clocks are required only for USB Super-Speed support. Reviewed-by: Krzysztof Kozlowski Signed-off-by: George Moussalem Acked-by: Manivannan Sadhasivam Tested-by: Stanislaw Pal --- .../devicetree/bindings/usb/qcom,snps-dwc3.yaml | 21 +++++++++++++++++= +++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml b/Do= cumentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml index aa263dfd42a1..97dd0cefd732 100644 --- a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml @@ -194,6 +194,26 @@ allOf: - const: sleep - const: mock_utmi =20 + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5018-dwc3 + then: + properties: + clocks: + minItems: 6 + maxItems: 6 + clock-names: + items: + - const: core + - const: iface + - const: sleep + - const: mock_utmi + - const: aux + - const: lfps + - if: properties: compatible: @@ -295,7 +315,6 @@ allOf: compatible: contains: enum: - - qcom,ipq5018-dwc3 - qcom,msm8994-dwc3 - qcom,qcs404-dwc3 then: --=20 2.53.0 From nobody Mon Sep 28 06:35:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24F28447816; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260825-ipq5018-usb3-v3-10-39be0955a6aa@outlook.com> References: <20260825-ipq5018-usb3-v3-0-39be0955a6aa@outlook.com> In-Reply-To: <20260825-ipq5018-usb3-v3-0-39be0955a6aa@outlook.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Praveenkumar I , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Varadarajan Narayanan , Nitheesh Sekar , Wesley Cheng , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, Dmitry Baryshkov , George Moussalem X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787661450; l=1328; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=STG2XcQgC6WNHuUCJZXxf9qTnMcaFKA0w+Hgc6UGMow=; b=LktWaB86JJzH2hvfz3p4tPxjnwwKE/gS5Cj4+uZODCnYfKGLIZDNyy7vsAJWRAcJb9ib1gijY 0H25XTVm7W2DMhEuniH01uTRDx8D4bHk2OD7/iEd9Ry2AI6pTLsIhPF X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Add aux and lfps clocks to USB controller node for Super-Speed support. These clocks are required for USB3 mode only and are not needed for USB2 mode. In addition, set UTMI clock frequency to ensure it's parented correctly and override the clock rate potentially set by the bootloader. Reviewed-by: Dmitry Baryshkov Signed-off-by: George Moussalem Reviewed-by: Konrad Dybcio Tested-by: Stanislaw Pal --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qc= om/ipq5018.dtsi index 7638299671d8..7f730c2ab763 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -604,11 +604,15 @@ usb: usb@8a00000 { clocks =3D <&gcc GCC_USB0_MASTER_CLK>, <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, <&gcc GCC_USB0_SLEEP_CLK>, - <&gcc GCC_USB0_MOCK_UTMI_CLK>; + <&gcc GCC_USB0_MOCK_UTMI_CLK>, + <&gcc GCC_USB0_AUX_CLK>, + <&gcc GCC_USB0_LFPS_CLK>; clock-names =3D "core", "iface", "sleep", - "mock_utmi"; + "mock_utmi", + "aux", + "lfps"; assigned-clocks =3D <&gcc GCC_USB0_MOCK_UTMI_CLK>; assigned-clock-rates =3D <60000000>; =20 --=20 2.53.0 From nobody Mon Sep 28 06:35:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24E4F447813; Tue, 25 Aug 2026 12:37:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787661456; cv=none; b=fCkiIgwNgyW4AmySoPw22D3Pkuos7wd6RoCZF42S9BFP6Tegup+3bpShFn2DBKrUuKEt+w0mgDbwghr7tP64MMxnd6lbGTKKJ1zOH9l1CSjKh3MV8SK0RRVf/6hOjX+XPTZk2zCXfu3LjJIDJVouMVYsVS7dnf0Ge2nXD8q/p34= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787661456; c=relaxed/simple; bh=7HqpnMgNEy9bMnvjfM6izpGfqJmx0bsSpY59UO9CNhE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NdpB0+G1+ZyAIJUh+F0+jHqj3+ZoO3cFiwJ5CdqYSQGpAaXcpzOObCCt84XhN/K1n9NACAO4tSaF0C+V9V3n9or6r5JEaC3gfCR208L6vqoqz1jYlIbYWK2XM9cCorJhPdNDyipJ64sKckoQD339XNDsk5R+52MxOPbRpwuVR8Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=IXGwJyLk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IXGwJyLk" Received: by smtp.kernel.org (Postfix) with ESMTPS id 898BFC4AF17; Tue, 25 Aug 2026 12:37:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787661453; bh=7HqpnMgNEy9bMnvjfM6izpGfqJmx0bsSpY59UO9CNhE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=IXGwJyLk/FZSzk0r5fnyUQvCX+FdjQ5TTlTHVDKRWaXROBYQCxUoHgICY2VTQbqTj Us9RVE1S6MsmhIweRD6IHWNDGudw3Q15PtBoWUy3i0RsWA3KRZY90DNu4k39ANCSTE 1pkfGJK3im+fI+Gjb138YXIJHtgp2p8mJ1zM/bnZan6DVx2SR5/B3iqGsPUfFS6yTD vAATFJ+Xyn6bDxKDq0TfouVXH3nYCrZhG03HUkWtejMuYgpN7DTnrIoST2zvKYykPR crGV7MlHMhA/ZhVjruSFez16IfwyAJFD0f4EdERe3zFR1WGAWqxP5BA8oQbZM++B0h tzOydQmnTpzoQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73977C61DC2; Tue, 25 Aug 2026 12:37:33 +0000 (UTC) From: George Moussalem via B4 Relay Date: Tue, 25 Aug 2026 16:37:28 +0400 Subject: [PATCH v3 11/12] arm64: dts: qcom: ipq5018: Add Super-Speed UNIPHY to USB node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260825-ipq5018-usb3-v3-11-39be0955a6aa@outlook.com> References: <20260825-ipq5018-usb3-v3-0-39be0955a6aa@outlook.com> In-Reply-To: <20260825-ipq5018-usb3-v3-0-39be0955a6aa@outlook.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Praveenkumar I , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Varadarajan Narayanan , Nitheesh Sekar , Wesley Cheng , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787661450; l=880; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=nVztOgvUA+UCMXgiAA8vKe6nVwfiycloNnuAVugC3Ac=; b=A85eEy0Q45TkeWiv8ekcGDPCXTButmyt7zaT2ZC2ASmwKckXMF16vG15NA5Lzn5L0Jbw/TfDs J0jBuxfN5JeDlJV9e5Bn2LeEzR8Mvrg4QbSrXL50YMl/r4119B7sv3K X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Add the USB3 UNIPHY to the USB controller node for USB3 support. In addition, switch to the pipe clock supplied by the USB3 UNIPHY instead of the UTMI clock. Signed-off-by: George Moussalem Reviewed-by: Konrad Dybcio Tested-by: Stanislaw Pal --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qc= om/ipq5018.dtsi index 7f730c2ab763..1f55b0ba5c9d 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -627,10 +627,9 @@ usb: usb@8a00000 { =20 resets =3D <&gcc GCC_USB0_BCR>; =20 - phys =3D <&usbphy0>; - phy-names =3D "usb2-phy"; + phys =3D <&usbphy0>, <&usbphy1>; + phy-names =3D "usb2-phy", "usb3-phy"; =20 - qcom,select-utmi-as-pipe-clk; qcom,select-utmi-as-ref-clk; =20 tx-fifo-resize; --=20 2.53.0 From nobody Mon Sep 28 06:35:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23A9E447811; Tue, 25 Aug 2026 12:37:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787661456; cv=none; b=s3pZ//IePzqYnX2Ee+uvNFcrwffkUDV7h0/uOclmk2htpNtBJu+HXTkFELAZcfupXlm2g01hPdtyroqG5MV33QqXuWE+r+mKXi6YyaxEHg1omZo2P84pS92Dbz3+xuTMy+ZvaD/S6gCiwEYhFc+QpvWzx4YM+M3CBDKk6RDmYdk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787661456; c=relaxed/simple; bh=7Zgspg2cpl6a219QZ8lKlBpC1rJx9A4XKCi4EwWakz4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Fvwvzcx34mAXzOxuDYTjXc7OqyxdCJ1LpGoMcUL7f4TBG5ZyIpTByhBRdiEumxH7w/y+2i/eEy8J2kfaRT8/6YBNIQc4eS/hFce11yBrFS2ESZGRlmoM+v3+TXCsBNYfGjoUStAmcnkHj1ZRByJsWhEQMOaYt/K1AzOQPSZK6mQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bZs2GgiJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bZs2GgiJ" Received: by smtp.kernel.org (Postfix) with ESMTPS id 97A99C4AF18; Tue, 25 Aug 2026 12:37:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787661453; bh=7Zgspg2cpl6a219QZ8lKlBpC1rJx9A4XKCi4EwWakz4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=bZs2GgiJnxbXABZ7Dm/P+b9Iw3Fh549cvtzTQur8tWjK4WHzTrCyJHPNNIALjCDHy KwWnhZAtJnNKo6liFOJ6d8jaSgw4odZ1ATv5ie52AUlX+qchqeHUNvw0bZtOIdfDq4 ixJjLdDavzcTDABdkl6k8paUNIkIce/XhdlgWch5yoVmF7XiavqQlxHFladFv0VvkE HsjINhUTOgUGfGsLmsVi/uX5rhK9cTcxfA66EbkihhpqHLO131mth2RhMpK6LURtm1 GK0bx4LcNYc79Es2nQO80JAtEAm25u7Q0S1LywEPi3+LFy3XiyUGEJ0Lz20/C2vXRf zqCbjxCep+qOA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82E91C61DC4; Tue, 25 Aug 2026 12:37:33 +0000 (UTC) From: George Moussalem via B4 Relay Date: Tue, 25 Aug 2026 16:37:29 +0400 Subject: [PATCH v3 12/12] arm64: dts: qcom: ipq5018: Enable USB Super-Speed PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260825-ipq5018-usb3-v3-12-39be0955a6aa@outlook.com> References: <20260825-ipq5018-usb3-v3-0-39be0955a6aa@outlook.com> In-Reply-To: <20260825-ipq5018-usb3-v3-0-39be0955a6aa@outlook.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Praveenkumar I , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Varadarajan Narayanan , Nitheesh Sekar , Wesley Cheng , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787661450; l=1078; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=mqT4fUHiS6tNRhSdjnTI3aemIVcVL9vUJPPDNDpgcvM=; b=Zbh5XdZj5kfib84EvhnO+1xUv69j2kvgZlvOlgYPrI6hfVGPf812sBi6fbEFwZkzDzuN8g92X zu3GBxeoPA+BP2pHmBTWaCK2dYjZLRiSjy+BermATV6GSCSAqPfpC8b X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Add the 5V supply regulator and enable USB Super-Speed PHY support. Signed-off-by: George Moussalem Reviewed-by: Konrad Dybcio Tested-by: Stanislaw Pal --- arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/bo= ot/dts/qcom/ipq5018-rdp432-c2.dts index 8efb2b21ed9e..ca29f271e673 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts @@ -22,6 +22,14 @@ aliases { chosen { stdout-path =3D "serial0:115200n8"; }; + + regulator_fixed_5p0: regulator-s0500 { + compatible =3D "regulator-fixed"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-name =3D "fixed_5p0"; + gpios =3D <&tlmm 24 GPIO_ACTIVE_LOW>; + }; }; =20 &blsp1_uart1 { @@ -119,6 +127,12 @@ &usbphy0 { status =3D "okay"; }; =20 +&usbphy1 { + vdd-supply =3D <®ulator_fixed_5p0>; + + status =3D "okay"; +}; + &xo_board_clk { clock-div =3D <4>; clock-mult =3D <1>; --=20 2.53.0