From nobody Mon Sep 28 06:36:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A57E43FA5FC; Tue, 25 Aug 2026 11:08:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787656134; cv=none; b=X/dGpB+q5+X2H4mQs5ZKK4JXtTKAf5xiPTJek2zPWZdUZ/zPiViRKi/p5jP9dLKkZ7IfRjK8ymkIoDep7F9k+a7bJk5B21d5XWD0O3ZUtfbmqJQlDaUKg/UxImRpVnV9YoxW9+MA3sVB3Vx7GDYpRyJsD0ANLZMh2FLCmyJ3IIo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787656134; c=relaxed/simple; bh=TUIgN/sa9/6uBBWA4LxoxB40C8FVlYaGtN9aNjYFVCw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=neJ06Hkiz/nNW5lY2Zyu7o6yTO4cU+70wqppxCT5hGICXE3HU9UUquwL815boziqtjJrNlT0i2w6fr2y6oMOgA0IWomQ0ys6QChnupALSIz5ZkOUWeCx5m5JHsk/ITTOhZoOGEJnsh3JrklUGfekypfBegviVhEOieiIV/P5LyY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=D+MtPpva; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="D+MtPpva" Received: by smtp.kernel.org (Postfix) with ESMTPS id 56F02C2BCC7; Tue, 25 Aug 2026 11:08:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787656134; bh=TUIgN/sa9/6uBBWA4LxoxB40C8FVlYaGtN9aNjYFVCw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=D+MtPpvaXUuzdrihiMmS9LOSPa1ry+oI/z5de1G2pJif0qg6kGwzOLmOydUMVN8qL 4V6PwaXkHBgY2os3OwEtsC7R4PLlxGz5ItIFrSHnFGjfkdG9XmhxFwgJBdqMe9nTnZ qcpczR1l0lBBMlRBmSS1XWXaxiCyJnbNI/+yabgA/2MsE2TZtPe5PuwZyV03KTF7fq afUW1mm7KA5PJazDCtLri8BXL0vahmMpBawzUSekXKHYycvYjiHsR4wsnNsP4M1Bk8 igaC9S9S6nvBjDiSRdO715jBu9LAw71CXu8WGcAVzvAy5ZFL34LZnjhdf6PYuU86Uz I+1cizRJhLkpA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37AF6C61DBD; Tue, 25 Aug 2026 11:08:54 +0000 (UTC) From: Rohan Joshi via B4 Relay Date: Tue, 25 Aug 2026 16:40:57 +0530 Subject: [PATCH v4 1/2] dt-bindings: mmc: cdns,sdhci: Add CQE support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260825-cdns_sdhci_cqe-support-v4-1-e9f72e338373@cadence.com> References: <20260825-cdns_sdhci_cqe-support-v4-0-e9f72e338373@cadence.com> In-Reply-To: <20260825-cdns_sdhci_cqe-support-v4-0-e9f72e338373@cadence.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Masahiro Yamada , Adrian Hunter Cc: Rohan Joshi , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mparab@cadence.com, pawell@cadence.com, sjakhade@cadence.com, mpillai@cadence.com, razb@mobileye.com, blarson@amd.com X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787656261; l=2483; i=rohan1sj@cadence.com; s=20260406; h=from:subject:message-id; bh=tnxL6P/kgvSIMtCk+Ymrqyu224na2jvLAY8/B+g5f2g=; b=hxGduSniPK0Ou//Q34vXOH5FohiuZGGh6AbxKHkphdv3d7T4+J9rperQnanY5J8R2XvQRTftb h9nPjVbKuJ7Ac3Z9wUST+0qOdx/JVCvyTa6w1OUwEmIgjQp6wFciuzp X-Developer-Key: i=rohan1sj@cadence.com; a=ed25519; pk=YuwylizMVlVj8I4+VPMZ6xrFR2wyqJAWZyj90OVZgD0= X-Endpoint-Received: by B4 Relay for rohan1sj@cadence.com/20260406 with auth_id=723 X-Original-From: Rohan Joshi Reply-To: rohan1sj@cadence.com From: Rohan Joshi Add optional named resource "cqhci" to map the CQE register space. When present, it is used for CQHCI initialization and enable Command Queue Engine for eMMC. The "cqhci" space is optional to maintain compatibility for platforms that don't have CQE block. When absent, the controller can operate without the CQE block as routined. Update amd,pensando-elba platform to include this resource since Elba does have hardware block required for CQE! The original author for Elba, Brad Larson (blarson@amd.com) was able to confirm the CQE support. Signed-off-by: Rohan Joshi --- .../devicetree/bindings/mmc/cdns,sdhci.yaml | 28 ++++++++++++++++++= +--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Docume= ntation/devicetree/bindings/mmc/cdns,sdhci.yaml index 6c7317d13aa6..10bc9ac2073a 100644 --- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml @@ -22,7 +22,14 @@ properties: =20 reg: minItems: 1 - maxItems: 2 + maxItems: 3 + + reg-names: + minItems: 1 + items: + - const: hc + - enum: [bctl, cqhci] + - const: cqhci =20 interrupts: maxItems: 1 @@ -131,13 +138,27 @@ allOf: then: properties: reg: + minItems: 2 items: - description: Host controller registers - description: Elba byte-lane enable register for writes + - description: CQE (Command Queuing Engine) registers (optiona= l) + reg-names: + minItems: 2 + items: + - const: hc + - const: bctl + - const: cqhci else: properties: reg: - maxItems: 1 + items: + - description: Host Controller registers + - description: CQE (Command Queuing Engine) registers (optiona= l) + reg-names: + items: + - const: hc + - const: cqhci =20 unevaluatedProperties: false =20 @@ -145,7 +166,8 @@ examples: - | emmc: mmc@5a000000 { compatible =3D "socionext,uniphier-sd4hc", "cdns,sd4hc"; - reg =3D <0x5a000000 0x400>; + reg =3D <0x5a000000 0x400>, <0x5a000400 0x060>; + reg-names =3D "hc", "cqhci"; interrupts =3D <0 78 4>; clocks =3D <&clk 4>; bus-width =3D <8>; --=20 2.43.0 From nobody Mon Sep 28 06:36:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5BCC3FB7EB; Tue, 25 Aug 2026 11:08:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787656134; cv=none; b=b+jyj35u+PyaLXKaDAMLVs0EAtNH3l2g3rC2ZPA7IgeP9UiakG/TYmY9cfDudoGZD3lC364LoEFgxaIs+jaXKCwX6djZ4NYp2JsylJoRu1cvqlP/gaqtu5RarAa0Z9wkuQBp4GqBz4ui4SH+PXdeYD0he4x0xoKM84bPhKjeLJs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787656134; c=relaxed/simple; bh=MEsK8Hfi6QeopkryejcPosPkhpPyMDvxUA5tkoHT32k=; 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Tue, 25 Aug 2026 11:08:54 +0000 (UTC) From: Rohan Joshi via B4 Relay Date: Tue, 25 Aug 2026 16:40:58 +0530 Subject: [PATCH v4 2/2] mmc: sdhci-cadence: Add CQE support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260825-cdns_sdhci_cqe-support-v4-2-e9f72e338373@cadence.com> References: <20260825-cdns_sdhci_cqe-support-v4-0-e9f72e338373@cadence.com> In-Reply-To: <20260825-cdns_sdhci_cqe-support-v4-0-e9f72e338373@cadence.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Masahiro Yamada , Adrian Hunter Cc: Rohan Joshi , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mparab@cadence.com, pawell@cadence.com, sjakhade@cadence.com, mpillai@cadence.com, razb@mobileye.com, blarson@amd.com X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787656261; l=7039; i=rohan1sj@cadence.com; s=20260406; h=from:subject:message-id; bh=UdDZCZdTFb9J+GcBk4lpdt0hRYsXPZ4V3RxJcKMOXpU=; b=wQx3DKZxnxpz0gQgF4PCuQd28wzbXqt31ywcJfCvajzEi+tcjaN+T+maSlxsI2PVQBqIIXhf8 kLJV3SytvJZA8hx4Vy+Ytv+7DRbXa/H96nsdCzIC6JqCvkREfvsdkFI X-Developer-Key: i=rohan1sj@cadence.com; a=ed25519; pk=YuwylizMVlVj8I4+VPMZ6xrFR2wyqJAWZyj90OVZgD0= X-Endpoint-Received: by B4 Relay for rohan1sj@cadence.com/20260406 with auth_id=723 X-Original-From: Rohan Joshi Reply-To: rohan1sj@cadence.com From: Rohan Joshi Cadence host controller has optional CQE (Command Queue Engine). The HW presence of CQE is determined by an additional host capability register. Look up for "cqhci" register space from the DT and when present, initialize CQHCI engine. Signed-off-by: Rohan Joshi --- drivers/mmc/host/Kconfig | 1 + drivers/mmc/host/sdhci-cadence.c | 125 +++++++++++++++++++++++++++++++++++= ++-- 2 files changed, 122 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 4f060d3e5636..2cc8133e8ef3 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -293,6 +293,7 @@ config MMC_SDHCI_CADENCE depends on MMC_SDHCI_PLTFM depends on OF select MMC_SDHCI_IO_ACCESSORS + select MMC_CQHCI help This selects the Cadence SD/SDIO/eMMC driver. =20 diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cade= nce.c index 435603c8c00b..aa4431ef2b39 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -15,6 +15,8 @@ #include =20 #include "sdhci-pltfm.h" +#include "sdhci-cqhci.h" +#include "cqhci.h" =20 /* HRS - Host Register Set (specific to Cadence) */ #define SDHCI_CDNS_HRS04 0x10 /* PHY access port */ @@ -36,6 +38,10 @@ #define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5 #define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6 =20 +/* Host capabilities not covered by the standard capability registers (SRS= 16-SRS18) */ +#define SDHCI_CDNS_HRS30 0x78 /* Host capabilities */ +#define SDHCI_CDNS_HRS30_CQE_SUPPORTED BIT(0) + /* Read block gap */ #define SDHCI_CDNS_HRS37 0x94 /* interface mode select */ #define SDHCI_CDNS_HRS37_MODE_DS 0x0 @@ -88,6 +94,7 @@ struct sdhci_cdns_priv { void __iomem *ctl_addr; /* write control */ spinlock_t wrlock; /* write lock */ bool enhanced_strobe; + bool cqe_support; /* Command Queuing Engine support */ void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *= reg); struct reset_control *rst_hw; unsigned int nr_phy_params; @@ -385,6 +392,68 @@ static void sdhci_cdns_set_uhs_signaling(struct sdhci_= host *host, sdhci_set_uhs_signaling(host, timing); } =20 +static u32 sdhci_cdns_cqhci_irq(struct sdhci_host *host, u32 intmask) +{ + int cmd_err =3D 0; + int data_err =3D 0; + + /* return original intmask to be handled by other handlers if it's not a = CQE interrupt */ + if (!sdhci_cqe_irq(host, intmask, &cmd_err, &data_err)) + return intmask; + + cqhci_irq(host->mmc, cmd_err, data_err); + + return 0; +} + +static const struct cqhci_host_ops sdhci_cdns_cqhci_ops =3D { + .enable =3D sdhci_cqe_enable, + .disable =3D sdhci_cqe_disable, +}; + +static int sdhci_cdns_cqe_add_host(struct sdhci_host *host, struct platfor= m_device *pdev) +{ + struct cqhci_host *cq_host; + bool dma64; + int ret; + + ret =3D sdhci_setup_host(host); + if (ret) + return ret; + + cq_host =3D cqhci_pltfm_init(pdev); + if (IS_ERR(cq_host)) { + ret =3D PTR_ERR(cq_host); + dev_err_probe(&pdev->dev, ret, "cqhci platform init failed\n"); + goto cleanup; + } + + dma64 =3D host->flags & SDHCI_USE_64_BIT_DMA; + if (dma64) + cq_host->caps |=3D CQHCI_TASK_DESC_SZ_128; + + cq_host->ops =3D &sdhci_cdns_cqhci_ops; + + host->mmc->caps2 |=3D MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; + + ret =3D cqhci_init(cq_host, host->mmc, dma64); + if (ret) { + dev_err_probe(&pdev->dev, ret, "cqhci init failed\n"); + goto cleanup; + } + + /* add host to MMC subsystem */ + ret =3D __sdhci_add_host(host); + if (ret) + goto cleanup; + + return 0; + +cleanup: + sdhci_cleanup_host(host); + return ret; +} + /* Elba control register bits [6:3] are byte-lane enables */ #define ELBA_BYTE_ENABLE_MASK(x) ((x) << 3) =20 @@ -445,8 +514,9 @@ static const struct sdhci_ops sdhci_elba_ops =3D { .set_clock =3D sdhci_set_clock, .get_timeout_clock =3D sdhci_cdns_get_timeout_clock, .set_bus_width =3D sdhci_set_bus_width, - .reset =3D sdhci_reset, + .reset =3D sdhci_and_cqhci_reset, .set_uhs_signaling =3D sdhci_cdns_set_uhs_signaling, + .irq =3D sdhci_cdns_cqhci_irq, }; =20 static int elba_drv_init(struct platform_device *pdev) @@ -474,9 +544,10 @@ static const struct sdhci_ops sdhci_cdns_ops =3D { .set_clock =3D sdhci_set_clock, .get_timeout_clock =3D sdhci_cdns_get_timeout_clock, .set_bus_width =3D sdhci_set_bus_width, - .reset =3D sdhci_reset, + .reset =3D sdhci_and_cqhci_reset, .platform_execute_tuning =3D sdhci_cdns_execute_tuning, .set_uhs_signaling =3D sdhci_cdns_set_uhs_signaling, + .irq =3D sdhci_cdns_cqhci_irq, }; =20 static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data =3D { @@ -553,6 +624,8 @@ static int sdhci_cdns_probe(struct platform_device *pde= v) int ret; struct device *dev =3D &pdev->dev; static const u16 version =3D SDHCI_SPEC_400 << SDHCI_SPEC_VER_SHIFT; + bool cqe_enabled; + u32 host_caps; =20 clk =3D devm_clk_get_enabled(dev, NULL); if (IS_ERR(clk)) @@ -608,7 +681,43 @@ static int sdhci_cdns_probe(struct platform_device *pd= ev) host->mmc_host_ops.card_hw_reset =3D sdhci_cdns_mmc_hw_reset; } =20 - return sdhci_add_host(host); + host_caps =3D readl(priv->hrs_addr + SDHCI_CDNS_HRS30); + + /* + * CQE is enabled only when both conditions are met: + * 1. Hardware reports CQE support via HRS30[0]. + * 2. DT provides a named "cqhci" register space. + */ + cqe_enabled =3D (host_caps & SDHCI_CDNS_HRS30_CQE_SUPPORTED) && + !!platform_get_resource_byname(pdev, IORESOURCE_MEM, "cqhci"); + + if ((host_caps & SDHCI_CDNS_HRS30_CQE_SUPPORTED) && !cqe_enabled) + dev_dbg(dev, "CQE supported by hardware but no 'cqhci' register space in= DT, disabling\n"); + + if (cqe_enabled) { + priv->cqe_support =3D true; + ret =3D sdhci_cdns_cqe_add_host(host, pdev); + } else { + ret =3D sdhci_add_host(host); + } + + return ret; +} + +static int sdhci_cdns_suspend(struct device *dev) +{ + struct sdhci_host *host =3D dev_get_drvdata(dev); + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_cdns_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + int ret; + + if (priv->cqe_support) { + ret =3D cqhci_suspend(host->mmc); + if (ret) + return ret; + } + + return sdhci_pltfm_suspend(dev); } =20 static int sdhci_cdns_resume(struct device *dev) @@ -630,6 +739,14 @@ static int sdhci_cdns_resume(struct device *dev) if (ret) goto disable_clk; =20 + /* Resume CQE if enabled */ + if (priv->cqe_support) { + ret =3D cqhci_resume(host->mmc); + if (ret) + dev_warn(dev, "CQE resume failed (%pe), continuing without CQE\n", + ERR_PTR(ret)); + } + return 0; =20 disable_clk: @@ -638,7 +755,7 @@ static int sdhci_cdns_resume(struct device *dev) return ret; } =20 -static DEFINE_SIMPLE_DEV_PM_OPS(sdhci_cdns_pm_ops, sdhci_pltfm_suspend, sd= hci_cdns_resume); +static DEFINE_SIMPLE_DEV_PM_OPS(sdhci_cdns_pm_ops, sdhci_cdns_suspend, sdh= ci_cdns_resume); =20 static const struct of_device_id sdhci_cdns_match[] =3D { { --=20 2.43.0