From nobody Mon Sep 28 06:37:49 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 675EF3D6463; Tue, 25 Aug 2026 10:48:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787654920; cv=none; b=gPNZa5C4RWcCxE89CJFW+MtdCJycveuiS3l9kMjD/ovL97SPPz32252Lr1s6zwjBcSEQTSkaEKjNXHgIukXSTrWnNEjjSll072cslXV7E8pjpsLnk8dZqmGIbjnvX71Zz6VKSkUjRdUNtWJNv6WDa40C7eokbpkahOO7uRkB0EY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787654920; c=relaxed/simple; bh=Vj1DHrmGR0tyVO+ZlDxsQgZLtvtVuNtuX+cbxrGaewI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RfK8QCOFKRBdFRkCGUFA6l1T9J0rS3hO+I7ZuVdPNzB4DXYcH8+Qhr+7ih9Ble99xRJXnJLE18fFpix4kHsqkmDYseO2IDVZfkKUWcWXbo+w8uTxdBHo9dLKL59TjfY2H98tMOm3HcWOBKiWOyvQ6CjsKho5j4ZMUlxPm6D31do= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Wlu61ztG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Wlu61ztG" Received: by smtp.kernel.org (Postfix) with ESMTPS id 15BDAC2BCC7; Tue, 25 Aug 2026 10:48:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787654920; bh=Vj1DHrmGR0tyVO+ZlDxsQgZLtvtVuNtuX+cbxrGaewI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Wlu61ztGYvIiCAkcwKONvj5YgDAk45PsbLBjX53+IlGR8L02chPEMJZoBRrI471D1 rKMyU2cMFHhaiWMka6lqdkFwz6qf/fhvJIjv36I2fIIEtcDz2Xb+OSRrBGe929upDY N2wv92QH/fDYwliDSd72/+h5rBc7UQaU1OQWkKnZyPpEL7JyG/TpUcIOzj1/8Z1q5D HzuaOeyJ2FlnY7hftrm4+T32EfLUH6Tcc7ZaElS7mfY46vwb1ejtfK00QaPpN/P5Rq oPcGkbXIbFkKrYR+y2cX7nrMD1sLWVk6XmK1W1qjVTmze75jOLC+zj9Ukbel90HECB CvVfEQcdPHOmg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E69AEC61DB6; Tue, 25 Aug 2026 10:48:39 +0000 (UTC) From: Colin Huang via B4 Relay Date: Tue, 25 Aug 2026 18:47:42 +0800 Subject: [PATCH v6 01/12] dt-bindings: arm: aspeed: Add Anacapa EVT1 EVT2 DVT board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260825-anacapa-devlop-phase-devicetree-v6-1-9059a2a279ce@gmail.com> References: <20260825-anacapa-devlop-phase-devicetree-v6-0-9059a2a279ce@gmail.com> In-Reply-To: <20260825-anacapa-devlop-phase-devicetree-v6-0-9059a2a279ce@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang , Conor Dooley X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787654905; l=985; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=Sw+OWK3YcWaJDMswc4oOvzoue3GKb6ZepbG6V99kpbc=; b=4A0y8x/hf3KaXM3cEV4tdE3POr/Pbjc3QPcf3gzD6S1OIXiqLc1psKaEhE352IbNumiwWyrXF 8tYTg9zCqU4BkQWdDFtOJ9M/T7H/tKeYNOY8xhej553QdnkEf1SzRFg X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Colin Huang Document Anacapa BMC EVT1, EVT2, and DVT compatibles. Signed-off-by: Colin Huang Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Doc= umentation/devicetree/bindings/arm/aspeed/aspeed.yaml index dd7996960de3..1c1570143bd9 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -84,6 +84,9 @@ properties: - asus,ast2600-kommando-ipmi-card - asus,x4tf-bmc - facebook,anacapa-bmc + - facebook,anacapa-bmc-dvt + - facebook,anacapa-bmc-evt1 + - facebook,anacapa-bmc-evt2 - facebook,bletchley-bmc - facebook,catalina-bmc - facebook,clemente-bmc --=20 2.34.1 From nobody Mon Sep 28 06:37:49 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A6723EC80C; Tue, 25 Aug 2026 10:48:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787654920; cv=none; b=iwWgBzgZpGkxlvRmYUpO+pZfVJE61RoRVF2Gol1ebBcZxrnn2srxH9mG6F9c0k21oUJshiygDsH9OujW1XePzz3Ki7hj8/SW/QkPiH/nJFDB795XKf1aijMYZg3SmkJuGS/6SpDkQsczxYqGZPrAH9ZyVeqa+5YnknuTqwh5fpE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787654920; c=relaxed/simple; bh=QnTKluo5M215tmGyZsejEK0C9UHUOMoA10zjUlUOcss=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UJjkTdZhzA9dB+bI9+lYVJM0vgMOZQQK3xzBimyzW8o6cwrnIeyR75V+DzH+5mwhnoNnWDv/fLsNQyQ0fK1t9Z+Cc91nbv9V91By1BlRYWNfST/tk2aOP/H4WZ1F7IOEwjAesWFf79tU+C1iR0D8AG6OvCe+oWFBdradsN8BkfQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rqheA5Ih; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rqheA5Ih" Received: by smtp.kernel.org (Postfix) with ESMTPS id 2B1D9C2BCFB; Tue, 25 Aug 2026 10:48:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787654920; bh=QnTKluo5M215tmGyZsejEK0C9UHUOMoA10zjUlUOcss=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=rqheA5IhOnlarJIIo8G7dckjY9ACCVTIYM8yYxxzvDs5lxpWMVlAHSPvw+6X0gC7T AI/NialElVOiATa9nGoSs42PJjq4hgf+CDogCrZtJT5izRnZauNC6JpIglYtFbwCNy US5FWayNImCHnHqhmMxPGcF55FOhrQM7Wmcq5MaHc8VruXS3h8vGjVOGFJxJl++0J6 nCPKJ3YvL9WidVpidGt1kiH/tLfipqRsW6V12o7XkzjSKs8BlbUJ6kXXUMcP6zqLdo lM3OgOQrz1eqOQvzOVedRFvqyM9T7P/EXfShtdXZS/5IhHw4Gk0sJLgViynAI2kbHF L0kGfy38VWdsA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B453C61DBD; Tue, 25 Aug 2026 10:48:40 +0000 (UTC) From: Colin Huang via B4 Relay Date: Tue, 25 Aug 2026 18:47:43 +0800 Subject: [PATCH v6 02/12] ARM: dts: aspeed: anacapa: Add EVT1 devicetree and point wrapper to it Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260825-anacapa-devlop-phase-devicetree-v6-2-9059a2a279ce@gmail.com> References: <20260825-anacapa-devlop-phase-devicetree-v6-0-9059a2a279ce@gmail.com> In-Reply-To: <20260825-anacapa-devlop-phase-devicetree-v6-0-9059a2a279ce@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787654905; l=47273; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=r9DU7cAfC8D29w0l4Q0jVQRjTt8tLeBrfEEru6DmgDw=; b=eEK6lygrAMhusyE3HdLrwyJXAsHGBiLiggq4WEoofOyu3lzJSY1017apPVL27+daY+yx3zSoc PykrEIgu61ABOjrjI4rOcP6X4hspub5eryy/8YwvRg+jkZVqdT0TEc9 X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Colin Huang This commit introduces an EVT1 development-phase devicetree for the Facebook Anacapa BMC. It updates the top-level wrapper DTS to include the EVT1 hardware revision file. =C2=A0 A dedicated EVT1 DTS is added as the base revision for subsequent board variants. The EVT1 devicetree is derived from the original Anacapa devicetree and incorporates several cleanups and fixes: - Remove redundant vhub pinctrl-names - Use default SPI2 memory mapping - Fix dt-check-style strict violations Remove p3v3_bmc_aux node to fix '[unused-lable]' warning. =C2=A0 The top-level aspeed-bmc-facebook-anacapa.dts now includes the EVT1 devicetree, allowing EVT2 and DVT revisions to inherit from a common baseline while preserving a single build target for Anacapa. Signed-off-by: Colin Huang --- .../aspeed/aspeed-bmc-facebook-anacapa-evt1.dts | 1120 ++++++++++++++++= ++++ .../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 1078 +---------------= --- 2 files changed, 1121 insertions(+), 1077 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts new file mode 100644 index 000000000000..25412cadb30a --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts @@ -0,0 +1,1120 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/dts-v1/; +#include "aspeed-g6.dtsi" +#include +#include + +/ { + compatible =3D "facebook,anacapa-bmc-evt1", "aspeed,ast2600"; + model =3D "Facebook Anacapa BMC"; + + aliases { + i2c16 =3D &i2c0mux0ch0; + i2c17 =3D &i2c0mux0ch1; + i2c18 =3D &i2c0mux0ch2; + i2c19 =3D &i2c0mux0ch3; + i2c20 =3D &i2c1mux0ch0; + i2c21 =3D &i2c1mux0ch1; + i2c22 =3D &i2c1mux0ch2; + i2c23 =3D &i2c1mux0ch3; + i2c24 =3D &i2c4mux0ch0; + i2c25 =3D &i2c4mux0ch1; + i2c26 =3D &i2c4mux0ch2; + i2c27 =3D &i2c4mux0ch3; + i2c28 =3D &i2c4mux0ch4; + i2c29 =3D &i2c4mux0ch5; + i2c30 =3D &i2c4mux0ch6; + i2c31 =3D &i2c4mux0ch7; + i2c32 =3D &i2c8mux0ch0; + i2c33 =3D &i2c8mux0ch1; + i2c34 =3D &i2c8mux0ch2; + i2c35 =3D &i2c8mux0ch3; + i2c36 =3D &i2c10mux0ch0; + i2c37 =3D &i2c10mux0ch1; + i2c38 =3D &i2c10mux0ch2; + i2c39 =3D &i2c10mux0ch3; + i2c40 =3D &i2c10mux0ch4; + i2c41 =3D &i2c10mux0ch5; + i2c42 =3D &i2c10mux0ch6; + i2c43 =3D &i2c10mux0ch7; + i2c44 =3D &i2c11mux0ch0; + i2c45 =3D &i2c11mux0ch1; + i2c46 =3D &i2c11mux0ch2; + i2c47 =3D &i2c11mux0ch3; + i2c48 =3D &i2c11mux0ch4; + i2c49 =3D &i2c11mux0ch5; + i2c50 =3D &i2c11mux0ch6; + i2c51 =3D &i2c11mux0ch7; + i2c52 =3D &i2c13mux0ch0; + i2c53 =3D &i2c13mux0ch1; + i2c54 =3D &i2c13mux0ch2; + i2c55 =3D &i2c13mux0ch3; + i2c56 =3D &i2c13mux0ch4; + i2c57 =3D &i2c13mux0ch5; + i2c58 =3D &i2c13mux0ch6; + i2c59 =3D &i2c13mux0ch7; + serial0 =3D &uart1; + serial1 =3D &uart2; + serial2 =3D &uart3; + serial3 =3D &uart4; + serial4 =3D &uart5; + }; + + chosen { + stdout-path =3D "serial4:57600n8"; + }; + + iio-hwmon { + compatible =3D "iio-hwmon"; + io-channels =3D <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 2>; + }; + + leds { + compatible =3D "gpio-leds"; + + led-0 { + gpios =3D <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; + label =3D "bmc_heartbeat_amber"; + linux,default-trigger =3D "heartbeat"; + }; + + led-1 { + default-state =3D "off"; + gpios =3D <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>; + label =3D "fp_id_amber"; + }; + }; + + memory@80000000 { + reg =3D <0x80000000 0x80000000>; + device_type =3D "memory"; + }; + + reserved-memory { + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + + gfx_memory: framebuffer { + compatible =3D "shared-dma-pool"; + alignment =3D <0x01000000>; + reusable; + size =3D <0x01000000>; + }; + + video_engine_memory: video { + compatible =3D "shared-dma-pool"; + alignment =3D <0x00100000>; + reusable; + size =3D <0x02c00000>; + }; + }; + + spi { + compatible =3D "spi-gpio"; + #address-cells =3D <1>; + cs-gpios =3D <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; + + miso-gpios =3D <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; + mosi-gpios =3D <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + num-chipselects =3D <1>; + sck-gpios =3D <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + #size-cells =3D <0>; + + status =3D "okay"; + + tpm@0 { + compatible =3D "infineon,slb9670", "tcg,tpm_tis-spi"; + reg =3D <0>; + spi-max-frequency =3D <33000000>; + }; + }; +}; + +&adc0 { + pinctrl-0 =3D <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; + pinctrl-names =3D "default"; + aspeed,int-vref-microvolt =3D <2500000>; + + status =3D "okay"; +}; + +&adc1 { + pinctrl-0 =3D <&pinctrl_adc10_default>; + pinctrl-names =3D "default"; + aspeed,int-vref-microvolt =3D <2500000>; + + status =3D "okay"; +}; + +&ehci1 { + status =3D "okay"; +}; + +&fmc { + status =3D "okay"; + + flash@0 { + label =3D "bmc"; + spi-max-frequency =3D <50000000>; + m25p,fast-read; + + status =3D "okay"; +#include "openbmc-flash-layout-128.dtsi" + }; + + flash@1 { + label =3D "alt-bmc"; + spi-max-frequency =3D <50000000>; + m25p,fast-read; + + status =3D "okay"; + }; +}; + +&gfx { + memory-region =3D <&gfx_memory>; + + status =3D "okay"; +}; + +&gpio0 { + gpio-line-names =3D + + /*A0-A7*/ + "","","","","","","","", + + /*B0-B7*/ + "BATTERY_DETECT", "", "", "BMC_READY", + "", "FM_ID_LED", "", "", + + /*C0-C7*/ + "","","","","","","","", + + /*D0-D7*/ + "","","","","","","","", + + /*E0-E7*/ + "","","","","","","","", + + /*F0-F7*/ + "","","","","","","","", + + /*G0-G7*/ + "FM_MUX1_SEL", "", "", "", + "", "", "FM_DEBUG_PORT_PRSNT_N", "FM_BMC_DBP_PRESENT_N", + + /*H0-H7*/ + "","","","","","","","", + + /*I0-I7*/ + "", "", "", "", + "", "FLASH_WP_STATUS", "BMC_JTAG_MUX_SEL", "", + + /*J0-J7*/ + "","","","","","","","", + + /*K0-K7*/ + "","","","","","","","", + + /*L0-L7*/ + "","","","","","","","", + + /*M0-M7*/ + "", "BMC_FRU_WP", "", "", + "", "", "", "", + + /*N0-N7*/ + "LED_POSTCODE_0", "LED_POSTCODE_1", "LED_POSTCODE_2", "LED_POSTCODE_3", + "LED_POSTCODE_4", "LED_POSTCODE_5", "LED_POSTCODE_6", "LED_POSTCODE_7", + + /*O0-O7*/ + "","","","","","","","", + + /*P0-P7*/ + "PWR_BTN_BMC_BUF_N", "", "ID_RST_BTN_BMC_N", "", + "PWR_LED", "", "", "BMC_HEARTBEAT_N", + + /*Q0-Q7*/ + "","","","","","","","", + + /*R0-R7*/ + "","","","","","","","", + + /*S0-S7*/ + "", "", "SYS_BMC_PWRBTN_N", "", + "", "", "", "RUN_POWER_FAULT", + + /*T0-T7*/ + "","","","","","","","", + + /*U0-U7*/ + "","","","","","","","", + + /*V0-V7*/ + "","","","","","","","", + + /*W0-W7*/ + "","","","","","","","", + + /*X0-X7*/ + "","","","","","","","", + + /*Y0-Y7*/ + "","","","","","","","", + + /*Z0-Z7*/ + "SPI_BMC_TPM_CS2_N", "", "", "SPI_BMC_TPM_CLK", + "SPI_BMC_TPM_MOSI", "SPI_BMC_TPM_MISO", "", ""; +}; + +&gpio1 { + gpio-line-names =3D + /*18A0-18A7*/ + "","","","","","","","", + + /*18B0-18B7*/ + "","","","", + "FM_BOARD_BMC_REV_ID0", "FM_BOARD_BMC_REV_ID1", + "FM_BOARD_BMC_REV_ID2", "", + + /*18C0-18C7*/ + "","","","","","","","", + + /*18D0-18D7*/ + "","","","","","","","", + + /*18E0-18E3*/ + "FM_BMC_PROT_LS_EN", "AC_PWR_BMC_BTN_N", "", ""; +}; + +// L Bridge Board +&i2c0 { + status =3D "okay"; + + eeprom@50 { + compatible =3D "atmel,24c2048"; + reg =3D <0x50>; + pagesize =3D <128>; + }; + + i2c-mux@70 { + compatible =3D "nxp,pca9546"; + reg =3D <0x70>; + #address-cells =3D <1>; + i2c-mux-idle-disconnect; + #size-cells =3D <0>; + + i2c0mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c0mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c0mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c0mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// R Bridge Board +&i2c1 { + status =3D "okay"; + + eeprom@50 { + compatible =3D "atmel,24c2048"; + reg =3D <0x50>; + pagesize =3D <128>; + }; + + i2c-mux@70 { + compatible =3D "nxp,pca9546"; + reg =3D <0x70>; + #address-cells =3D <1>; + i2c-mux-idle-disconnect; + #size-cells =3D <0>; + + i2c1mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c1mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c1mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c1mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// MB - E1.S +&i2c4 { + status =3D "okay"; + + i2c-mux@70 { + compatible =3D "nxp,pca9548"; + reg =3D <0x70>; + #address-cells =3D <1>; + i2c-mux-idle-disconnect; + #size-cells =3D <0>; + + i2c4mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c4mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c4mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c4mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c4mux0ch4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c4mux0ch5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c4mux0ch6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c4mux0ch7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// AMC +&i2c5 { + status =3D "okay"; +}; + +// MB +&i2c6 { + status =3D "okay"; + + // HPM FRU + eeprom@50 { + compatible =3D "atmel,24c256"; + reg =3D <0x50>; + }; +}; + +// SCM +&i2c7 { + status =3D "okay"; +}; + +// MB - PDB +&i2c8 { + status =3D "okay"; + + i2c-mux@72 { + compatible =3D "nxp,pca9546"; + reg =3D <0x72>; + #address-cells =3D <1>; + i2c-mux-idle-disconnect; + #size-cells =3D <0>; + + i2c8mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@1f { + compatible =3D "ti,adc128d818"; + reg =3D <0x1f>; + ti,mode =3D /bits/ 8 <1>; + }; + + gpio@22 { + compatible =3D "nxp,pca9555"; + reg =3D <0x22>; + #gpio-cells =3D <2>; + gpio-controller; + + gpio-line-names =3D + "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TEMP75_U8_ALERT_R_N", + "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP", + "RPDB_FAN_CT_FAN_FAIL_R_N", "", + "", "", + "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N", + "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N", + "RPDB_I2C_P12V_MB_VRM_ALERT_R_N", + "RPDB_I2C_P12V_STBY_VRM_ALERT_R_N", + "RPDB_PGD_P3V3_STBY_PWRGD_R", + "RPDB_P12V_STBY_VRM_PWRGD_BUF_R"; + interrupt-parent =3D <&sgpiom0>; + + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + }; + + gpio@24 { + compatible =3D "nxp,pca9555"; + reg =3D <0x24>; + #gpio-cells =3D <2>; + gpio-controller; + + gpio-line-names =3D + "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", + "RPDB_PWRGD_P50V_HSC4_SYS_R", + "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", + "RPDB_P50V_FAN1_R2_PG", "RPDB_P50V_FAN2_R2_PG", + "RPDB_P50V_FAN3_R2_PG", "RPDB_P50V_FAN4_R2_PG", + "", "RPDB_FAN1_PRSNT_N_R", + "", "RPDB_FAN2_PRSNT_N_R", + "RPDB_FAN3_PRSNT_N_R", "RPDB_FAN4_PRSNT_N_R", + "", ""; + interrupt-parent =3D <&sgpiom0>; + + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + }; + + // R-PDB FRU + eeprom@50 { + compatible =3D "atmel,24c128"; + reg =3D <0x50>; + }; + }; + + i2c8mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + gpio@22 { + compatible =3D "nxp,pca9555"; + reg =3D <0x22>; + #gpio-cells =3D <2>; + gpio-controller; + + gpio-line-names =3D + "LPDB_FAN_FULL_SPEED_R_N","LPDB_I2C_TEMP75_U8_ALERT_R_N", + "LPDB_I2C_TMP432_U29_ALERT_R_N","LPDB_GLOBAL_WP", + "LPDB_FAN_CT_FAN_FAIL_R_N","", + "","", + "LPDB_ALERT_P50V_HSC0_R_N","LPDB_ALERT_P50V_HSC1_R_N", + "LPDB_ALERT_P50V_HSC5_R_N","LPDB_I2C_P12V_SW_VRM_ALERT_R_N", + "LPDB_EAM0_PRSNT_MOS_N_R","LPDB_EAM1_PRSNT_MOS_N_R", + "LPDB_PWRGD_P50V_HSC5_SYS_R",""; + interrupt-parent =3D <&sgpiom0>; + + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + }; + + gpio@24 { + compatible =3D "nxp,pca9555"; + reg =3D <0x24>; + #gpio-cells =3D <2>; + gpio-controller; + + gpio-line-names =3D + "LPDB_P50V_FAN1_R2_PG","LPDB_P50V_FAN2_R2_PG", + "LPDB_P50V_FAN3_R2_PG","LPDB_P50V_FAN4_R2_PG", + "LPDB_P50V_FAN5_R2_PG","LPDB_FAN1_PRSNT_N_R", + "LPDB_FAN2_PRSNT_N_R","LPDB_FAN3_PRSNT_N_R", + "LPDB_FAN4_PRSNT_N_R","LPDB_FAN5_PRSNT_N_R", + "","", + "","", + "",""; + interrupt-parent =3D <&sgpiom0>; + + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + }; + + // L-PDB FRU + eeprom@50 { + compatible =3D "atmel,24c128"; + reg =3D <0x50>; + }; + }; + + i2c8mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c8mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// SCM +&i2c9 { + status =3D "okay"; + + // SCM FRU + eeprom@50 { + compatible =3D "atmel,24c128"; + reg =3D <0x50>; + }; + + // BSM FRU + eeprom@56 { + compatible =3D "atmel,24c64"; + reg =3D <0x56>; + }; +}; + +// R Bridge Board +&i2c10 { + status =3D "okay"; + + i2c-mux@71 { + compatible =3D "nxp,pca9548"; + reg =3D <0x71>; + #address-cells =3D <1>; + i2c-mux-idle-disconnect; + #size-cells =3D <0>; + + i2c10mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c10mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c10mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c10mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c10mux0ch4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c10mux0ch5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + gpio@22 { + compatible =3D "nxp,pca9555"; + reg =3D <0x22>; + #gpio-cells =3D <2>; + gpio-controller; + + gpio-line-names =3D + "","", + "","RBB_CPLD_REFRESH_IN_PRGRS_R_L", + "RBB_EAM0_NIC_CBL_PRSNT_R_L","RBB_EAM1_NIC_CBL_PRSNT_R_L", + "RBB_AINIC_JTAG_MUX_R2_SEL","RBB_SPI_MUX0_R2_SEL", + "RBB_AINIC_PRSNT_R_L","RBB_AINIC_OE_R_N", + "RBB_AINIC_BOARD_R2_ID","RBB_RST_USB2_HUB_R_N", + "RBB_RST_FT4222_R_N","RBB_RST_MCP2210_R_N", + "",""; + }; + + // R Bridge Board FRU + eeprom@52 { + compatible =3D "atmel,24c256"; + reg =3D <0x52>; + }; + }; + + i2c10mux0ch6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c10mux0ch7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// L Bridge Board +&i2c11 { + status =3D "okay"; + + i2c-mux@71 { + compatible =3D "nxp,pca9548"; + reg =3D <0x71>; + #address-cells =3D <1>; + i2c-mux-idle-disconnect; + #size-cells =3D <0>; + + i2c11mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c11mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c11mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c11mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c11mux0ch4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c11mux0ch5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + gpio@22 { + compatible =3D "nxp,pca9555"; + reg =3D <0x22>; + #gpio-cells =3D <2>; + gpio-controller; + + gpio-line-names =3D + "","", + "","LBB_CPLD_REFRESH_IN_PRGRS_R_L", + "LBB_EAM0_NIC_CBL_PRSNT_R_L","LBB_EAM1_NIC_CBL_PRSNT_R_L", + "LBB_AINIC_JTAG_MUX_R2_SEL","LBB_SPI_MUX0_R2_SEL", + "LBB_AINIC_PRSNT_R_L","LBB_AINIC_OE_R_N", + "LBB_AINIC_BOARD_R2_ID","LBB_RST_USB2_HUB_R_N", + "LBB_RST_FT4222_R_N","LBB_RST_MCP2210_R_N", + "",""; + }; + + // L Bridge Board FRU + eeprom@52 { + compatible =3D "atmel,24c256"; + reg =3D <0x52>; + }; + }; + + i2c11mux0ch6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c11mux0ch7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// Debug Card +&i2c12 { + status =3D "okay"; +}; + +// MB +&i2c13 { + status =3D "okay"; + + i2c-mux@70 { + compatible =3D "nxp,pca9548"; + reg =3D <0x70>; + #address-cells =3D <1>; + i2c-mux-idle-disconnect; + #size-cells =3D <0>; + + i2c13mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c13mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c13mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c13mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@1f { + compatible =3D "ti,adc128d818"; + reg =3D <0x1f>; + ti,mode =3D /bits/ 8 <1>; + }; + }; + + i2c13mux0ch4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + // HPM BRD ID FRU + eeprom@51 { + compatible =3D "atmel,24c256"; + reg =3D <0x51>; + }; + }; + + i2c13mux0ch5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c13mux0ch6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c13mux0ch7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + nfc@28 { + compatible =3D "nxp,nxp-nci-i2c"; + reg =3D <0x28>; + + enable-gpios =3D <&sgpiom0 241 GPIO_ACTIVE_HIGH>; + interrupt-parent =3D <&sgpiom0>; + + interrupts =3D <156 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; +}; + +// SCM +&i2c14 { + status =3D "okay"; +}; + +&i2c15 { + status =3D "okay"; +}; + +&kcs2 { + aspeed,lpc-io-reg =3D <0xca8>; + + status =3D "okay"; +}; + +&kcs3 { + aspeed,lpc-io-reg =3D <0xca2>; + + status =3D "okay"; +}; + +&lpc_ctrl { + status =3D "okay"; +}; + +&mac2 { + pinctrl-0 =3D <&pinctrl_ncsi3_default>; + pinctrl-names =3D "default"; + use-ncsi; + + status =3D "okay"; +}; + +&sgpiom0 { + bus-frequency =3D <2000000>; + gpio-line-names =3D + /*in - out - in - out */ + /* A0-A7 line 0-15 */ + "", "FM_CPU0_SYS_RESET_N", "", "CPU0_KBRST_N", + "", "FM_CPU0_PROCHOT_trigger_N", "", "FM_CLR_CMOS_R_P0", + "", "Force_I3C_SEL", "", "SYSTEM_Force_Run_AC_Cycle", + "", "", "", "", + + /* B0-B7 line 16-31 */ + "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", + "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", + "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", + "Channel3_leakage", "FM_CPU0_NMI_SYNC_FLOOD_N", + "Channel4_leakage_Manifold2", "", + "Channel5_leakage_EAM1", "", + "Channel6_leakage_CPU_DIMM", "", + "Channel7_leakage_EAM2", "", + + /* C0-C7 line 32-47 */ + "RSVD_RMC_GPIO3", "", "", "", + "", "", "", "", + "LEAK_DETECT_RMC_N", "JTAG_CPLD_TRST_R_N", "", "", + "", "", "", "", + + /* D0-D7 line 48-63 */ + "PWRGD_PDB_EAMHSC0_CPLD_PG_R", "", + "PWRGD_PDB_EAMHSC1_CPLD_PG_R", "", + "PWRGD_PDB_EAMHSC2_CPLD_PG_R", "", + "PWRGD_PDB_EAMHSC3_CPLD_PG_R", "", + "AMC_BRD_PRSNT_CPLD_L", "", "", "", + "", "", "", "", + + /* E0-E7 line 64-79 */ + "AMC_PDB_EAMHSC0_CPLD_EN_R", "", + "AMC_PDB_EAMHSC1_CPLD_EN_R", "", + "AMC_PDB_EAMHSC2_CPLD_EN_R", "", + "AMC_PDB_EAMHSC3_CPLD_EN_R", "", + "", "", "", "", + "", "", "", "", + + /* F0-F7 line 80-95 */ + "PWRGD_PVDDCR_CPU1_P0", "SGPIO_READY", + "PWRGD_PVDDCR_CPU0_P0", "", + "", "", "", "", + "", "", "", "", + + /* G0-G7 line 96-111 */ + "L_PRSNT_EDSFF0_N", "", + "L_PRSNT_EDSFF1_N", "", + "R_PRSNT_EDSFF2_N", "", + "R_PRSNT_EDSFF3_N", "", + "HPM_EDSFF_PG", "", + "PWRGD_CHEH_CPU0_FPGA", "", + "PWRGD_CHAD_CPU0_FPGA", "FM_BMC_READY_PLD", + "", "", + + /* H0-H7 line 112-127 */ + "PWRGD_P3V3", "", + "P12V_DDR_IP_PWRGD_R", "", + "P12V_DDR_AH_PWRGD_R", "", + "PWRGD_P12V_VRM1_CPLD_PG_R", "", + "PWRGD_P12V_VRM0_CPLD_PG_R", "", + "PWRGD_PDB_HSC4_CPLD_PG_R", "", + "PWRGD_PVDD18_S5_P0_PG", "", + "PWRGD_PVDD33_S5_P0_PG", "", + + /* I0-I7 line 128-143 */ + "EAM0_BRD_PRSNT_R_L", "", + "EAM1_BRD_PRSNT_R_L", "", + "EAM2_BRD_PRSNT_R_L", "", + "EAM3_BRD_PRSNT_R_L", "", + "EAM0_CPU_MOD_PWR_GD_R", "", + "EAM1_CPU_MOD_PWR_GD_R", "", + "PRSNT_EDSFF_BOOT_N", "", + "EAM3_CPU_MOD_PWR_GD_R", "", + + /* J0-J7 line 144-159 */ + "PRSNT_L_BIRDGE_R", "", + "PRSNT_R_BIRDGE_R", "", + "BRIDGE_L_MAIN_PG_R", "", + "BRIDGE_R_MAIN_PG_R", "", + "BRIDGE_L_STBY_PG_R", "", + "BRIDGE_R_STBY_PG_R", "", + "", "", "", "", + + /* K0-K7 line 160-175 */ + "ADC_I2C_ALERT_N", "", + "TEMP_I2C_ALERT_R_L", "", + "CPU0_VR_SMB_ALERT_CPLD_N", "", + "COVER_INTRUDER_R_N", "", + "HANDLE_INTRUDER_CPLD_N", "", + "IRQ_MCIO_CPLD_WAKE_R_N", "", + "APML_CPU0_ALERT_R_N", "", + "PDB_ALERT_R_N", "", + + /* L0-L7 line 176-191 */ + "L_EDSFF0_PG", "", "L_EDSFF1_PG", "", + "R_EDSFF2_PG", "", "R_EDSFF3_PG", "", + "CPU0_CORETYPE0", "", "CPU0_CORETYPE1", "", + "CPU0_CORETYPE2", "", "FM_BIOS_POST_CMPLT_R_N", "", + + /* M0-M7 line 192-207 */ + "EAM0_SMERR_CPLD_R_L", "", + "EAM1_SMERR_CPLD_R_L", "", + "EAM2_SMERR_CPLD_R_L", "", + "EAM3_SMERR_CPLD_R_L", "", + "CPU0_SMERR_N_R", "", + "CPU0_NV_SAVE_N_R", "", + "PDB_PWR_LOSS_CPLD_N", "", + "IRQ_BMC_SMI_ACTIVE_R_N", "", + + /* N0-N7 line 208-223 */ + "AMCROT_BMC_S5_RDY_R", "", + "AMC_RDY_R", "", + "AMC_STBY_PGOOD_R", "", + "CPU_AMC_SLP_S5_R_L", "", + "AMC_CPU_EAMPG_R", "", + "", "", "", "", + + /* O0-O7 line 224-239 */ + "HPM_PWR_FAIL", "Port80_b0", + "FM_DIMM_IP_FAIL", "Port80_b1", + "FM_DIMM_AH_FAIL", "Port80_b2", + "AMC_THERMTRIP_ASSERT", "Port80_b3", + "CPU_THERMTRIP_ASSERT", "Port80_b4", + "PVDDCR_SOC_P0_OCP_L", "Port80_b5", + "CPLD_SGPIO_RDY", "Port80_b6", + "", "Port80_b7", + + /* P0-P7 line 240-255 */ + "CPU0_SLP_S5_N_R", "NFC_VEN", + "CPU0_SLP_S3_N_R", "", + "FM_CPU0_PWRGD", "", + "PWRGD_RMC", "", + "FM_RST_CPU0_RESET_N", "", + "FM_PWRGD_CPU0_PWROK", "", + "wS5_PWR_Ready", "", + "wS0_ON_N", "PWRGD_P1V0_AUX"; + + ngpios =3D <128>; + + status =3D "okay"; +}; + +// BIOS Flash +&spi2 { + pinctrl-0 =3D <&pinctrl_spi2_default>; + + pinctrl-names =3D "default"; + + status =3D "okay"; + + flash@0 { + compatible =3D "jedec,spi-nor"; + label =3D "pnor"; + spi-max-frequency =3D <12000000>; + spi-rx-bus-width =3D <2>; + spi-tx-bus-width =3D <2>; + + status =3D "okay"; + }; +}; + +// HOST BIOS Debug +&uart1 { + status =3D "okay"; +}; + +&uart3 { + status =3D "okay"; +}; + +&uart4 { + status =3D "okay"; +}; + +// BMC Debug Console +&uart5 { + status =3D "okay"; +}; + +&uart_routing { + status =3D "okay"; +}; + +&uhci { + status =3D "okay"; +}; + +&vhub { + status =3D "okay"; +}; + +&video { + memory-region =3D <&video_engine_memory>; + + status =3D "okay"; +}; + +&wdt1 { + pinctrl-0 =3D <&pinctrl_wdtrst1_default>; + pinctrl-names =3D "default"; + aspeed,ext-active-high; + aspeed,ext-pulse-duration =3D <256>; + aspeed,ext-push-pull; + aspeed,external-signal; + aspeed,reset-type =3D "soc"; + + status =3D "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arc= h/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts index 1fddf3a5d138..3ae84e25dcb8 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts @@ -1,1079 +1,3 @@ // SPDX-License-Identifier: GPL-2.0-or-later =20 -/dts-v1/; -#include "aspeed-g6.dtsi" -#include -#include - -/ { - model =3D "Facebook Anacapa BMC"; - compatible =3D "facebook,anacapa-bmc", "aspeed,ast2600"; - - aliases { - serial0 =3D &uart1; - serial1 =3D &uart2; - serial2 =3D &uart3; - serial3 =3D &uart4; - serial4 =3D &uart5; - i2c16 =3D &i2c0mux0ch0; - i2c17 =3D &i2c0mux0ch1; - i2c18 =3D &i2c0mux0ch2; - i2c19 =3D &i2c0mux0ch3; - i2c20 =3D &i2c1mux0ch0; - i2c21 =3D &i2c1mux0ch1; - i2c22 =3D &i2c1mux0ch2; - i2c23 =3D &i2c1mux0ch3; - i2c24 =3D &i2c4mux0ch0; - i2c25 =3D &i2c4mux0ch1; - i2c26 =3D &i2c4mux0ch2; - i2c27 =3D &i2c4mux0ch3; - i2c28 =3D &i2c4mux0ch4; - i2c29 =3D &i2c4mux0ch5; - i2c30 =3D &i2c4mux0ch6; - i2c31 =3D &i2c4mux0ch7; - i2c32 =3D &i2c8mux0ch0; - i2c33 =3D &i2c8mux0ch1; - i2c34 =3D &i2c8mux0ch2; - i2c35 =3D &i2c8mux0ch3; - i2c36 =3D &i2c10mux0ch0; - i2c37 =3D &i2c10mux0ch1; - i2c38 =3D &i2c10mux0ch2; - i2c39 =3D &i2c10mux0ch3; - i2c40 =3D &i2c10mux0ch4; - i2c41 =3D &i2c10mux0ch5; - i2c42 =3D &i2c10mux0ch6; - i2c43 =3D &i2c10mux0ch7; - i2c44 =3D &i2c11mux0ch0; - i2c45 =3D &i2c11mux0ch1; - i2c46 =3D &i2c11mux0ch2; - i2c47 =3D &i2c11mux0ch3; - i2c48 =3D &i2c11mux0ch4; - i2c49 =3D &i2c11mux0ch5; - i2c50 =3D &i2c11mux0ch6; - i2c51 =3D &i2c11mux0ch7; - i2c52 =3D &i2c13mux0ch0; - i2c53 =3D &i2c13mux0ch1; - i2c54 =3D &i2c13mux0ch2; - i2c55 =3D &i2c13mux0ch3; - i2c56 =3D &i2c13mux0ch4; - i2c57 =3D &i2c13mux0ch5; - i2c58 =3D &i2c13mux0ch6; - i2c59 =3D &i2c13mux0ch7; - }; - - chosen { - stdout-path =3D "serial4:57600n8"; - }; - - iio-hwmon { - compatible =3D "iio-hwmon"; - io-channels =3D <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, - <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, - <&adc1 2>; - }; - - leds { - compatible =3D "gpio-leds"; - - led-0 { - label =3D "bmc_heartbeat_amber"; - gpios =3D <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; - linux,default-trigger =3D "heartbeat"; - }; - - led-1 { - label =3D "fp_id_amber"; - default-state =3D "off"; - gpios =3D <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>; - }; - }; - - memory@80000000 { - device_type =3D "memory"; - reg =3D <0x80000000 0x80000000>; - }; - - reserved-memory { - #address-cells =3D <1>; - #size-cells =3D <1>; - ranges; - - video_engine_memory: video { - size =3D <0x02c00000>; - alignment =3D <0x00100000>; - compatible =3D "shared-dma-pool"; - reusable; - }; - - gfx_memory: framebuffer { - size =3D <0x01000000>; - alignment =3D <0x01000000>; - compatible =3D "shared-dma-pool"; - reusable; - }; - }; - - p3v3_bmc_aux: regulator-p3v3-bmc-aux { - compatible =3D "regulator-fixed"; - regulator-name =3D "p3v3_bmc_aux"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - regulator-always-on; - }; - - spi_gpio: spi { - compatible =3D "spi-gpio"; - #address-cells =3D <1>; - #size-cells =3D <0>; - - sck-gpios =3D <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; - mosi-gpios =3D <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; - miso-gpios =3D <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; - cs-gpios =3D <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; - num-chipselects =3D <1>; - status =3D "okay"; - - tpm@0 { - compatible =3D "infineon,slb9670", "tcg,tpm_tis-spi"; - spi-max-frequency =3D <33000000>; - reg =3D <0>; - }; - }; -}; - -&adc0 { - aspeed,int-vref-microvolt =3D <2500000>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_adc0_default &pinctrl_adc1_default - &pinctrl_adc2_default &pinctrl_adc3_default - &pinctrl_adc4_default &pinctrl_adc5_default - &pinctrl_adc6_default &pinctrl_adc7_default>; - status =3D "okay"; -}; - -&adc1 { - aspeed,int-vref-microvolt =3D <2500000>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_adc10_default>; - status =3D "okay"; -}; - -&ehci1 { - status =3D "okay"; -}; - -&fmc { - status =3D "okay"; - - flash@0 { - status =3D "okay"; - m25p,fast-read; - label =3D "bmc"; - spi-max-frequency =3D <50000000>; -#include "openbmc-flash-layout-128.dtsi" - }; - - flash@1 { - status =3D "okay"; - m25p,fast-read; - label =3D "alt-bmc"; - spi-max-frequency =3D <50000000>; - }; -}; - -&gfx { - status =3D "okay"; - memory-region =3D <&gfx_memory>; -}; - -&gpio0 { - gpio-line-names =3D - - /*A0-A7*/ - "","","","","","","","", - - /*B0-B7*/ - "BATTERY_DETECT", "", "", "BMC_READY", - "", "FM_ID_LED", "", "", - - /*C0-C7*/ - "","","","","","","","", - - /*D0-D7*/ - "","","","","","","","", - - /*E0-E7*/ - "","","","","","","","", - - /*F0-F7*/ - "","","","","","","","", - - /*G0-G7*/ - "FM_MUX1_SEL", "", "", "", - "", "", "FM_DEBUG_PORT_PRSNT_N", "FM_BMC_DBP_PRESENT_N", - - /*H0-H7*/ - "","","","","","","","", - - /*I0-I7*/ - "", "", "", "", - "", "FLASH_WP_STATUS", "BMC_JTAG_MUX_SEL", "", - - /*J0-J7*/ - "","","","","","","","", - - /*K0-K7*/ - "","","","","","","","", - - /*L0-L7*/ - "","","","","","","","", - - /*M0-M7*/ - "", "BMC_FRU_WP", "", "", - "", "", "", "", - - /*N0-N7*/ - "LED_POSTCODE_0", "LED_POSTCODE_1", "LED_POSTCODE_2", "LED_POSTCODE_3", - "LED_POSTCODE_4", "LED_POSTCODE_5", "LED_POSTCODE_6", "LED_POSTCODE_7", - - /*O0-O7*/ - "","","","","","","","", - - /*P0-P7*/ - "PWR_BTN_BMC_BUF_N", "", "ID_RST_BTN_BMC_N", "", - "PWR_LED", "", "", "BMC_HEARTBEAT_N", - - /*Q0-Q7*/ - "","","","","","","","", - - /*R0-R7*/ - "","","","","","","","", - - /*S0-S7*/ - "", "", "SYS_BMC_PWRBTN_N", "", - "", "", "", "RUN_POWER_FAULT", - - /*T0-T7*/ - "","","","","","","","", - - /*U0-U7*/ - "","","","","","","","", - - /*V0-V7*/ - "","","","","","","","", - - /*W0-W7*/ - "","","","","","","","", - - /*X0-X7*/ - "","","","","","","","", - - /*Y0-Y7*/ - "","","","","","","","", - - /*Z0-Z7*/ - "SPI_BMC_TPM_CS2_N", "", "", "SPI_BMC_TPM_CLK", - "SPI_BMC_TPM_MOSI", "SPI_BMC_TPM_MISO", "", ""; -}; - -&gpio1 { - gpio-line-names =3D - /*18A0-18A7*/ - "","","","","","","","", - - /*18B0-18B7*/ - "","","","", - "FM_BOARD_BMC_REV_ID0", "FM_BOARD_BMC_REV_ID1", - "FM_BOARD_BMC_REV_ID2", "", - - /*18C0-18C7*/ - "","","","","","","","", - - /*18D0-18D7*/ - "","","","","","","","", - - /*18E0-18E3*/ - "FM_BMC_PROT_LS_EN", "AC_PWR_BMC_BTN_N", "", ""; -}; - -// L Bridge Board -&i2c0 { - status =3D "okay"; - - eeprom@50 { - compatible =3D "atmel,24c2048"; - reg =3D <0x50>; - pagesize =3D <128>; - }; - - i2c-mux@70 { - compatible =3D "nxp,pca9546"; - reg =3D <0x70>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c0mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c0mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c0mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c0mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - }; -}; - -// R Bridge Board -&i2c1 { - status =3D "okay"; - - eeprom@50 { - compatible =3D "atmel,24c2048"; - reg =3D <0x50>; - pagesize =3D <128>; - }; - - i2c-mux@70 { - compatible =3D "nxp,pca9546"; - reg =3D <0x70>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c1mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c1mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c1mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c1mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - }; -}; - -// MB - E1.S -&i2c4 { - status =3D "okay"; - - i2c-mux@70 { - compatible =3D "nxp,pca9548"; - reg =3D <0x70>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c4mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch4: i2c@4 { - reg =3D <4>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch5: i2c@5 { - reg =3D <5>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch6: i2c@6 { - reg =3D <6>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch7: i2c@7 { - reg =3D <7>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - }; -}; - -// AMC -&i2c5 { - status =3D "okay"; -}; - -// MB -&i2c6 { - status =3D "okay"; - - // HPM FRU - eeprom@50 { - compatible =3D "atmel,24c256"; - reg =3D <0x50>; - }; -}; - -// SCM -&i2c7 { - status =3D "okay"; - - -}; - -// MB - PDB -&i2c8 { - status =3D "okay"; - - i2c-mux@72 { - compatible =3D "nxp,pca9546"; - reg =3D <0x72>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c8mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - adc@1f { - compatible =3D "ti,adc128d818"; - reg =3D <0x1f>; - ti,mode =3D /bits/ 8 <1>; - }; - - gpio@22 { - compatible =3D "nxp,pca9555"; - reg =3D <0x22>; - gpio-controller; - #gpio-cells =3D <2>; - - interrupt-parent =3D <&sgpiom0>; - interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; - - gpio-line-names =3D - "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TEMP75_U8_ALERT_R_N", - "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP", - "RPDB_FAN_CT_FAN_FAIL_R_N", "", - "", "", - "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N", - "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N", - "RPDB_I2C_P12V_MB_VRM_ALERT_R_N", - "RPDB_I2C_P12V_STBY_VRM_ALERT_R_N", - "RPDB_PGD_P3V3_STBY_PWRGD_R", - "RPDB_P12V_STBY_VRM_PWRGD_BUF_R"; - }; - - gpio@24 { - compatible =3D "nxp,pca9555"; - reg =3D <0x24>; - gpio-controller; - #gpio-cells =3D <2>; - - interrupt-parent =3D <&sgpiom0>; - interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; - - gpio-line-names =3D - "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", - "RPDB_PWRGD_P50V_HSC4_SYS_R", - "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", - "RPDB_P50V_FAN1_R2_PG", "RPDB_P50V_FAN2_R2_PG", - "RPDB_P50V_FAN3_R2_PG", "RPDB_P50V_FAN4_R2_PG", - "", "RPDB_FAN1_PRSNT_N_R", - "", "RPDB_FAN2_PRSNT_N_R", - "RPDB_FAN3_PRSNT_N_R", "RPDB_FAN4_PRSNT_N_R", - "", ""; - }; - - // R-PDB FRU - eeprom@50 { - compatible =3D "atmel,24c128"; - reg =3D <0x50>; - }; - }; - i2c8mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - gpio@22 { - compatible =3D "nxp,pca9555"; - reg =3D <0x22>; - gpio-controller; - #gpio-cells =3D <2>; - - interrupt-parent =3D <&sgpiom0>; - interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; - - gpio-line-names =3D - "LPDB_FAN_FULL_SPEED_R_N","LPDB_I2C_TEMP75_U8_ALERT_R_N", - "LPDB_I2C_TMP432_U29_ALERT_R_N","LPDB_GLOBAL_WP", - "LPDB_FAN_CT_FAN_FAIL_R_N","", - "","", - "LPDB_ALERT_P50V_HSC0_R_N","LPDB_ALERT_P50V_HSC1_R_N", - "LPDB_ALERT_P50V_HSC5_R_N","LPDB_I2C_P12V_SW_VRM_ALERT_R_N", - "LPDB_EAM0_PRSNT_MOS_N_R","LPDB_EAM1_PRSNT_MOS_N_R", - "LPDB_PWRGD_P50V_HSC5_SYS_R",""; - }; - - gpio@24 { - compatible =3D "nxp,pca9555"; - reg =3D <0x24>; - gpio-controller; - #gpio-cells =3D <2>; - - interrupt-parent =3D <&sgpiom0>; - interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; - - gpio-line-names =3D - "LPDB_P50V_FAN1_R2_PG","LPDB_P50V_FAN2_R2_PG", - "LPDB_P50V_FAN3_R2_PG","LPDB_P50V_FAN4_R2_PG", - "LPDB_P50V_FAN5_R2_PG","LPDB_FAN1_PRSNT_N_R", - "LPDB_FAN2_PRSNT_N_R","LPDB_FAN3_PRSNT_N_R", - "LPDB_FAN4_PRSNT_N_R","LPDB_FAN5_PRSNT_N_R", - "","", - "","", - "",""; - }; - - // L-PDB FRU - eeprom@50 { - compatible =3D "atmel,24c128"; - reg =3D <0x50>; - }; - }; - i2c8mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c8mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - }; -}; - -// SCM -&i2c9 { - status =3D "okay"; - - // SCM FRU - eeprom@50 { - compatible =3D "atmel,24c128"; - reg =3D <0x50>; - }; - - // BSM FRU - eeprom@56 { - compatible =3D "atmel,24c64"; - reg =3D <0x56>; - }; -}; - -// R Bridge Board -&i2c10 { - status =3D "okay"; - - i2c-mux@71 { - compatible =3D "nxp,pca9548"; - reg =3D <0x71>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c10mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c10mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c10mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c10mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c10mux0ch4: i2c@4 { - reg =3D <4>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c10mux0ch5: i2c@5 { - reg =3D <5>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - gpio@22 { - compatible =3D "nxp,pca9555"; - reg =3D <0x22>; - gpio-controller; - #gpio-cells =3D <2>; - - gpio-line-names =3D - "","", - "","RBB_CPLD_REFRESH_IN_PRGRS_R_L", - "RBB_EAM0_NIC_CBL_PRSNT_R_L","RBB_EAM1_NIC_CBL_PRSNT_R_L", - "RBB_AINIC_JTAG_MUX_R2_SEL","RBB_SPI_MUX0_R2_SEL", - "RBB_AINIC_PRSNT_R_L","RBB_AINIC_OE_R_N", - "RBB_AINIC_BOARD_R2_ID","RBB_RST_USB2_HUB_R_N", - "RBB_RST_FT4222_R_N","RBB_RST_MCP2210_R_N", - "",""; - }; - - // R Bridge Board FRU - eeprom@52 { - compatible =3D "atmel,24c256"; - reg =3D <0x52>; - }; - }; - i2c10mux0ch6: i2c@6 { - reg =3D <6>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c10mux0ch7: i2c@7 { - reg =3D <7>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - }; -}; - -// L Bridge Board -&i2c11 { - status =3D "okay"; - - i2c-mux@71 { - compatible =3D "nxp,pca9548"; - reg =3D <0x71>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c11mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c11mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c11mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c11mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c11mux0ch4: i2c@4 { - reg =3D <4>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c11mux0ch5: i2c@5 { - reg =3D <5>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - gpio@22 { - compatible =3D "nxp,pca9555"; - reg =3D <0x22>; - gpio-controller; - #gpio-cells =3D <2>; - - gpio-line-names =3D - "","", - "","LBB_CPLD_REFRESH_IN_PRGRS_R_L", - "LBB_EAM0_NIC_CBL_PRSNT_R_L","LBB_EAM1_NIC_CBL_PRSNT_R_L", - "LBB_AINIC_JTAG_MUX_R2_SEL","LBB_SPI_MUX0_R2_SEL", - "LBB_AINIC_PRSNT_R_L","LBB_AINIC_OE_R_N", - "LBB_AINIC_BOARD_R2_ID","LBB_RST_USB2_HUB_R_N", - "LBB_RST_FT4222_R_N","LBB_RST_MCP2210_R_N", - "",""; - }; - - // L Bridge Board FRU - eeprom@52 { - compatible =3D "atmel,24c256"; - reg =3D <0x52>; - }; - }; - i2c11mux0ch6: i2c@6 { - reg =3D <6>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c11mux0ch7: i2c@7 { - reg =3D <7>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - }; -}; - -// Debug Card -&i2c12 { - status =3D "okay"; -}; - -// MB -&i2c13 { - status =3D "okay"; - - i2c-mux@70 { - compatible =3D "nxp,pca9548"; - reg =3D <0x70>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c13mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c13mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c13mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c13mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - adc@1f { - compatible =3D "ti,adc128d818"; - reg =3D <0x1f>; - ti,mode =3D /bits/ 8 <1>; - }; - }; - i2c13mux0ch4: i2c@4 { - reg =3D <4>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - // HPM BRD ID FRU - eeprom@51 { - compatible =3D "atmel,24c256"; - reg =3D <0x51>; - }; - }; - i2c13mux0ch5: i2c@5 { - reg =3D <5>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c13mux0ch6: i2c@6 { - reg =3D <6>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c13mux0ch7: i2c@7 { - reg =3D <7>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - nfc@28 { - compatible =3D "nxp,nxp-nci-i2c"; - reg =3D <0x28>; - - interrupt-parent =3D <&sgpiom0>; - interrupts =3D <156 IRQ_TYPE_LEVEL_HIGH>; - - enable-gpios =3D <&sgpiom0 241 GPIO_ACTIVE_HIGH>; - }; - }; - }; -}; - -// SCM -&i2c14 { - status =3D "okay"; -}; - -&i2c15 { - status =3D "okay"; -}; - -&kcs2 { - aspeed,lpc-io-reg =3D <0xca8>; - status =3D "okay"; -}; - -&kcs3 { - aspeed,lpc-io-reg =3D <0xca2>; - status =3D "okay"; -}; - -&lpc_ctrl { - status =3D "okay"; -}; - -&mac2 { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_ncsi3_default>; - use-ncsi; -}; - -&sgpiom0 { - ngpios =3D <128>; - bus-frequency =3D <2000000>; - gpio-line-names =3D - /*in - out - in - out */ - /* A0-A7 line 0-15 */ - "", "FM_CPU0_SYS_RESET_N", "", "CPU0_KBRST_N", - "", "FM_CPU0_PROCHOT_trigger_N", "", "FM_CLR_CMOS_R_P0", - "", "Force_I3C_SEL", "", "SYSTEM_Force_Run_AC_Cycle", - "", "", "", "", - - /* B0-B7 line 16-31 */ - "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", - "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", - "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", - "Channel3_leakage", "FM_CPU0_NMI_SYNC_FLOOD_N", - "Channel4_leakage_Manifold2", "", - "Channel5_leakage_EAM1", "", - "Channel6_leakage_CPU_DIMM", "", - "Channel7_leakage_EAM2", "", - - /* C0-C7 line 32-47 */ - "RSVD_RMC_GPIO3", "", "", "", - "", "", "", "", - "LEAK_DETECT_RMC_N", "JTAG_CPLD_TRST_R_N", "", "", - "", "", "", "", - - /* D0-D7 line 48-63 */ - "PWRGD_PDB_EAMHSC0_CPLD_PG_R", "", - "PWRGD_PDB_EAMHSC1_CPLD_PG_R", "", - "PWRGD_PDB_EAMHSC2_CPLD_PG_R", "", - "PWRGD_PDB_EAMHSC3_CPLD_PG_R", "", - "AMC_BRD_PRSNT_CPLD_L", "", "", "", - "", "", "", "", - - /* E0-E7 line 64-79 */ - "AMC_PDB_EAMHSC0_CPLD_EN_R", "", - "AMC_PDB_EAMHSC1_CPLD_EN_R", "", - "AMC_PDB_EAMHSC2_CPLD_EN_R", "", - "AMC_PDB_EAMHSC3_CPLD_EN_R", "", - "", "", "", "", - "", "", "", "", - - /* F0-F7 line 80-95 */ - "PWRGD_PVDDCR_CPU1_P0", "SGPIO_READY", - "PWRGD_PVDDCR_CPU0_P0", "", - "", "", "", "", - "", "", "", "", - - /* G0-G7 line 96-111 */ - "L_PRSNT_EDSFF0_N", "", - "L_PRSNT_EDSFF1_N", "", - "R_PRSNT_EDSFF2_N", "", - "R_PRSNT_EDSFF3_N", "", - "HPM_EDSFF_PG", "", - "PWRGD_CHEH_CPU0_FPGA", "", - "PWRGD_CHAD_CPU0_FPGA", "FM_BMC_READY_PLD", - "", "", - - /* H0-H7 line 112-127 */ - "PWRGD_P3V3", "", - "P12V_DDR_IP_PWRGD_R", "", - "P12V_DDR_AH_PWRGD_R", "", - "PWRGD_P12V_VRM1_CPLD_PG_R", "", - "PWRGD_P12V_VRM0_CPLD_PG_R", "", - "PWRGD_PDB_HSC4_CPLD_PG_R", "", - "PWRGD_PVDD18_S5_P0_PG", "", - "PWRGD_PVDD33_S5_P0_PG", "", - - /* I0-I7 line 128-143 */ - "EAM0_BRD_PRSNT_R_L", "", - "EAM1_BRD_PRSNT_R_L", "", - "EAM2_BRD_PRSNT_R_L", "", - "EAM3_BRD_PRSNT_R_L", "", - "EAM0_CPU_MOD_PWR_GD_R", "", - "EAM1_CPU_MOD_PWR_GD_R", "", - "PRSNT_EDSFF_BOOT_N", "", - "EAM3_CPU_MOD_PWR_GD_R", "", - - /* J0-J7 line 144-159 */ - "PRSNT_L_BIRDGE_R", "", - "PRSNT_R_BIRDGE_R", "", - "BRIDGE_L_MAIN_PG_R", "", - "BRIDGE_R_MAIN_PG_R", "", - "BRIDGE_L_STBY_PG_R", "", - "BRIDGE_R_STBY_PG_R", "", - "", "", "", "", - - /* K0-K7 line 160-175 */ - "ADC_I2C_ALERT_N", "", - "TEMP_I2C_ALERT_R_L", "", - "CPU0_VR_SMB_ALERT_CPLD_N", "", - "COVER_INTRUDER_R_N", "", - "HANDLE_INTRUDER_CPLD_N", "", - "IRQ_MCIO_CPLD_WAKE_R_N", "", - "APML_CPU0_ALERT_R_N", "", - "PDB_ALERT_R_N", "", - - /* L0-L7 line 176-191 */ - "L_EDSFF0_PG", "", "L_EDSFF1_PG", "", - "R_EDSFF2_PG", "", "R_EDSFF3_PG", "", - "CPU0_CORETYPE0", "", "CPU0_CORETYPE1", "", - "CPU0_CORETYPE2", "", "FM_BIOS_POST_CMPLT_R_N", "", - - /* M0-M7 line 192-207 */ - "EAM0_SMERR_CPLD_R_L", "", - "EAM1_SMERR_CPLD_R_L", "", - "EAM2_SMERR_CPLD_R_L", "", - "EAM3_SMERR_CPLD_R_L", "", - "CPU0_SMERR_N_R", "", - "CPU0_NV_SAVE_N_R", "", - "PDB_PWR_LOSS_CPLD_N", "", - "IRQ_BMC_SMI_ACTIVE_R_N", "", - - /* N0-N7 line 208-223 */ - "AMCROT_BMC_S5_RDY_R", "", - "AMC_RDY_R", "", - "AMC_STBY_PGOOD_R", "", - "CPU_AMC_SLP_S5_R_L", "", - "AMC_CPU_EAMPG_R", "", - "", "", "", "", - - /* O0-O7 line 224-239 */ - "HPM_PWR_FAIL", "Port80_b0", - "FM_DIMM_IP_FAIL", "Port80_b1", - "FM_DIMM_AH_FAIL", "Port80_b2", - "AMC_THERMTRIP_ASSERT", "Port80_b3", - "CPU_THERMTRIP_ASSERT", "Port80_b4", - "PVDDCR_SOC_P0_OCP_L", "Port80_b5", - "CPLD_SGPIO_RDY", "Port80_b6", - "", "Port80_b7", - - /* P0-P7 line 240-255 */ - "CPU0_SLP_S5_N_R", "NFC_VEN", - "CPU0_SLP_S3_N_R", "", - "FM_CPU0_PWRGD", "", - "PWRGD_RMC", "", - "FM_RST_CPU0_RESET_N", "", - "FM_PWRGD_CPU0_PWROK", "", - "wS5_PWR_Ready", "", - "wS0_ON_N", "PWRGD_P1V0_AUX"; - status =3D "okay"; -}; - -// BIOS Flash -&spi2 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_spi2_default>; - status =3D "okay"; - reg =3D <0x1e631000 0xc4>, <0x50000000 0x8000000>; - - flash@0 { - compatible =3D "jedec,spi-nor"; - label =3D "pnor"; - spi-max-frequency =3D <12000000>; - spi-tx-bus-width =3D <2>; - spi-rx-bus-width =3D <2>; - status =3D "okay"; - }; -}; - -// HOST BIOS Debug -&uart1 { - status =3D "okay"; -}; - -&uart3 { - status =3D "okay"; -}; - -&uart4 { - status =3D "okay"; -}; - -// BMC Debug Console -&uart5 { - status =3D "okay"; -}; - -&uart_routing { - status =3D "okay"; -}; - -&uhci { - status =3D "okay"; -}; - -&vhub { - status =3D "okay"; - pinctrl-names =3D "default"; -}; - -&video { - status =3D "okay"; - memory-region =3D <&video_engine_memory>; -}; - -&wdt1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_wdtrst1_default>; - aspeed,reset-type =3D "soc"; - aspeed,external-signal; - aspeed,ext-push-pull; - aspeed,ext-active-high; - aspeed,ext-pulse-duration =3D <256>; - status =3D "okay"; -}; +#include "aspeed-bmc-facebook-anacapa-evt1.dts" --=20 2.34.1 From nobody Mon Sep 28 06:37:49 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A7843EE1E9; Tue, 25 Aug 2026 10:48:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787654920; cv=none; b=ZXrwMzKU6RemHab3Md5tr8ET4kL6++sCicuf0bI9nxLWEUkJ/6nQuReO/MGw3pYyql0XaSFKormBLzO5hJgq4TUNhRrY2OBsP/8eSmRzTG0tmsMaqjsWfkjIwDcPeHwDp+P4Bo6f0tlsHnk1ajYRUfDJGzebFP6mPrfTDn6U5VM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787654920; c=relaxed/simple; bh=jVWDKkhv4pTdJ5+vRgBLamJB4IUxDZR/IAZBjuxaidM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Tue, 25 Aug 2026 10:48:40 +0000 (UTC) From: Colin Huang via B4 Relay Date: Tue, 25 Aug 2026 18:47:44 +0800 Subject: [PATCH v6 03/12] ARM: dts: aspeed: anacapa: Add EVT2 devicetree inheriting EVT1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260825-anacapa-devlop-phase-devicetree-v6-3-9059a2a279ce@gmail.com> References: <20260825-anacapa-devlop-phase-devicetree-v6-0-9059a2a279ce@gmail.com> In-Reply-To: <20260825-anacapa-devlop-phase-devicetree-v6-0-9059a2a279ce@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787654905; l=5861; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=TtwkAED6cW6HzsbJFREDSWJqsSTrllN1N+rcKtguFks=; b=Ojh7Q4C6PBH8GUAliVgFpAcL8G5xjjUwoffQ8B2zn0nAM7OLyv+t1NnLOvtEyhczxVMvgQ7Tu 8sbgNJfimAUBYFcZjl7NqSZGKQBRjfZ4Bbux/RwvsDIvfKivV4k9EKM X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Colin Huang Add a development-phase devicetree for the Facebook Anacapa BMC EVT2 hardware revision and update the Anacapa wrapper DTS to reference it. Signed-off-by: Colin Huang --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 178 +++++++++++++++++= ++++ .../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 2 +- 2 files changed, 179 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts new file mode 100644 index 000000000000..075ac39f369f --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/dts-v1/; +#include "aspeed-bmc-facebook-anacapa-evt1.dts" + +/ { + compatible =3D "facebook,anacapa-bmc-evt2", "aspeed,ast2600"; + model =3D "Facebook Anacapa BMC"; +}; + +&sgpiom0 { + bus-frequency =3D <2000000>; + gpio-line-names =3D + /*in - out */ + /* A0-A7 line 0-15 */ + "L_FNIC_FLT", "FM_CPU0_SYS_RESET_N", + "L_BNIC0_FLT", "CPU0_KBRST_N", + "L_BNIC1_FLT", "FM_CPU0_PROCHOT_trigger_N", + "L_BNIC2_FLT", "FM_CLR_CMOS_R_P0", + "L_BNIC3_FLT", "Force_I3C_SEL", + "L_RTM_SW_FLT", "SYSTEM_Force_Run_AC_Cycle", + "", "", + "", "", + + /* B0-B7 line 16-31 */ + "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", + "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", + "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", + "Channel5_leakage_present_EAM1", "FM_CPU0_NMI_SYNC_FLOOD_N", + "Channel4_leakage_Manifold2", "BMC_AINIC0_WP_R2_L", + "Channel5_leakage_EAM1", "BMC_AINIC1_WP_R2_L", + "Channel6_leakage_CPU_DIMM", "CPLD_BUF_R_AGPIO330", + "Channel7_leakage_EAM2", "CPLD_BUF_R_AGPIO331", + + /* C0-C7 line 32-47 */ + "RSVD_RMC_GPIO3", "RTM_MUX_L", + "LEAK_DETECT_RMC_N", "RTM_MUX_R", + "HDR_P0_NMI_BTN_BUF_R_N", "FPGA_JTAG_SCM_DBREQ_N", + "Channel6_leakage_present_CPU_DIMM", "whdt_sel", + "", "JTAG_CPLD_TRST_R_N", + "", "", + "", "", + "", "", + + /* D0-D7 line 48-63 */ + "Channel0_leakage_present_EAM3", "", + "Channel1_leakage_present_EAM0", "", + "Channel2_leakage_present_Manifold1", "", + "Channel4_leakage_present_Manifold2", "", + "AMC_BRD_PRSNT_CPLD_L", "", + "Channel7_leakage_present_EAM2", "", + "", "", + "", "", + + /* E0-E7 line 64-79 */ + "L_PRSNT_B_FENIC_R2_N", "", + "L_PRSNT_B_BENIC0_R2_N", "", + "L_PRSNT_B_BENIC1_R2_N", "", + "L_PRSNT_B_BENIC2_R2_N", "", + "L_PRSNT_B_BENIC3_R2_N", "", + "", "", + "", "", + "", "", + + /* F0-F7 line 80-95 */ + "R_PRSNT_B_FENIC_R2_N", "SGPIO_READY", + "R_PRSNT_B_BENIC0_R2_N", "", + "R_PRSNT_B_BENIC1_R2_N", "", + "R_PRSNT_B_BENIC2_R2_N", "", + "R_PRSNT_B_BENIC3_R2_N", "", + "", "", + "", "", + "", "", + + /* G0-G7 line 96-111 */ + "L_PRSNT_EDSFF0_N", "", + "L_PRSNT_EDSFF1_N", "", + "R_PRSNT_EDSFF2_N", "", + "R_PRSNT_EDSFF3_N", "", + "HPM_EDSFF_PG", "", + "", "", + "", "FM_BMC_READY_PLD", + "PRSNT_NFC_BOARD_R", "", + + /* H0-H7 line 112-127 */ + "R_FNIC_FLT", "", + "R_BNIC0_FLT", "", + "R_BNIC1_FLT", "", + "R_BNIC2_FLT", "", + "R_BNIC3_FLT", "", + "R_RTM_SW_FLT", "", + "", "", + "", "", + + /* I0-I7 line 128-143 */ + "EAM0_BRD_PRSNT_R_L", "", + "EAM1_BRD_PRSNT_R_L", "", + "EAM2_BRD_PRSNT_R_L", "", + "EAM3_BRD_PRSNT_R_L", "", + "FM_TPM_PRSNT_R_N", "", + "PDB_L_PRSNT_R_N", "", + "PRSNT_EDSFF_BOOT_N", "", + "PRSNT_CPU0_N", "", + + /* J0-J7 line 144-159 */ + "PRSNT_L_BRIDGE_R", "", + "PRSNT_R_BRIDGE_R", "", + "BRIDGE_L_MAIN_PG_R", "", + "BRIDGE_R_MAIN_PG_R", "", + "BRIDGE_L_STBY_PG_R", "", + "BRIDGE_R_STBY_PG_R", "", + "IRQ_NFC_BOARD_R", "", + "RSMRST_N", "", + + /* K0-K7 line 160-175 */ + "ADC_I2C_ALERT_N", "", + "TEMP_I2C_ALERT_R_L", "", + "CPU0_VR_SMB_ALERT_CPLD_N", "", + "COVER_INTRUDER_R_N", "", + "HANDLE_INTRUDER_CPLD_N", "", + "IRQ_MCIO_CPLD_WAKE_R_N", "", + "APML_CPU0_ALERT_R_N", "", + "PDB_ALERT_R_N", "", + + /* L0-L7 line 176-191 */ + "L_EDSFF0_PG", "", + "L_EDSFF1_PG", "", + "R_EDSFF2_PG", "", + "R_EDSFF3_PG", "", + "HPM_CPLD_HEART_BIT", "", + "RBB_CPLD_HEART_BIT", "", + "LBB_CPLD_HEART_BIT", "", + "FM_BIOS_POST_CMPLT_R_N", "", + + /* M0-M7 line 192-207 */ + "EAM0_SMERR_CPLD_R_L", "", + "EAM1_SMERR_CPLD_R_L", "", + "EAM2_SMERR_CPLD_R_L", "", + "EAM3_SMERR_CPLD_R_L", "", + "CPU0_SMERR_N_R", "", + "CPU0_NV_SAVE_N_R", "", + "PDB_PWR_LOSS_CPLD_N", "", + "IRQ_BMC_SMI_ACTIVE_R_N", "", + + /* N0-N7 line 208-223 */ + "AMCROT_BMC_S5_RDY_R", "", + "AMC_RDY_R", "", + "AMC_STBY_PGOOD_R", "", + "CPU_AMC_SLP_S5_R_L", "", + "AMC_CPU_EAMPG_R", "", + "DIMM_PMIC_PG_TIMEOUT", "", + "EAM_MOD_PWR_GD_TIMEOUT", "", + "CPLD_AMC_STBY_PWR_EN", "", + + /* O0-O7 line 224-239 */ + "HPM_PWR_FAIL", "Port80_b0", + "FM_DIMM_IP_FAIL", "Port80_b1", + "FM_DIMM_AH_FAIL", "Port80_b2", + "AMC_THERMTRIP_ASSERT", "Port80_b3", + "CPU_THERMTRIP_ASSERT", "Port80_b4", + "PVDDCR_SOC_P0_OCP_L", "Port80_b5", + "CPLD_SGPIO_RDY", "Port80_b6", + "FM_MAIN_PWREN_RMC_EN_ISO", "Port80_b7", + + /* P0-P7 line 240-255 */ + "CPU0_SLP_S5_N_R", "NFC_VEN", + "CPU0_SLP_S3_N_R", "", + "FM_CPU0_PWRGD", "", + "PWRGD_RMC", "", + "FM_RST_CPU0_RESET_N", "RBB_CPLD_RISCV_RST", + "FM_PWRGD_CPU0_PWROK", "LBB_CPLD_RISCV_RST", + "AMC_FAIL", "HPM_CPLD_RISCV_RST", + "S0_ON", ""; + + ngpios =3D <128>; + + status =3D "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arc= h/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts index 3ae84e25dcb8..8244d7a8a7da 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts @@ -1,3 +1,3 @@ // SPDX-License-Identifier: GPL-2.0-or-later =20 -#include "aspeed-bmc-facebook-anacapa-evt1.dts" +#include "aspeed-bmc-facebook-anacapa-evt2.dts" --=20 2.34.1 From nobody Mon Sep 28 06:37:49 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 731543DE44B; Tue, 25 Aug 2026 10:48:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260825-anacapa-devlop-phase-devicetree-v6-4-9059a2a279ce@gmail.com> References: <20260825-anacapa-devlop-phase-devicetree-v6-0-9059a2a279ce@gmail.com> In-Reply-To: <20260825-anacapa-devlop-phase-devicetree-v6-0-9059a2a279ce@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787654905; l=6001; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=sf2LPXmq2StZDZDl220rI/hWBYWTUa9p8+CGSr6d0C0=; b=bxGIAkCB8Q1k0n0s0hnS39sS5Vt11IHH83u0jam7ykLYmuQX4cqLad5yHPKgyMyOng1Yf3bGg gcyQiN67VsUA6JUXQJZ4xEEr4/EcEnHOUyUuP6arUsuXg4jfoieYBIn X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Colin Huang Add a development-phase devicetree for the Facebook Anacapa BMC DVT hardware revision and update the Anacapa wrapper DTS to reference it. Signed-off-by: Colin Huang --- .../dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts | 178 +++++++++++++++++= ++++ .../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 2 +- 2 files changed, 179 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts b= /arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts new file mode 100644 index 000000000000..975d603ca540 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/dts-v1/; +#include "aspeed-bmc-facebook-anacapa-evt2.dts" + +/ { + compatible =3D "facebook,anacapa-bmc-dvt", "aspeed,ast2600"; + model =3D "Facebook Anacapa BMC"; +}; + +&sgpiom0 { + bus-frequency =3D <2000000>; + gpio-line-names =3D + /*in - out */ + /* A0-A7 line 0-15 */ + "L_FNIC_FLT", "FM_CPU0_SYS_RESET_N", + "L_BNIC0_FLT", "CPU0_KBRST_N", + "L_BNIC1_FLT", "FM_CPU0_PROCHOT_trigger_N", + "L_BNIC2_FLT", "FM_CLR_CMOS_R_P0", + "L_BNIC3_FLT", "Force_I3C_SEL", + "L_RTM_SW_FLT", "SYSTEM_Force_Run_AC_Cycle", + "", "", + "", "", + + /* B0-B7 line 16-31 */ + "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", + "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", + "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", + "Channel5_leakage_present_EAM1", "FM_CPU0_NMI_SYNC_FLOOD_N", + "Channel4_leakage_Manifold2", "BMC_AINIC0_WP_R2_L", + "Channel5_leakage_EAM1", "BMC_AINIC1_WP_R2_L", + "Channel6_leakage_CPU_DIMM", "CPLD_BUF_R_AGPIO330", + "Channel7_leakage_EAM2", "CPLD_BUF_R_AGPIO331", + + /* C0-C7 line 32-47 */ + "RSVD_RMC_GPIO3", "RTM_MUX_L", + "LEAK_DETECT_RMC_N", "RTM_MUX_R", + "HDR_P0_NMI_BTN_BUF_R_N", "FPGA_JTAG_SCM_DBREQ_N", + "Channel6_leakage_present_CPU_DIMM", "whdt_sel", + "R_EAM0_NIC_CBL_PRSNT_L", "JTAG_CPLD_TRST_R_N", + "R_EAM1_NIC_CBL_PRSNT_L", "", + "L_EAM0_NIC_CBL_PRSNT_L", "", + "L_EAM1_NIC_CBL_PRSNT_L", "", + + /* D0-D7 line 48-63 */ + "Channel0_leakage_present_EAM3", "", + "Channel1_leakage_present_EAM0", "", + "Channel2_leakage_present_Manifold1", "", + "Channel4_leakage_present_Manifold2", "", + "AMC_BRD_PRSNT_CPLD_L", "", + "Channel7_leakage_present_EAM2", "", + "", "", + "", "", + + /* E0-E7 line 64-79 */ + "L_PRSNT_B_FENIC_R2_N", "", + "L_PRSNT_B_BENIC0_R2_N", "", + "L_PRSNT_B_BENIC1_R2_N", "", + "L_PRSNT_B_BENIC2_R2_N", "", + "L_PRSNT_B_BENIC3_R2_N", "", + "", "", + "", "", + "", "", + + /* F0-F7 line 80-95 */ + "R_PRSNT_B_FENIC_R2_N", "SGPIO_READY", + "R_PRSNT_B_BENIC0_R2_N", "", + "R_PRSNT_B_BENIC1_R2_N", "", + "R_PRSNT_B_BENIC2_R2_N", "", + "R_PRSNT_B_BENIC3_R2_N", "", + "", "", + "", "", + "", "", + + /* G0-G7 line 96-111 */ + "L_PRSNT_EDSFF0_N", "", + "L_PRSNT_EDSFF1_N", "", + "R_PRSNT_EDSFF2_N", "", + "R_PRSNT_EDSFF3_N", "", + "HPM_EDSFF_PG", "", + "", "", + "P12V_PWR_CABLE_PRSNT_L_R", "FM_BMC_READY_PLD", + "PRSNT_NFC_BOARD_R", "", + + /* H0-H7 line 112-127 */ + "R_FNIC_FLT", "", + "R_BNIC0_FLT", "", + "R_BNIC1_FLT", "", + "R_BNIC2_FLT", "", + "R_BNIC3_FLT", "", + "R_RTM_SW_FLT", "", + "RBB_Cable_Present", "", + "LBB_Cable_Present", "", + + /* I0-I7 line 128-143 */ + "EAM0_BRD_PRSNT_R_L", "", + "EAM1_BRD_PRSNT_R_L", "", + "EAM2_BRD_PRSNT_R_L", "", + "EAM3_BRD_PRSNT_R_L", "", + "FM_TPM_PRSNT_R_N", "", + "PDB_L_PRSNT_R_N", "", + "PRSNT_EDSFF_BOOT_N", "", + "PRSNT_CPU0_N", "", + + /* J0-J7 line 144-159 */ + "PRSNT_L_BRIDGE_R", "", + "PRSNT_R_BRIDGE_R", "", + "BRIDGE_L_MAIN_PG_R", "", + "BRIDGE_R_MAIN_PG_R", "", + "BRIDGE_L_STBY_PG_R", "", + "BRIDGE_R_STBY_PG_R", "", + "IRQ_NFC_BOARD_R", "", + "RSMRST_N", "", + + /* K0-K7 line 160-175 */ + "ADC_I2C_ALERT_N", "", + "TEMP_I2C_ALERT_R_L", "", + "CPU0_VR_SMB_ALERT_CPLD_N", "", + "COVER_INTRUDER_R_N", "", + "HANDLE_INTRUDER_CPLD_N", "", + "IRQ_MCIO_CPLD_WAKE_R_N", "", + "APML_CPU0_ALERT_R_N", "", + "PDB_ALERT_R_N", "", + + /* L0-L7 line 176-191 */ + "L_EDSFF0_PG", "", + "L_EDSFF1_PG", "", + "R_EDSFF2_PG", "", + "R_EDSFF3_PG", "", + "HPM_CPLD_HEART_BIT", "", + "RBB_CPLD_HEART_BIT", "", + "LBB_CPLD_HEART_BIT", "", + "FM_BIOS_POST_CMPLT_R_N", "", + + /* M0-M7 line 192-207 */ + "EAM0_SMERR_CPLD_R_L", "", + "EAM1_SMERR_CPLD_R_L", "", + "EAM2_SMERR_CPLD_R_L", "", + "EAM3_SMERR_CPLD_R_L", "", + "CPU0_SMERR_N_R", "", + "CPU0_NV_SAVE_N_R", "", + "PDB_PWR_LOSS_CPLD_N", "", + "IRQ_BMC_SMI_ACTIVE_R_N", "", + + /* N0-N7 line 208-223 */ + "AMCROT_BMC_S5_RDY_R", "", + "AMC_RDY_R", "", + "AMC_STBY_PGOOD_R", "", + "CPU_AMC_SLP_S5_R_L", "", + "AMC_CPU_EAMPG_R", "", + "DIMM_PMIC_PG_TIMEOUT", "", + "EAM_MOD_PWR_GD_TIMEOUT", "", + "CPLD_AMC_STBY_PWR_EN", "", + + /* O0-O7 line 224-239 */ + "HPM_PWR_FAIL", "Port80_b0", + "FM_DIMM_IP_FAIL", "Port80_b1", + "FM_DIMM_AH_FAIL", "Port80_b2", + "AMC_THERMTRIP_ASSERT", "Port80_b3", + "CPU_THERMTRIP_ASSERT", "Port80_b4", + "PVDDCR_SOC_P0_OCP_L", "Port80_b5", + "CPLD_SGPIO_RDY", "Port80_b6", + "FM_MAIN_PWREN_RMC_EN_ISO", "Port80_b7", + + /* P0-P7 line 240-255 */ + "CPU0_SLP_S5_N_R", "NFC_VEN", + "CPU0_SLP_S3_N_R", "", + "FM_CPU0_PWRGD", "", + "PWRGD_RMC", "", + "FM_RST_CPU0_RESET_N", "RBB_CPLD_RISCV_RST", + "FM_PWRGD_CPU0_PWROK", "LBB_CPLD_RISCV_RST", + "AMC_FAIL", "HPM_CPLD_RISCV_RST", + "S0_ON", ""; + + ngpios =3D <128>; + + status =3D "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arc= h/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts index 8244d7a8a7da..a9512ea771e3 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts @@ -1,3 +1,3 @@ // SPDX-License-Identifier: GPL-2.0-or-later =20 -#include "aspeed-bmc-facebook-anacapa-evt2.dts" +#include "aspeed-bmc-facebook-anacapa-dvt.dts" --=20 2.34.1 From nobody Mon Sep 28 06:37:49 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B378B394461; Tue, 25 Aug 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Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="i9XvgZsO" Received: by smtp.kernel.org (Postfix) with ESMTPS id 535A9C2BD01; Tue, 25 Aug 2026 10:48:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787654920; bh=wAwBTsf3GkIlrHwbVtRdn+g/x5eJ9jnUFDqj54HbqqY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=i9XvgZsOzRwVgbl4s0RN+eeMo/VatgD1nDeMLWst42HtLlcmGa8Uuz1ZJhRRX3mIm uxV7jFR+cq9TAyFGi5kxtqWYo/dSMzRshcFonTQdy36PvG238uIZ6ZcC1CnL9OkdcB h2CKADzv8jio5Q4J+lC8+WTyiVekEvnonuB8ytmA/sx5jmaEH3kQYJNpsYaNh90pXL tTrZdop9aSi+a5tX4G8q7x6BMmDtJRfQjIdiX/Ld9FznDR0EsTlRUky0XqfG6Fk1Ev ZtuI8IlF+9ab41dVgivnSqwvOIlkPGbnq48Pt0W4eqlx1xgWFQnGg7TUY0Ol3ZAtxk b/b5qA+J7s1mA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40F66C61DBE; Tue, 25 Aug 2026 10:48:40 +0000 (UTC) From: Colin Huang via B4 Relay Date: Tue, 25 Aug 2026 18:47:46 +0800 Subject: [PATCH v6 05/12] ARM: dts: aspeed: anacapa: Add additional EEPROM node for SCM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260825-anacapa-devlop-phase-devicetree-v6-5-9059a2a279ce@gmail.com> References: <20260825-anacapa-devlop-phase-devicetree-v6-0-9059a2a279ce@gmail.com> In-Reply-To: <20260825-anacapa-devlop-phase-devicetree-v6-0-9059a2a279ce@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787654905; l=1224; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=6bqaYqKHlIwRPbR4gPkyIhffT51cOaBU7ByQ/FJQMrw=; b=XMu0Lx/noo3Yw4GhiYGV3uBQBVNQwxetTW3BuNLfMxGfGVAjhSLlcpJ1GPO/6ErE0vg0SL8e+ i8f/ZdGC4EgAUpb33SHEAvvzThzQk2Ducd4TDuZjNGdmY992hmkH7GZ X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Colin Huang The SCM FRU EEPROM I2C address differs between SCM revisions: - Rev B uses address 0x50 - Rev C/D/E/F and later use address 0x51 Add an additional AT24C128 EEPROM node at 0x51 on i2c9 so the same device tree can support multiple SCM revisions. Signed-off-by: Colin Huang --- .../boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 14 ++++++++++= ++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts index 075ac39f369f..d2b4855ff1ad 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts @@ -8,6 +8,20 @@ / { model =3D "Facebook Anacapa BMC"; }; =20 +// SCM +&i2c9 { + // SCM FRU + // | DC-SCM Rev | Slave address of eeprom | + // |-------------------|--------------------------| + // | Rev B | 0x50 | + // | Rev C/D/E/F/above | 0x51 | + + eeprom@51 { + compatible =3D "atmel,24c128"; + reg =3D <0x51>; + }; +}; + &sgpiom0 { bus-frequency =3D <2000000>; gpio-line-names =3D --=20 2.34.1 From nobody Mon Sep 28 06:37:49 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5CB43F660B; Tue, 25 Aug 2026 10:48:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787654920; cv=none; b=fLbBSRTnwn9sXccfspp96qh16hfXbfBBUPlQd0eegks/yGYxxw9LPqGsZrQjdiW0bKHHJhCZs2Ns1z/fvIeW1+CU6AdJhZeDdIoUi0Ad2Z0malydaA4vu0hSmB4mUDSoVSPgicakrJ+Xh/012W7CPjoDXYutqkqxh1Jcj/qOXAA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787654920; c=relaxed/simple; bh=hOPf1LjDT4s/OsOzZ2OJtL3XdwwW4MxYaI4DYi2V2sU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=plPAkNpB0oZM+opZ4Yc8alhAjsjqGP0ixN6oCxLPeAaFgrcEOMuAXk9w4yDdmUxhyoiKJiV1YRVZS447+jqTUR2WtyXlnf8RVSzrcUeO5wNRQQQZZwJlCd165Wqz2/MSPw2nt7OQRNeyNomyGSMizKtv8nHjuTPWtqb7fOqEJAQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OSFvEz5o; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OSFvEz5o" Received: by smtp.kernel.org (Postfix) with ESMTPS id 667DEC32781; Tue, 25 Aug 2026 10:48:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787654920; bh=hOPf1LjDT4s/OsOzZ2OJtL3XdwwW4MxYaI4DYi2V2sU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=OSFvEz5oV8Y3l/1TyLawkleLuvr2nBr89ZNKh22mbjevlimUgbpVaJyT6pqqVsLJd M01Q9d0g71TSoK8dSsPJM1jPbb0OAuajb3uGsRZeWTcvqGeYAnOH5TWMw7uvgmJDob Vt3CuHgZhSZ8+YYhYiRBl1jOik/3OZFxe2XsVTfI4aRcrgSqC1TQl1YfHXYdeiw3Ly cE9octPQldmxLD+Oi42p1gQGBVJsgYPZonl24wGEtTaAQhnKdD1hp4rp3Z5z1fP+mI byYu3FV16JO1ObHhH0asIs71U9+sm/tX+zF9dKwasqFsztlAfA7ncLrnmMVRdhF40O QV05thF2EWRtg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53F5BC61DB6; Tue, 25 Aug 2026 10:48:40 +0000 (UTC) From: Colin Huang via B4 Relay Date: Tue, 25 Aug 2026 18:47:47 +0800 Subject: [PATCH v6 06/12] ARM: dts: aspeed: anacapa: Add eeprom device node for NFC adaptor board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260825-anacapa-devlop-phase-devicetree-v6-6-9059a2a279ce@gmail.com> References: <20260825-anacapa-devlop-phase-devicetree-v6-0-9059a2a279ce@gmail.com> In-Reply-To: <20260825-anacapa-devlop-phase-devicetree-v6-0-9059a2a279ce@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang , Carl Lee X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787654905; l=842; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=W3IShAyxygRLxWChQBNmztwL/6A+5D13GAPOb/9nyvI=; b=5x1Obe8eZXfIFVi/XcjUmqoHbfzWEKr0Q2Ht3cV/i6rI0oARG/5URdCp987sJGxoggp4J2waU Fy/L2QvVoLqCe/2IXYU1hvkPrEWLB4L3HvsOWWn5V0E56PpgZEwEYKk X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Carl Lee Add eeprom device node for NFC adaptor board FRU. Signed-off-by: Carl Lee --- .../boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 13 +++++++++= ++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts index d2b4855ff1ad..22f79a2c2639 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts @@ -22,6 +22,19 @@ eeprom@51 { }; }; =20 +// MB +&i2c13 { + i2c-mux@70 { + i2c@7 { + // NFC adaptor board FRU + eeprom@50 { + compatible =3D "atmel,24c128"; + reg =3D <0x50>; + }; + }; + }; +}; + &sgpiom0 { bus-frequency =3D <2000000>; gpio-line-names =3D --=20 2.34.1 From nobody Mon Sep 28 06:37:49 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE4253F660F; Tue, 25 Aug 2026 10:48:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787654920; cv=none; b=dVsNlewIgLtS9Eu6hrNDLwa3az5a8dpcdqUtTB9zI9ltnZ2bIoSP7bZs+H9V9Ogy2ErIbnrUJJ7qcID+Exo299mQIT79MZDifJ204sgZUABnNWECWQ62qzLUPURufNNR6F6O0iPICHbGH1dMS3094jXQ3ZDFD9smuiBvAO0u/1c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787654920; c=relaxed/simple; bh=7B4CIvFBlUPoqiqtTNRDZlqFEZUDmeo/aZGl2e0vT6Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WHzCRiYBBn5a8ck4M5S04lHioGFiuAUm5owcbeYbAdjfi6Cmtz5DQKt25w5onWXobiUe9g5u/bXCjcJY2x+xBB7fSWAJvmVe1IL4qVa9wPFvXKxmxT8zwZYE2qYzFewCq0z/d3qczs32vqYpuht8yk4Sdf9Krd0ybKuuJ8/+bE8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hExsl1wj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hExsl1wj" Received: by smtp.kernel.org (Postfix) with ESMTPS id 997ABC2BCB8; Tue, 25 Aug 2026 10:48:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787654920; bh=7B4CIvFBlUPoqiqtTNRDZlqFEZUDmeo/aZGl2e0vT6Y=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=hExsl1wj6eTK18X5zeE7KYVkH3qo4KEwjQoMaGzMCva/8fQIqOXA4O6bBpbwkUmkR cMfYyA/wkN0hgkNqxyXfq7PZpummefwuJfFZVkdNlDkEVyowy+6RgbWX2QsZU0H8/v a4mPtIkisU/J0AD9IDco3YDh0MBaIlbv91fZ2aiyGeqmZi/6Wy7/l9MZc5IX/JOhLZ cjSMGjf8MwtlwpEXttJkzBpShVpcw4mTnAZzSjqQzJO/5ZbjTb/H6+O89jVi4o0y48 fbRtEKfQ2dT3WhXM34dawQ3SH/ncodYoAWCQz5FQHURQfZwTCrL6kUgxc8b3PF4dhJ JylukrL2NyKgQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85D3BC5DF94; Tue, 25 Aug 2026 10:48:40 +0000 (UTC) From: Colin Huang via B4 Relay Date: Tue, 25 Aug 2026 18:47:48 +0800 Subject: [PATCH v6 07/12] ARM: dts: aspeed: anacapa: Align PDB fan GPIO numbering Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260825-anacapa-devlop-phase-devicetree-v6-7-9059a2a279ce@gmail.com> References: <20260825-anacapa-devlop-phase-devicetree-v6-0-9059a2a279ce@gmail.com> In-Reply-To: <20260825-anacapa-devlop-phase-devicetree-v6-0-9059a2a279ce@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang , Rex Fu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787654905; l=1786; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=xut55nGmyVcLA4lUuB3YtiRCvXqR0OQ6rs4Nd5fFYK4=; b=IOqdIn3GqorvxZirolfm46DF6ukJ4TdtbZVfTl5uVVwUcq6q1pwAOnk7YMCDiATzWiaDYiJ5p tEnPc5HBFPnBYTZqUDqfIYBUeEV6bfUjM3WuVkdU9rSNepaVmYxKRHt X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Rex Fu Update the LPDB and RPDB fan GPIO line names to align with the platform fan numbering scheme. The LPDB fan GPIOs are named FAN0 through FAN4, while the RPDB fan GPIOs are named FAN5 through FAN8. This keeps the GPIO line names consistent with the fan inventory and platform-level fan numbering. Signed-off-by: Rex Fu --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 34 ++++++++++++++++++= ++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts index 22f79a2c2639..7c641a79f63e 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts @@ -8,6 +8,40 @@ / { model =3D "Facebook Anacapa BMC"; }; =20 +// MB - PDB +&i2c8 { + i2c-mux@72 { + i2c@0 { + gpio@24 { + gpio-line-names =3D + "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", + "RPDB_PWRGD_P50V_HSC4_SYS_R", + "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", + "RPDB_P50V_FAN5_R2_PG", "RPDB_P50V_FAN6_R2_PG", + "RPDB_P50V_FAN7_R2_PG", "RPDB_P50V_FAN8_R2_PG", + "", "RPDB_FAN5_PRSNT_N_R", + "", "RPDB_FAN6_PRSNT_N_R", + "RPDB_FAN7_PRSNT_N_R", "RPDB_FAN8_PRSNT_N_R", + "", ""; + }; + }; + + i2c@1 { + gpio@24 { + gpio-line-names =3D + "LPDB_P50V_FAN0_R2_PG","LPDB_P50V_FAN1_R2_PG", + "LPDB_P50V_FAN2_R2_PG","LPDB_P50V_FAN3_R2_PG", + "LPDB_P50V_FAN4_R2_PG","LPDB_FAN0_PRSNT_N_R", + "LPDB_FAN1_PRSNT_N_R","LPDB_FAN2_PRSNT_N_R", + "LPDB_FAN3_PRSNT_N_R","LPDB_FAN4_PRSNT_N_R", + "","", + "","", + "",""; + }; + }; + }; +}; + // SCM &i2c9 { // SCM FRU --=20 2.34.1 From nobody Mon Sep 28 06:37:49 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E13443F7AB2; Tue, 25 Aug 2026 10:48:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787654921; cv=none; b=Gvq+9PGluVOvOaNKDHUXfAPrGYKEEScWDo6dJxk+KfExLhdQKdZ9v3q386/kVbULgCkQMErVHwGH+vRk17hasNTwLcYEu4L82VVgt1iVjA5TqXdXiMMpIhrnci6M/K/VGZeq5Ly45jAiOfiY3kuZ6wdLYJ+vhbImvq69IPhNEOg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787654921; c=relaxed/simple; bh=x266lsRftT8i25oBXl2ssgbHQhGOw8P7oh+KboxNXTY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Tue, 25 Aug 2026 10:48:40 +0000 (UTC) From: Colin Huang via B4 Relay Date: Tue, 25 Aug 2026 18:47:49 +0800 Subject: [PATCH v6 08/12] ARM: dts: aspeed: anacapa: Enable MCTP and FRU for NIC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260825-anacapa-devlop-phase-devicetree-v6-8-9059a2a279ce@gmail.com> References: <20260825-anacapa-devlop-phase-devicetree-v6-0-9059a2a279ce@gmail.com> In-Reply-To: <20260825-anacapa-devlop-phase-devicetree-v6-0-9059a2a279ce@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang , Andy Chung X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787654905; l=3240; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=dOnAmtbd66IVx7oXtqFQ1g3XoTMO1Ryg0F0x9FVbMP8=; b=ftyDPTkjdoGzotF4l5iWYs6uhTqylEgD5qyrES/Ylqri27+Dso7FI2I0uqGRiBcqYUp1nMkgc Dw7Lg2km/n5BgNptYTxctfAUFsGd5PPJiJW0yhYnmlyaZzPlc0+/kUh X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Andy Chung Add the mctp-controller property to enable frontend NIC management via PLDM over MCTP. Also add EEPROM device for NIC FRU and reorder the I2C virtual bus index accroding to the system silkscreen index. Signed-off-by: Andy Chung --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 137 +++++++++++++++++= ++++ 1 file changed, 137 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts index 7c641a79f63e..7fe8d279202a 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts @@ -8,6 +8,25 @@ / { model =3D "Facebook Anacapa BMC"; }; =20 +&{/aliases} { + i2c36 =3D &i2c11mux0ch5; + i2c37 =3D &i2c11mux0ch6; + i2c38 =3D &i2c11mux0ch7; + i2c39 =3D &i2c11mux0ch0; + i2c40 =3D &i2c11mux0ch1; + i2c41 =3D &i2c11mux0ch2; + i2c42 =3D &i2c11mux0ch3; + i2c43 =3D &i2c11mux0ch4; + i2c44 =3D &i2c10mux0ch1; + i2c45 =3D &i2c10mux0ch2; + i2c46 =3D &i2c10mux0ch3; + i2c47 =3D &i2c10mux0ch4; + i2c48 =3D &i2c10mux0ch5; + i2c49 =3D &i2c10mux0ch6; + i2c50 =3D &i2c10mux0ch7; + i2c51 =3D &i2c10mux0ch0; +}; + // MB - PDB &i2c8 { i2c-mux@72 { @@ -56,6 +75,124 @@ eeprom@51 { }; }; =20 +// R Bridge Board +&i2c10 { + multi-master; + + mctp@10 { + compatible =3D "mctp-i2c-controller"; + reg =3D <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + i2c-mux@71 { + /delete-property/ i2c-mux-idle-disconnect; + + i2c10mux0ch1: i2c@1 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + + i2c10mux0ch2: i2c@2 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + + i2c10mux0ch3: i2c@3 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + + i2c10mux0ch4: i2c@4 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + }; +}; + +// L Bridge Board +&i2c11 { + multi-master; + + mctp@10 { + compatible =3D "mctp-i2c-controller"; + reg =3D <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + i2c-mux@71 { + /delete-property/ i2c-mux-idle-disconnect; + + i2c11mux0ch0: i2c@0 { + mctp-controller; + // FE NIC FRU + + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + + i2c11mux0ch1: i2c@1 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + + i2c11mux0ch2: i2c@2 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + + i2c11mux0ch3: i2c@3 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + + i2c11mux0ch4: i2c@4 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + }; +}; + // MB &i2c13 { i2c-mux@70 { --=20 2.34.1 From nobody Mon Sep 28 06:37:49 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E95403F822A; Tue, 25 Aug 2026 10:48:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260825-anacapa-devlop-phase-devicetree-v6-9-9059a2a279ce@gmail.com> References: <20260825-anacapa-devlop-phase-devicetree-v6-0-9059a2a279ce@gmail.com> In-Reply-To: <20260825-anacapa-devlop-phase-devicetree-v6-0-9059a2a279ce@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang , Peter Shen X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787654905; l=2042; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=Nkr6isVpDdRMMBTaTgNrI6h8ViGx2pJj1Pj8jJLDOHI=; b=PbLx5G7AHzh5WHvsZjQlObM/t2WWS+f13JDDHoRPhAHTS4EM3/Kmx+wi9urIcxgO1YkJ1mwJP hZ1XInQY+ZCCpJwGP+ghsQrYIQ6SCJwXAdU+hKj3MluKtF1s2p7jfKT X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Peter Shen Add shunt resistor configuration for LTC4287 hot-swap controllers on Anacapa EVT2 platform. The resistor values are required for accurate current and power measurement by the driver. These settings reflect the actual BOM used on EVT2, where different sense resistor values (150 uOhm and 250 uOhm) are populated across rails. Without this configuration, the reported readings would be incorrect. Signed-off-by: Peter Shen --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 42 ++++++++++++++++++= ++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts index 7fe8d279202a..c36519a601a9 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts @@ -43,6 +43,30 @@ gpio@24 { "RPDB_FAN7_PRSNT_N_R", "RPDB_FAN8_PRSNT_N_R", "", ""; }; + + power-monitor@42 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x42>; + shunt-resistor-micro-ohms =3D <150>; + }; + + power-monitor@43 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x43>; + shunt-resistor-micro-ohms =3D <150>; + }; + + power-monitor@44 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x44>; + shunt-resistor-micro-ohms =3D <250>; + }; + + power-monitor@45 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x45>; + shunt-resistor-micro-ohms =3D <250>; + }; }; =20 i2c@1 { @@ -57,6 +81,24 @@ gpio@24 { "","", "",""; }; + + power-monitor@40 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x40>; + shunt-resistor-micro-ohms =3D <150>; + }; + + power-monitor@41 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x41>; + shunt-resistor-micro-ohms =3D <150>; + }; + + power-monitor@45 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x45>; + shunt-resistor-micro-ohms =3D <250>; + }; }; }; }; --=20 2.34.1 From nobody Mon Sep 28 06:37:49 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 087AC3F8241; Tue, 25 Aug 2026 10:48:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787654921; cv=none; b=V2SkyTnozoUCDRqY3mqtGki50oM/Z4MDGDD/cadUc+T5hQlPY4adAm33XfypVSIz9L9iKrsuNqmFcYfq7KbSDj0iQyONCFf/WO73tM7mLKGBfHYUSv8iMn9i5owpJQJlwrTfyLi1KC6FIF5Yka+5Iv7zcJi9RLPp205E6uE1p78= ARC-Message-Signature: i=1; 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b=a3cZLascbDxL1ZPivBZ5+d92jyNU9u8kz28ZCtM0E0UzGdYZYlbrUc4bo/q6DR6Qr IA+YswSO7Ea/cMka9/rtuilA7SdOoyL8yUUdbMQOwDkMNtgPnEWYSqq8nhC7r+bhL4 O/zw5BIXfy5wCCe4zWF/OR8WDVa30Ho3hnqnzp89Xv8HRJPhjrverB/4W9SO0Jbd3S wVO1UWWvx8htDS1ahpBrN84mTYPHMNCXBSQ83PdrqxVHOwVq89a8obiZAjJr6iWr68 4aVfegnGKqHZNZ/Likh/Yhgz1jaXt3fZpYtg7MrCDztYcWGMccBudmHTx5qShW6JHF VJibGegl6sbqA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9330C61DC4; Tue, 25 Aug 2026 10:48:40 +0000 (UTC) From: Colin Huang via B4 Relay Date: Tue, 25 Aug 2026 18:47:51 +0800 Subject: [PATCH v6 10/12] ARM: dts: aspeed: anacapa: Add LPDB fuse monitor GPIO expander Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260825-anacapa-devlop-phase-devicetree-v6-10-9059a2a279ce@gmail.com> References: <20260825-anacapa-devlop-phase-devicetree-v6-0-9059a2a279ce@gmail.com> In-Reply-To: <20260825-anacapa-devlop-phase-devicetree-v6-0-9059a2a279ce@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang , Rex Fu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787654905; l=3697; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=E531mFcQuSg4vkfS0BrbVzRcV4G9+LgoYtq/R4Xx1MI=; b=UjQBhYpkRedPJGHhjHpjBxaA7X7I2AKSg5HvZVfdXO73zjLgpdDG00HVQ0TMRWF2h4ynW5o8K giROwDkqboJAqjqasdnTAu8sFudjHh//Uaw8jhZy44wIXQStaTXYPeG X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Rex Fu Add PCA9554 GPIO expanders for PDB fuse monitor signals on the Anacapa DVT board. The patch adds GPIO expander definitions for both the left and right PDBs under the i2c8 multiplexer and updates the associated gpio-line-names to reflect the final signal assignments. Signed-off-by: Rex Fu --- .../dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts | 92 ++++++++++++++++++= ++++ 1 file changed, 92 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts b= /arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts index 975d603ca540..923954cff7a2 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts @@ -8,6 +8,98 @@ / { model =3D "Facebook Anacapa BMC"; }; =20 +// MB - PDB +&i2c8 { + i2c-mux@72 { + i2c@0 { + gpio@22 { + gpio-line-names =3D + "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TMP432_U8_ALERT_R_N", + "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP", + "RPDB_FAN_CT_FAN_FAIL_R_N", "RPDB_VERID_A0", + "RPDB_VERID_A1", "RPDB_VERID_A2", + "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N", + "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N", + "RPDB_P12V_MB_VRM_ALERT_R_N", + "RPDB_P12V_STBY_VRM_ALERT_R_N", + "RPDB_PGD_P3V3_STBY_PWRGD_R", + "RPDB_P12V_STBY_VRM_PWRGD_BUF_R"; + }; + + gpio@24 { + gpio-line-names =3D + "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", + "RPDB_PWRGD_P50V_HSC4_SYS_R", + "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", + "RPDB_P50V_FAN5_R2_PG", "RPDB_P50V_FAN6_R2_PG", + "RPDB_P50V_FAN7_R2_PG", "RPDB_P50V_FAN8_R2_PG", + "RPDB_SKU_ID0", "RPDB_FAN5_PRSNT_N_R", + "", "RPDB_FAN6_PRSNT_N_R", + "RPDB_FAN7_PRSNT_N_R", "RPDB_FAN8_PRSNT_N_R", + "", ""; + }; + + gpio@38 { + compatible =3D "nxp,pca9554"; + reg =3D <0x38>; + #gpio-cells =3D <2>; + gpio-controller; + + gpio-line-names =3D + "RPDB_P50V_FUSE2_TVS1", "RPDB_P50V_FUSE2_TVS2", + "RPDB_P50V_FUSE3_TVS1", "RPDB_P50V_FUSE3_TVS2", + "RPDB_P50V_FUSE4_TVS1", "", + "", ""; + + interrupt-parent =3D <&sgpiom0>; + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + i2c@1 { + gpio@22 { + gpio-line-names =3D + "LPDB_FAN_FULL_SPEED_R_N", "LPDB_I2C_TEMP75_U8_ALERT_R_N", + "LPDB_I2C_TMP432_U29_ALERT_R_N", "LPDB_GLOBAL_WP", + "LPDB_FAN_CT_FAN_FAIL_R_N", "LPDB_VERID_A0", + "LPDB_VERID_A1", "LPDB_VERID_A2", + "LPDB_ALERT_P50V_HSC0_R_N", "LPDB_ALERT_P50V_HSC1_R_N", + "LPDB_ALERT_P50V_HSC5_R_N", "LPDB_I2C_P12V_SW_VRM_ALERT_R_N", + "LPDB_EAM0_PRSNT_MOS_N_R", "LPDB_EAM1_PRSNT_MOS_N_R", + "LPDB_PWRGD_P50V_HSC5_SYS_R", "BARKLIP_PRSNT_N_R3"; + }; + + gpio@24 { + gpio-line-names =3D + "LPDB_P50V_FAN0_R2_PG", "LPDB_P50V_FAN1_R2_PG", + "LPDB_P50V_FAN2_R2_PG", "LPDB_P50V_FAN3_R2_PG", + "LPDB_P50V_FAN4_R2_PG", "LPDB_FAN0_PRSNT_N_R", + "LPDB_FAN1_PRSNT_N_R", "LPDB_FAN2_PRSNT_N_R", + "LPDB_FAN3_PRSNT_N_R", "LPDB_FAN4_PRSNT_N_R", + "LPDB_SKU_ID0", "", + "", "", + "", "LPDB_PG_P3V3_R"; + }; + + gpio@38 { + compatible =3D "nxp,pca9554"; + reg =3D <0x38>; + #gpio-cells =3D <2>; + gpio-controller; + + gpio-line-names =3D + "LPDB_P50V_FUSE0_TVS1", "LPDB_P50V_FUSE0_TVS2", + "LPDB_P50V_FUSE1_TVS1", "LPDB_P50V_FUSE1_TVS2", + "LPDB_P50V_FUSE5_TVS1", "", + "", ""; + + interrupt-parent =3D <&sgpiom0>; + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + }; + }; + }; +}; + &sgpiom0 { bus-frequency =3D <2000000>; gpio-line-names =3D --=20 2.34.1 From nobody Mon Sep 28 06:37:49 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E3AD3F99F4; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260825-anacapa-devlop-phase-devicetree-v6-11-9059a2a279ce@gmail.com> References: <20260825-anacapa-devlop-phase-devicetree-v6-0-9059a2a279ce@gmail.com> In-Reply-To: <20260825-anacapa-devlop-phase-devicetree-v6-0-9059a2a279ce@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang , Rex Fu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787654905; l=2439; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=XQDIFJln5LUr5je4HHMPl/KkFoydy7hdQv6lmXRo/nY=; b=JJh19acHLjk6BIqON54AAAJ6nyD0BvJmNb6ViLscQ/8AMPUHM5zo2qxzukGzxq1vXpnX1HRLl rJym+UyEozwDubZhvHJKaJGhhJ7VjojmhoM6Sp11os25nYIsPTSEqZ6 X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Rex Fu Remove the board location suffixes from the leakage present GPIO line names. The channel number is enough to identify each leakage present signal. Signed-off-by: Rex Fu --- .../dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts | 28 +++++++++++-------= ---- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts b= /arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts index 923954cff7a2..ce5aecc984c8 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts @@ -115,32 +115,32 @@ &sgpiom0 { "", "", =20 /* B0-B7 line 16-31 */ - "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", - "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", - "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", - "Channel5_leakage_present_EAM1", "FM_CPU0_NMI_SYNC_FLOOD_N", - "Channel4_leakage_Manifold2", "BMC_AINIC0_WP_R2_L", - "Channel5_leakage_EAM1", "BMC_AINIC1_WP_R2_L", - "Channel6_leakage_CPU_DIMM", "CPLD_BUF_R_AGPIO330", - "Channel7_leakage_EAM2", "CPLD_BUF_R_AGPIO331", + "Channel0_leakage", "FM_CPU_FPGA_JTAG_MUX_SEL", + "Channel1_leakage", "FM_SCM_JTAG_MUX_SEL", + "Channel2_leakage", "FM_BRIDGE_JTAG_MUX_SEL", + "Channel5_leakage_present", "FM_CPU0_NMI_SYNC_FLOOD_N", + "Channel4_leakage", "BMC_AINIC0_WP_R2_L", + "Channel5_leakage", "BMC_AINIC1_WP_R2_L", + "Channel6_leakage", "CPLD_BUF_R_AGPIO330", + "Channel7_leakage", "CPLD_BUF_R_AGPIO331", =20 /* C0-C7 line 32-47 */ "RSVD_RMC_GPIO3", "RTM_MUX_L", "LEAK_DETECT_RMC_N", "RTM_MUX_R", "HDR_P0_NMI_BTN_BUF_R_N", "FPGA_JTAG_SCM_DBREQ_N", - "Channel6_leakage_present_CPU_DIMM", "whdt_sel", + "Channel6_leakage_present", "whdt_sel", "R_EAM0_NIC_CBL_PRSNT_L", "JTAG_CPLD_TRST_R_N", "R_EAM1_NIC_CBL_PRSNT_L", "", "L_EAM0_NIC_CBL_PRSNT_L", "", "L_EAM1_NIC_CBL_PRSNT_L", "", =20 /* D0-D7 line 48-63 */ - "Channel0_leakage_present_EAM3", "", - "Channel1_leakage_present_EAM0", "", - "Channel2_leakage_present_Manifold1", "", - "Channel4_leakage_present_Manifold2", "", + "Channel0_leakage_present", "", + "Channel1_leakage_present", "", + "Channel2_leakage_present", "", + "Channel4_leakage_present", "", "AMC_BRD_PRSNT_CPLD_L", "", - "Channel7_leakage_present_EAM2", "", + "Channel7_leakage_present", "", "", "", "", "", =20 --=20 2.34.1 From nobody Mon Sep 28 06:37:49 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3844C3F9F2B; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260825-anacapa-devlop-phase-devicetree-v6-12-9059a2a279ce@gmail.com> References: <20260825-anacapa-devlop-phase-devicetree-v6-0-9059a2a279ce@gmail.com> In-Reply-To: <20260825-anacapa-devlop-phase-devicetree-v6-0-9059a2a279ce@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang , Rex Fu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787654905; l=1370; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=LtEnhYtDTDdaFJ8Tq5vy4icjC937RP4+reqqmwZJfEY=; b=tPqM9x7iBx4Q7kaW/I2LUyeTaNwihkP+gBdmjQ9uMV+pvqC+B1zq5uUw2RQ4umZ7N8hhJCHjl rfrrsJmtiDxA1XkeI9iLyhclx/ysdHZhAwGTk2LJj6kxjjDlz53EkQH X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Rex Fu Specify the 3.3 V auxiliary rail as the SPI flash VCC supply to avoid using the dummy regulator during device initialization. Signed-off-by: Rex Fu Signed-off-by: Colin Huang --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 25 ++++++++++++++++++= ++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts index c36519a601a9..ecb1c86f9e90 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts @@ -6,6 +6,14 @@ / { compatible =3D "facebook,anacapa-bmc-evt2", "aspeed,ast2600"; model =3D "Facebook Anacapa BMC"; + + p3v3_bmc_aux: regulator-p3v3-bmc-aux { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "p3v3_bmc_aux"; + }; }; =20 &{/aliases} { @@ -27,6 +35,23 @@ / { i2c51 =3D &i2c10mux0ch0; }; =20 +&fmc { + flash@0 { + vcc-supply =3D <&p3v3_bmc_aux>; + }; + + flash@1 { + vcc-supply =3D <&p3v3_bmc_aux>; + }; +}; + +// BIOS Flash +&spi2 { + flash@0 { + vcc-supply =3D <&p3v3_bmc_aux>; + }; +}; + // MB - PDB &i2c8 { i2c-mux@72 { --=20 2.34.1