From nobody Mon Sep 28 08:55:48 2026 Received: from mail-oa1-f51.google.com (mail-oa1-f51.google.com [209.85.160.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 734B441F5D4 for ; Mon, 24 Aug 2026 13:05:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576715; cv=none; b=WhWdwDbja0zCHPQuoGSkN1a6TmOWz0DARwo/DscrFlDOovJIk4eVxKeu/tQSLvUEiWaBW8K4nW5QCUBfLMeWrr1e3gKHs+nUMENTtKLdFDYfy5NpnA0X7SjrONpYfgOTNA2r9nWME5TXv3VurDQVX/9g+zhxEcWAcxHjGsgEOIs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576715; c=relaxed/simple; bh=pbOuLnMdY2W+iCdw66yndLQjoRN+QvlknxTRrElQL8E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Nv+omnHRoRyIQUIIv9m9dTBE7f+qoXhysiSrDpx0ue9ZvdFZqiqdeKJ8SV9TJ0OcV4TAh3wlwoKd9YFoPOQ+KW6kKOfznsB6AUm/n7HYiEejyiZaUm9cD44XVK7JB2B7l/z+FUVKf9Qp6E2dwe3lYYQkkDXQX382cuJjSZvWXkI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=HDeBg8Hn; arc=none smtp.client-ip=209.85.160.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="HDeBg8Hn" Received: by mail-oa1-f51.google.com with SMTP id 586e51a60fabf-45eddb6fdccso1824096fac.2 for ; Mon, 24 Aug 2026 06:05:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787576711; x=1788181511; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=068pYnBVpLmUX/vSkfsFSQIv11h+T+N0t9GB6UkmtgU=; b=HDeBg8Hna/geD1n1B3JgsT0q3KEg8go8efjdUh6y+LbzF0Jv2Eew/g21tYygLzLuKU NIQTSiRyC92o3VHcES50TLjmhu1BC6Dxhmn8EVTm5oSFZbhVsPF48/gJLRHmr6/DD9qr tcsr/KbgOFPHWHKGfJC8Dk5kcpcKhQ7KP1dr96vuZMIQmKD6ibxU1IiYxVPE7G56b9MG k7ULvlHSNpf/Q1Zf8eUJn1iLuVtAkcx+XqEcFzXotmgWcPgzQ5Kw0NnDCaTJz9NWz+iX DYd7PFQxoCXFIIPsJ0pGI0MwEF9yjfjJA5/FKgjrzVF1haYySujztV8VYAGMwtt6JD0K kKeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787576711; x=1788181511; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=068pYnBVpLmUX/vSkfsFSQIv11h+T+N0t9GB6UkmtgU=; b=Xa5nW5C+NLLeXHNhzKRIEkWxXLEhVuDGDTTr7ZHumAuju4TLG7/Ydmb2sUXcpMbokN 4O/s2o6FbcX98/g2bnMaV4KSTTlKQbVn261R69FBacWQ7pITnBVudVy75k9RolX3qFPl Ta3KxeNM9twFK+UBHH/Tqi8+ObT0YcSeF175jm6JxxmlPdwDCJKzbVnlTs/yxZgY5sZT FZ1GrSc5l4eMuHtZfbbPb+AuMBhR1KfDv/FCOOhWbZttu/iAtk6fOzB5dBMU/DuezBK6 hy9OYd5OgIeuC/lBs/828sjte7eNMCoBcChJgPC4qP4GL4gMLAPZwOSHiwyjFeO42hy7 NVVg== X-Forwarded-Encrypted: i=1; AHgh+Ro9jnNaqcj2i3UNCAd6yYqOt7obsK6m07GvM/AdOIkoRnlvvNlAMNX43JWQsdltUUwRiIdjFqPC1iMXj7E=@vger.kernel.org X-Gm-Message-State: AFuF++kiWMt8xXz2CF024qmrxu5SMBmnxERDQcIjVkqSMaI2zKwYXKH4 BngnNzoB1QlB0bMtRuBfFSYVziS0Q0tCKwwJ7ZgmhU2Ll+dj8fSpw9C1 X-Gm-Gg: AR+sD13yTfMadO2ZErrbRBQoscCtn+1r4ciaYdgzg0h/JtP96ZLBYtP5FHoW+iMNWlL /1SbcRgMpGjvK78xr7qckdmiN0vTTgSLUIT7bfl+bJ8SD9ha10k8pXq6T2yL+sM3VBFI636uD61 qJB3v0TZr0OVbt0DBlKBW9BHTo+jbALqNSlQFPT6N08PMOMcvFLDOtlC0ZIiZncxU8IuAKzNqgi OzizNEP9EifDerWaVcnB16y3d6T9klv9Bpd9GPLII5VCrccKVUXIUo5mgM8iFfpgn3eKNce4zz4 W/67EyUkn+24ytszFBZepybseIK609KiJ35jdnRHVlR4yP+eCjC4uX9YscVRZ2PTumYLuFH/h2C rBbDqBJETb6FmHH4uun1RUp2/WZyzG9SlsNSt4styxc7wp7F8ukQuGSZkvop4XmWolleMdNJcrr Srs4tPqYORWbuQ/G5W2NKIlw3NLrbMIqNH7+NB21VrxIb2ARWtKSlUAFL7KXGRy8zq9EKMiyfFE 8OD8s+JF64ReqJIInjZg4I= X-Received: by 2002:a05:6820:a50c:b0:6b1:5180:bc73 with SMTP id 006d021491bc7-6b15925dbc4mr18970135eaf.15.1787576711215; Mon, 24 Aug 2026 06:05:11 -0700 (PDT) Received: from localhost.localdomain ([152.59.223.115]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-327f92359c9sm26409711eec.27.2026.08.24.06.05.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 06:05:10 -0700 (PDT) From: Sreeshankar K To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, konradybcio@kernel.org, tglx@kernel.org, ulfh@kernel.org Cc: bmasney@redhat.com, radu@rendec.net, abel.vesa@oss.qualcomm.com, lpieralisi@kernel.org, taniya.das@oss.qualcomm.com, danila@mainlining.org, davidwronek@gmail.com, mani@kernel.org, robimarko@gmail.com, linux@gurudas.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K , Krzysztof Kozlowski , Konrad Dybcio , Dmitry Baryshkov Subject: [PATCH v5 01/13] dt-bindings: arm: qcom,ids: Add SoC ID for SM7250 Date: Mon, 24 Aug 2026 13:04:25 +0000 Message-ID: <20260824130437.2771-2-sreeshankar0910@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260824130437.2771-1-sreeshankar0910@gmail.com> References: <20260824130437.2771-1-sreeshankar0910@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the ID for the Qualcomm SM7250 SoC. Acked-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Sreeshankar K --- include/dt-bindings/arm/qcom,ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/q= com,ids.h index 2cf433f61..b63e4a0b8 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -209,6 +209,7 @@ #define QCOM_ID_IPQ8172 397 #define QCOM_ID_IPQ8173 398 #define QCOM_ID_IPQ8174 399 +#define QCOM_ID_SM7250 400 #define QCOM_ID_IPQ6018 402 #define QCOM_ID_IPQ6028 403 #define QCOM_ID_SDM429W 416 --=20 2.43.0 From nobody Mon Sep 28 08:55:48 2026 Received: from mail-ot1-f54.google.com (mail-ot1-f54.google.com [209.85.210.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 926B341F5CA for ; Mon, 24 Aug 2026 13:05:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576724; cv=none; b=bjTNBSmUgezz36eP0K3TkluaTh1JoO6it6feNpIgvHp5uEHtB6fDgS7NuzEGDbrCde/cVdHCzIHxCW9pdHDztsE7YILZoMrllifeSDpYV7+gaFqIaecIdz6OYM+IKDD87q5bZ4Wkoc8mkhTEgk1Py06V1jiu1K3rDlq9FJZ3Swg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576724; c=relaxed/simple; bh=0wB3huwwaG49ycl517NSgfQ5t7SptdZ6MYz/Al88uo8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qEdgmbvPzBV+BSKwJhnQenKfKMAJRleOQrfnnOijKdEVJiqFeMsVeOWzQ7cnBwerpSePfW2HNqT812qcbjq8ixdVR+rAzAP+6nxSzlzQou3yYimQcO5GeaEF/tDqc3U3Ktz9ZqbHW/4bZfhvOy34L+SG/CuaG4WAUItktIY7mAc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=TQ5hszws; arc=none smtp.client-ip=209.85.210.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TQ5hszws" Received: by mail-ot1-f54.google.com with SMTP id 46e09a7af769-7f3fd905828so3205943a34.1 for ; Mon, 24 Aug 2026 06:05:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787576721; x=1788181521; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=mvJP88qTTuZPBMVLY1eZgRPCHAr9o03VzsEiEHnDVHs=; b=TQ5hszwsadExAZ/HgzBagiaYn1wZ2NWrPaj8sBg36pMmNwsmhWLSS5qIBL3Ls3tMsf wVmBlq5gGEMy+CbP3tXZTb3J7uIpRxlW3aZ/moH1cVCDCS94RTMeyCGKoJ0OjYkC4G9l Gsv6c0RgCKM9bafNWC3FmcRL3vN8H3yhj7n+anve+JH8meFARlwsjt/7ptiPSxjorNXW OwiBvruGYrU/Bo7EACrx/NTejhIHFaO4gzaprT0QIb9Tfu/FzofwxDxiNnMQ9aS0Ue9k i2IGMQ4tMQeSz6J0UBJFVvM2VsAcpluiTbUlm5RMqsJKkRsdy322dsRySdFkPz0EGpCZ sADg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787576721; x=1788181521; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=mvJP88qTTuZPBMVLY1eZgRPCHAr9o03VzsEiEHnDVHs=; b=pin810D+lAtkw4pXYrawrAr/C9jyGeQj48y2ApsaHgI/lIgo4mMEsitDK3jAGddyJk Kpz3tY6WNTgo0Aog39+eexS/HIADLboNc2uXXBb2DmEkdtHxxAtGHpzjgwodkXRHdCpA jZTZ3F2Vi5pOoO/wQIY87k/lsqQ2kXeaCsYkJLXbUzdq56GTvkwoOBQKosSe2EP0FxvK 4yui6P/IReUinVf/LpAdqbo60Vp5ibkW2d6Kj2ZfqSEjeXikwyD8tAhPF7yOGc9AChuc KQkRyD/52Rxv5q1gDesfFy2TKl3pfcB7jKsTIZYrLpAimNNxLoIGUjaWXMQ169kno1O/ pRuQ== X-Forwarded-Encrypted: i=1; AHgh+Rr9J+4YJ9InnB5JeZbykQEdjWD2Bad6xxB40jOVCgOkPk1D0NIfzSBME0oD2tqyoFoA09aGU5o01kU5QJA=@vger.kernel.org X-Gm-Message-State: AFuF++m7CnxJylX/OWVcFxqPs9edIXwSO4YOMLHXlPkqBxWMAO6Mwpr6 CI6tphHxpFtyww2622a3FVIchl02omvfhk8UTyEurPXgpBTIW83kIAq+ X-Gm-Gg: AR+sD11bLNTZ+pBdx6/LrQrqWLhHWAh3FnE+6ML7M4yjb20kNlAum1PapjT0FhZZJyW qtHpsMEHXVdhMrsvUfAcTl5V0CupwVuIPWKIfUKDUsZwtjvAbVNDufP5NYD4+JWfWaryBC4wqg0 0mso9Ap5yxzFa+NLeZqE52Oh0OocU3azSsApekyWYmcAWs97F1I5GvxQmKvB9cb1A1ivO/ePf43 dqIBmX+xZcs4XOVufaAP5As+MnEMMIRyFZDcnV8hi6mSV8O6OVaaCYpAiMYO8puQuxq3Zp3Z5qZ DkzrJ/5E6sjdpZz7wEveHOHAVW8fHE0WtNrukIgENeaQuiZ5g/ASTTCd6SdLr4dnq/xCzgasUmw mPZAlDCcV11wJFUWN7JmYUuhvj/B5SENL8eYqqCVUYcB+6bX/P8WkYGH29Ic/Am46j8wrFmbxG8 MPOhu1Sxr6wji4HziRYpWIK0ebkaADI7YN/v4UfyzTDS36SNfTd18lBlZVL7K88Lg+yXNKPAnuj Ytek1JtseE+ X-Received: by 2002:a05:6820:1629:b0:6b1:7ee2:6d42 with SMTP id 006d021491bc7-6b17ee28ef3mr6476143eaf.27.1787576721331; Mon, 24 Aug 2026 06:05:21 -0700 (PDT) Received: from localhost.localdomain ([152.59.223.115]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-327f92359c9sm26409711eec.27.2026.08.24.06.05.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 06:05:20 -0700 (PDT) From: Sreeshankar K To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, konradybcio@kernel.org, tglx@kernel.org, ulfh@kernel.org Cc: bmasney@redhat.com, radu@rendec.net, abel.vesa@oss.qualcomm.com, lpieralisi@kernel.org, taniya.das@oss.qualcomm.com, danila@mainlining.org, davidwronek@gmail.com, mani@kernel.org, robimarko@gmail.com, linux@gurudas.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K , Dmitry Baryshkov Subject: [PATCH v5 02/13] soc: qcom: socinfo: Add SM7250 SoC ID Date: Mon, 24 Aug 2026 13:04:26 +0000 Message-ID: <20260824130437.2771-3-sreeshankar0910@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260824130437.2771-1-sreeshankar0910@gmail.com> References: <20260824130437.2771-1-sreeshankar0910@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add SoC ID for Qualcomm SM7250 SoC. Reviewed-by: Dmitry Baryshkov Reviewed-by: Abel Vesa Signed-off-by: Sreeshankar K --- drivers/soc/qcom/socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 1836e226a..63ee5cd56 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -450,6 +450,7 @@ static const struct soc_id soc_id[] =3D { { qcom_board_id(IPQ8172) }, { qcom_board_id(IPQ8173) }, { qcom_board_id(IPQ8174) }, + { qcom_board_id(SM7250) }, { qcom_board_id(IPQ6018) }, { qcom_board_id(IPQ6028) }, { qcom_board_id(SDM429W) }, --=20 2.43.0 From nobody Mon Sep 28 08:55:48 2026 Received: from mail-pj1-f46.google.com (mail-pj1-f46.google.com [209.85.216.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4DF2420479 for ; Mon, 24 Aug 2026 13:05:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576734; cv=none; b=e8he0lbEj2lFVwyCDNe57jaVRkffySGh7RKAgpe5GPFZEqrC58IuXNhZShMNMQvBhwlm9eiw7L4LNn2CiEyt5POXgyhCHgdfuaF7TeUQ3Sb4g6U0BthrLbNmgBqI8G6k7Ft37ktI/KGiZ6lLKBPuivJdWu3QF+caphM/8ypeVSo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576734; c=relaxed/simple; bh=TzgPSR5vt7Zmz5hrBvIOUcULGYsDswbliTKtrlos6Zw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=g9xTZbmYrK2XDpwxM4bv1lw07V3NrpIYnU9Vl9LOBcv7jhelVH++T/oHr+hp4zioWYmt5M/nb5m63Fk4xtq2+0mk+RqD8DiKYrM9r95PtLeJPJwr20vxXEep2WIClRKHULhhFu77Uv3nKhJjE0QA6keSQpytlsJ0WiWlxfHTXY8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=TEhobsCa; arc=none smtp.client-ip=209.85.216.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TEhobsCa" Received: by mail-pj1-f46.google.com with SMTP id 98e67ed59e1d1-38ec1402b05so2620153a91.2 for ; Mon, 24 Aug 2026 06:05:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787576732; x=1788181532; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=+ZrAiYjHQlOkTbww6JuB7Q+sjD0nHy2uwB58G9ysiiw=; b=TEhobsCacMKhvI+JPycImbtL3EAoxkCH07J3v6dXg+nhgtb5CpDv/yjwlXE6xg2xlM c3NTDvkiXXG7NHoXr42nLKkT1AIlIgaB9sTJ+og3UEqSa+O062A0jcJFc+NhTbbEivZ1 Jwi/hiEPhn8UVpuAqiWZUirpz1eUuASn7puWsSbC6RnT6q1l8ZPOMnZ2tkzlXiyjL1mS blZoctDnEbtErahBjn5cgha8m/8RBREfJRZLzfdDthrE6RdxVa1RQLpIa1r14EYemNkJ IisDE2zxXGNwqGUqso24sfs8YX9sNBmEjRdK0W1PwOrLmGNAwtUg93A/NNBqyXHsVcmL Q2YA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787576732; x=1788181532; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=+ZrAiYjHQlOkTbww6JuB7Q+sjD0nHy2uwB58G9ysiiw=; b=UD7GdeDhi3mjwuf7qzohh26fbaLO74NRaRaOwMCdrzBbipx3eGoOJS2b134NF0PmQS tg9t9KAPU4fa5z5hA/zuJV6dZkw2CTSoQVRYMZ76PqiZEGJxPYPz94cfKWIwGagy2Prv UBn2aU9bIU5bMr0hFUX7Cl0ptTXVMmlHoS/nsy4kSyQ/F71RcdTYK1/dhEpKkG1X4Kze Sc4+ei4uRc/fztXh1zOXu0bL0L0Mj968o4hgElD/Wjs+nYdJqbztVFEXGmPqR5eCkCEF auV/Xdy1olyOew9z5cAZmtQhn6lEBQagpm5bncPo8ufOEO7GM/vZS7Erwrz9vM9b8J1N 8VJQ== X-Forwarded-Encrypted: i=1; AHgh+RpW5QHg4NZ6eNhNZvNko/vASjZJv2LI26W9SfUpT5Ag2PcD3mcaToHzMSI9REVRGcJLhDni3KLLK3JwwvI=@vger.kernel.org X-Gm-Message-State: AFuF++mQCpAJ05KogXANl4Ge9fHQSJ+aq5V8nxG6Van/YznYz2phRYlz QDsP2+O3XXy0m3hRgU7Bovzk2SspKK34cy4zR7Umz+DVm2xqxSlXs22i X-Gm-Gg: AR+sD13H+3Q7Hgw7IHmdmrBk3kjgAMIrqrHG28MUgWAzhPDDcuBig2KW2eFxtUkSZ0+ xZYjPNYjcqhu0Wl6OSOtYLWwAK/7X0g1zBzaDEsszjPZXkCmoWj9TIonU35r4CYZ53HzQorya64 IURL8viqDbyvR05af9BGyH3XqHmJswcKvwlkDjYnmzULa/UdmIOWQyeddbPF5K/O8t++FUtkUMg t5C964rG0FmSrl1k75bLdJpNXcWmIqfLrs2hz5jIgtplzNrKwJ/VREjFkHRkjT1gdQ9sG0VCx4I lRaHzgFsT6QPd1gWWybUCjNVANcGvfzqZKWI3WiVhX4XhFYav6eH0/uat1cbK3Miyt80lkkoOj1 MjSN59XUXyL40dzsPbK/grtqSbw8LvOX1r+D9pvArMHc/Q3TUsIOk9UMEJl9WOhgveRkyBDyrsH mEOiy2q1IxX6InNDW/boCUSZ3MgjDYPVtB/8kFiXb4tEbaV2g2ajgitrf3AiG/4SUBxWypNM4VD EpPIJcwXDt1 X-Received: by 2002:a17:90b:1a85:b0:38e:250b:122f with SMTP id 98e67ed59e1d1-395c3aa9e26mr45720305a91.16.1787576731563; Mon, 24 Aug 2026 06:05:31 -0700 (PDT) Received: from localhost.localdomain ([152.59.223.115]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-327f92359c9sm26409711eec.27.2026.08.24.06.05.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 06:05:31 -0700 (PDT) From: Sreeshankar K To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, konradybcio@kernel.org, tglx@kernel.org, ulfh@kernel.org Cc: bmasney@redhat.com, radu@rendec.net, abel.vesa@oss.qualcomm.com, lpieralisi@kernel.org, taniya.das@oss.qualcomm.com, danila@mainlining.org, davidwronek@gmail.com, mani@kernel.org, robimarko@gmail.com, linux@gurudas.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K , Krzysztof Kozlowski Subject: [PATCH v5 03/13] dt-bindings: clock: Add SM7250 global clock controller Date: Mon, 24 Aug 2026 13:04:27 +0000 Message-ID: <20260824130437.2771-4-sreeshankar0910@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260824130437.2771-1-sreeshankar0910@gmail.com> References: <20260824130437.2771-1-sreeshankar0910@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree bindings for global clock controller on SM7250 SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Sreeshankar K --- .../bindings/clock/qcom,sm6375-gcc.yaml | 4 +- include/dt-bindings/clock/qcom,sm7250-gcc.h | 163 ++++++++++++++++++ 2 files changed, 166 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/clock/qcom,sm7250-gcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml b= /Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml index b4ad2ad14..39a2d2839 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml @@ -4,13 +4,14 @@ $id: http://devicetree.org/schemas/clock/qcom,sm6375-gcc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Qualcomm Global Clock & Reset Controller on SM6375 and SM7150 +title: Qualcomm Global Clock & Reset Controller on SM6375, SM7150 and SM72= 50 =20 maintainers: - Konrad Dybcio - Bjorn Andersson - Danila Tikhonov - David Wronek + - Sreeshankar K =20 description: | Qualcomm global clock control module provides the clocks, resets and pow= er @@ -26,6 +27,7 @@ properties: enum: - qcom,sm6375-gcc - qcom,sm7150-gcc + - qcom,sm7250-gcc =20 clocks: items: diff --git a/include/dt-bindings/clock/qcom,sm7250-gcc.h b/include/dt-bindi= ngs/clock/qcom,sm7250-gcc.h new file mode 100644 index 000000000..765fdc38f --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm7250-gcc.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2026, Sreeshankar K + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM7250_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SM7250_H + +/* GCC clocks */ +#define GPLL0 0 +#define GPLL0_OUT_EVEN 1 +#define GPLL6 2 +#define GPLL9 3 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 4 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 5 +#define GCC_BOOT_ROM_AHB_CLK 6 +#define GCC_CAMERA_AHB_CLK 7 +#define GCC_CAMERA_HF_AXI_CLK 8 +#define GCC_CAMERA_SF_AXI_CLK 9 +#define GCC_CAMERA_XO_CLK 10 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 11 +#define GCC_CPUSS_AHB_CLK 12 +#define GCC_CPUSS_AHB_CLK_SRC 13 +#define GCC_CPUSS_GNOC_CLK 14 +#define GCC_CPUSS_RBCPR_CLK 15 +#define GCC_DDRSS_GPU_AXI_CLK 16 +#define GCC_DISP_GPLL0_CLK_SRC 17 +#define GCC_DISP_AHB_CLK 18 +#define GCC_DISP_HF_AXI_CLK 19 +#define GCC_DISP_SF_AXI_CLK 20 +#define GCC_DISP_XO_CLK 21 +#define GCC_GP1_CLK 22 +#define GCC_GP1_CLK_SRC 23 +#define GCC_GP2_CLK 24 +#define GCC_GP2_CLK_SRC 25 +#define GCC_GP3_CLK 26 +#define GCC_GP3_CLK_SRC 27 +#define GCC_GPU_CFG_AHB_CLK 28 +#define GCC_GPU_GPLL0_CLK_SRC 29 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 30 +#define GCC_GPU_IREF_CLK 31 +#define GCC_GPU_MEMNOC_GFX_CLK 32 +#define GCC_GPU_SNOC_DVM_GFX_CLK 33 +#define GCC_NPU_AXI_CLK 34 +#define GCC_NPU_BWMON2_AXI_CLK 35 +#define GCC_NPU_BWMON_AXI_CLK 36 +#define GCC_NPU_BWMON_CFG_AHB_CLK 37 +#define GCC_NPU_CFG_AHB_CLK 38 +#define GCC_NPU_DMA_CLK 39 +#define GCC_NPU_GPLL0_CLK_SRC 40 +#define GCC_NPU_GPLL0_DIV_CLK_SRC 41 +#define GCC_PDM2_CLK 42 +#define GCC_PDM2_CLK_SRC 43 +#define GCC_PDM_AHB_CLK 44 +#define GCC_PDM_XO4_CLK 45 +#define GCC_PRNG_AHB_CLK 46 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 47 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 48 +#define GCC_QMIP_DISP_AHB_CLK 49 +#define GCC_QMIP_RT_DISP_AHB_CLK 50 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 51 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 52 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 53 +#define GCC_QUPV3_WRAP0_CORE_CLK 54 +#define GCC_QUPV3_WRAP0_S0_CLK 55 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 56 +#define GCC_QUPV3_WRAP0_S1_CLK 57 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 58 +#define GCC_QUPV3_WRAP0_S2_CLK 59 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 60 +#define GCC_QUPV3_WRAP0_S3_CLK 61 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 62 +#define GCC_QUPV3_WRAP0_S4_CLK 63 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 64 +#define GCC_QUPV3_WRAP0_S5_CLK 65 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 66 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 67 +#define GCC_QUPV3_WRAP1_CORE_CLK 68 +#define GCC_QUPV3_WRAP1_S0_CLK 69 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 70 +#define GCC_QUPV3_WRAP1_S1_CLK 71 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 72 +#define GCC_QUPV3_WRAP1_S2_CLK 73 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 74 +#define GCC_QUPV3_WRAP1_S3_CLK 75 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 76 +#define GCC_QUPV3_WRAP1_S4_CLK 77 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 78 +#define GCC_QUPV3_WRAP1_S5_CLK 79 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 80 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 81 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 82 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 83 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 84 +#define GCC_SDCC1_AHB_CLK 85 +#define GCC_SDCC1_APPS_CLK 86 +#define GCC_SDCC1_APPS_CLK_SRC 87 +#define GCC_SDCC1_ICE_CORE_CLK 88 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 89 +#define GCC_SDCC2_AHB_CLK 90 +#define GCC_SDCC2_APPS_CLK 91 +#define GCC_SDCC2_APPS_CLK_SRC 92 +#define GCC_SDCC4_AHB_CLK 93 +#define GCC_SDCC4_APPS_CLK 94 +#define GCC_SDCC4_APPS_CLK_SRC 95 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 96 +#define GCC_UFS_1X_CLKREF_CLK 97 +#define GCC_UFS_PHY_AHB_CLK 98 +#define GCC_UFS_PHY_AXI_CLK 99 +#define GCC_UFS_PHY_AXI_CLK_SRC 100 +#define GCC_UFS_PHY_ICE_CORE_CLK 101 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 102 +#define GCC_UFS_PHY_PHY_AUX_CLK 103 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 104 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 105 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 106 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 107 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 108 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 109 +#define GCC_USB30_PRIM_MASTER_CLK 110 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 111 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 112 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 113 +#define GCC_USB30_PRIM_SLEEP_CLK 114 +#define GCC_USB3_PRIM_CLKREF_CLK 115 +#define GCC_USB3_PRIM_PHY_AUX_CLK 116 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 117 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 118 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 119 +#define GCC_VIDEO_AHB_CLK 120 +#define GCC_VIDEO_AXI_CLK 121 +#define GCC_VIDEO_XO_CLK 122 + +/* GCC resets */ +#define GCC_DPM_BCR 0 +#define GCC_GPU_BCR 1 +#define GCC_MMSS_BCR 2 +#define GCC_NPU_BWMON_BCR 3 +#define GCC_NPU_BCR 4 +#define GCC_PDM_BCR 5 +#define GCC_PRNG_BCR 6 +#define GCC_QUPV3_WRAPPER_0_BCR 7 +#define GCC_QUPV3_WRAPPER_1_BCR 8 +#define GCC_QUSB2PHY_PRIM_BCR 9 +#define GCC_SDCC1_BCR 10 +#define GCC_SDCC2_BCR 11 +#define GCC_SDCC4_BCR 12 +#define GCC_UFS_PHY_BCR 13 +#define GCC_USB30_PRIM_BCR 14 +#define GCC_USB3_DP_PHY_PRIM_BCR 15 +#define GCC_USB3_PHY_PRIM_BCR 16 +#define GCC_USB3PHY_PHY_PRIM_BCR 17 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 18 + +/* GCC power domains */ +#define UFS_PHY_GDSC 0 +#define USB30_PRIM_GDSC 1 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 2 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 3 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 4 + +#endif --=20 2.43.0 From nobody Mon Sep 28 08:55:48 2026 Received: from mail-ot1-f54.google.com (mail-ot1-f54.google.com [209.85.210.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B822641F5E6 for ; Mon, 24 Aug 2026 13:05:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576749; cv=none; b=Kn3Kyp7IF5FM4y92lVK5dArgECNljmT2T6jDslSngpM6OV4/yIcaXL366m879olJSIMRwUfredwVPXjU54OXst+Yaey/a4lmVjYOonGKaFGckbQteQtY0ERmOrOK9Radczal0kj71dNSHzuNdNkRBl7k0VDsKdkJJNLr87WRYqE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576749; c=relaxed/simple; bh=OGg9K7faRft+CNQL7QfP/05Ttp4/9KlFqphfHKDaxsI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eSceLcWy5yh4HGGdqgqXmb4ofHUg9dBxgaiCHDZXx57zC4bm4okYzaNesI7jUn9VDSEsYPlckqI3th2s+b6wDu5C4eJvI3mw5RMnl1ta+KS8+Q4M1rEcGY78DMDSF8XNrxDXz+Zg0byHB8uP8S2XHpgjs1q4UfxitqF/q/korII= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=gMKccc+B; arc=none smtp.client-ip=209.85.210.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gMKccc+B" Received: by mail-ot1-f54.google.com with SMTP id 46e09a7af769-7eb34c17b96so3257613a34.2 for ; Mon, 24 Aug 2026 06:05:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787576744; x=1788181544; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=XxcP4K8E+VnNz/eBJ6uqz79ZxekgAVyGW8DORsWF5Hk=; b=gMKccc+BlXi0AISm/7BBJEy3U5gmHmN/H3P5ngkaxj7VxGJ9JKfyWqaECg+9xvF/lx UYEsq51Be0JIXPRjxanrWBmVWXsn1QH2+6z9HUvlhPsMb0GOiqWkzsooD4PvWI25NFrB jPjh6ii9LZ4okGQ0Vrj0OsJN2/5527u/tb1kGNCfnD0hZKpdnazAF+q4fwC29rSVysFo nGPs3JDUcGpgttlIXfyfaSThQT6EL9/0YoW8d83yRsMnYcEuGVuhF8GEHbDBrWnNI/aF FzjGN31eQtBhXXv+lpXER24dIrUAAmaqQtKvLuXntWcxmUgjWBWnGJKbYdNG4Gy9PixB Mqzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787576744; x=1788181544; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=XxcP4K8E+VnNz/eBJ6uqz79ZxekgAVyGW8DORsWF5Hk=; b=KyX6qnWzxJ5iiQ/jknG9G4UifElEdKk/HuF494v22xBPnFXaE6EBlReIZEVPbLylNz jKP1gVtni4Po/iR3HVNV1WCc6F3/TzqRbrHDn7jH5uM1K+eh3OA7to/3bp7aTp/u5+Hw 1GLJzYVSKHlIH6WiF2W89zbR4nfVwJi74TKOC5TtiFc0+i344mqMgI9X7wAy4SvquHO9 BUua7s5ypF/xlVzAphIkN5uJ8mb9UeoaZ2jUES2LMIo6dwUt53I6oUVBnAbEUfE/s+if l7mFFnsIKNkfZM9pDvhzlfNELTZgc1RPAnJLytUE5bqi/NadkoBAZjM5/kdmbYQWuTj/ JbKg== X-Forwarded-Encrypted: i=1; AHgh+RqoYQ0xwub9tyZGf1vaZDZEobZJUk1E5NyrL+MPIQhhdZQzBdyjixwdbBx1tJPUxprOiJUAsFJDCYFQPfE=@vger.kernel.org X-Gm-Message-State: AFuF++lCp9cQsRc/FDHVzGrRkrWjXt29MXV0In0Vi3HGxVTq11lizS+J TvYIJwV/7m3DCQxTWMj1Asqj+Tt4RQF2HLpuhlEptVLv4+TMTC+66HXP X-Gm-Gg: AR+sD13QDURZUOiIPl/Qn5y0GqTsYNqIDzbKLE69pnkPshWCNwqyXYZkrq2Li5qhcYU +q6F3Kh8313w+0mnlAwih2JMbG6kX5ZOzoa6WGSKJvLZ2ZmtBKCeDIpKxNXIExRN0+SDbTuzSfK H7TR8Q1+GMoYx9GVRvTINJEtk3s83WyWF2aqojELeYngqUfiVfb4g604QtHnLp3Z4N+szNPG4i9 ZUnf5DHxqCCknFrL9uVK27CT920Aun0ZzWBOoqIG9SLlfWoOMb0WUvwPj0170ziSPljO95NzCJN F72BTODzjT3KuXY1p0RsyxXmdrkasQ/OcoiaVIW9UpvSrhGOOfyx0B1UJNJQcMThhVCQesl5tdL lASQKyxTHKU12qc+eX0+ubWS9lerRU1dnsGEyq519ky1q31uk+quRhbRpZEekXzZMCv6pCCxe1M H403gfVRT7A4VLuD3/Et2auSoQHfJ6Gtb0eLAh9h9jlA== X-Received: by 2002:a05:6820:8107:b0:6a3:f597:7552 with SMTP id 006d021491bc7-6b16b5ba6b3mr16531309eaf.35.1787576743480; Mon, 24 Aug 2026 06:05:43 -0700 (PDT) Received: from localhost.localdomain ([152.59.223.115]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-327f92359c9sm26409711eec.27.2026.08.24.06.05.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 06:05:42 -0700 (PDT) From: Sreeshankar K To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, konradybcio@kernel.org, tglx@kernel.org, ulfh@kernel.org Cc: bmasney@redhat.com, radu@rendec.net, abel.vesa@oss.qualcomm.com, lpieralisi@kernel.org, taniya.das@oss.qualcomm.com, danila@mainlining.org, davidwronek@gmail.com, mani@kernel.org, robimarko@gmail.com, linux@gurudas.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K Subject: [PATCH v5 04/13] clk: qcom: Add Global Clock Controller (GCC) driver for SM7250 Date: Mon, 24 Aug 2026 13:04:28 +0000 Message-ID: <20260824130437.2771-5-sreeshankar0910@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260824130437.2771-1-sreeshankar0910@gmail.com> References: <20260824130437.2771-1-sreeshankar0910@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the global clock controller found on SM7250 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by: Sreeshankar K --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-sm7250.c | 2275 +++++++++++++++++++++++++++++++++ 3 files changed, 2285 insertions(+) create mode 100644 drivers/clk/qcom/gcc-sm7250.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 7d84c2f1d..532d8f002 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1416,6 +1416,15 @@ config SM_GCC_7150 Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, SD/UFS, PCIe etc. =20 +config SM_GCC_7250 + tristate "SM7250 Global Clock Controller" + depends on ARM64 || COMPILE_TEST + select QCOM_GDSC + help + Support for the global clock controller on SM7250 devices. + Say Y if you want to use peripheral devices such as UART, + SPI, I2C, USB, SD/UFS etc. + config SM_GCC_MILOS tristate "Milos Global Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 58f9a5eb6..18414089c 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -174,6 +174,7 @@ obj-$(CONFIG_SM_GCC_6125) +=3D gcc-sm6125.o obj-$(CONFIG_SM_GCC_6350) +=3D gcc-sm6350.o obj-$(CONFIG_SM_GCC_6375) +=3D gcc-sm6375.o obj-$(CONFIG_SM_GCC_7150) +=3D gcc-sm7150.o +obj-$(CONFIG_SM_GCC_7250) +=3D gcc-sm7250.o obj-$(CONFIG_SM_GCC_8150) +=3D gcc-sm8150.o obj-$(CONFIG_SM_GCC_8250) +=3D gcc-sm8250.o obj-$(CONFIG_SM_GCC_8350) +=3D gcc-sm8350.o diff --git a/drivers/clk/qcom/gcc-sm7250.c b/drivers/clk/qcom/gcc-sm7250.c new file mode 100644 index 000000000..bf75c8ec1 --- /dev/null +++ b/drivers/clk/qcom/gcc-sm7250.c @@ -0,0 +1,2275 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2026, Sreeshankar K + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_EVEN, + P_GPLL0_OUT_MAIN, + P_GPLL6_OUT_MAIN, + P_GPLL9_OUT_MAIN, + P_SLEEP_CLK, +}; + +static struct clk_alpha_pll gpll0 =3D { + .offset =3D 0x0, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpll0", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpll0_out_even[] =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll0_out_even =3D { + .offset =3D 0x0, + .post_div_shift =3D 8, + .post_div_table =3D post_div_table_gpll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_gpll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gpll0_out_even", + .parent_hws =3D (const struct clk_hw*[]){ + &gpll0.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_lucid_ops, + }, +}; + +static struct clk_alpha_pll gpll6 =3D { + .offset =3D 0x13000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(6), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpll6", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll9 =3D { + .offset =3D 0x1c000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(9), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpll9", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ops, + }, + }, +}; + +static const struct parent_map gcc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct clk_parent_data gcc_parent_data_0_ao[] =3D { + { .index =3D DT_BI_TCXO_AO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_SLEEP_CLK, 5 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data gcc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL6_OUT_MAIN, 2 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll6.clkr.hw }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL9_OUT_MAIN, 2 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll9.clkr.hw }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_5[] =3D { + { P_BI_TCXO, 0 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_5[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_cpuss_ahb_clk_src =3D { + .cmd_rcgr =3D 0x48010, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_cpuss_ahb_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_cpuss_ahb_clk_src", + .parent_data =3D gcc_parent_data_0_ao, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0_ao), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_gp1_clk_src =3D { + .cmd_rcgr =3D 0x64004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gp1_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_gp2_clk_src =3D { + .cmd_rcgr =3D 0x65004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gp2_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_gp3_clk_src =3D { + .cmd_rcgr =3D 0x66004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gp3_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] =3D { + F(9600000, P_BI_TCXO, 2, 0, 0), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pdm2_clk_src =3D { + .cmd_rcgr =3D 0x33010, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pdm2_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_pdm2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] =3D { + F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), + F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), + F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), + F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), + F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), + F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), + F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), + F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), + F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), + F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), + F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s0_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src =3D { + .cmd_rcgr =3D 0x17010, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s1_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src =3D { + .cmd_rcgr =3D 0x17140, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s1_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src =3D { + .cmd_rcgr =3D 0x17270, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s3_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src =3D { + .cmd_rcgr =3D 0x173a0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s4_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src =3D { + .cmd_rcgr =3D 0x174d0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s4_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s5_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src =3D { + .cmd_rcgr =3D 0x17600, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s5_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s0_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src =3D { + .cmd_rcgr =3D 0x18010, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s1_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src =3D { + .cmd_rcgr =3D 0x18140, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s1_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src =3D { + .cmd_rcgr =3D 0x18270, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s3_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src =3D { + .cmd_rcgr =3D 0x183a0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s4_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src =3D { + .cmd_rcgr =3D 0x184d0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s4_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s5_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src =3D { + .cmd_rcgr =3D 0x18600, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s5_clk_src_init, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] =3D { + F(144000, P_BI_TCXO, 16, 3, 25), + F(400000, P_BI_TCXO, 12, 1, 4), + F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3), + F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), + F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_apps_clk_src =3D { + .cmd_rcgr =3D 0x26024, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_sdcc1_apps_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc1_apps_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .flags =3D CLK_OPS_PARENT_ENABLE, + .ops =3D &clk_rcg2_floor_ops, + }, +}; + + +static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] =3D { + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src =3D { + .cmd_rcgr =3D 0x2600c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_sdcc1_ice_core_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc1_ice_core_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_OPS_PARENT_ENABLE, + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] =3D { + F(400000, P_BI_TCXO, 12, 1, 4), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc2_apps_clk_src =3D { + .cmd_rcgr =3D 0x1400c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_4, + .freq_tbl =3D ftbl_gcc_sdcc2_apps_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc2_apps_clk_src", + .parent_data =3D gcc_parent_data_4, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_4), + .flags =3D CLK_OPS_PARENT_ENABLE, + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] =3D { + F(400000, P_BI_TCXO, 12, 1, 4), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc4_apps_clk_src =3D { + .cmd_rcgr =3D 0x1600c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_sdcc4_apps_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc4_apps_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] =3D { + F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_axi_clk_src =3D { + .cmd_rcgr =3D 0x77024, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_ufs_phy_axi_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_axi_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] =3D { + F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), + F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src =3D { + .cmd_rcgr =3D 0x7706c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_ufs_phy_ice_core_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_ice_core_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x770a0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_ufs_phy_phy_aux_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] =3D { + F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), + F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src =3D { + .cmd_rcgr =3D 0x77084, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_ufs_phy_unipro_core_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_unipro_core_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] =3D { + F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), + F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb30_prim_master_clk_src =3D { + .cmd_rcgr =3D 0xf020, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_usb30_prim_master_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb30_prim_master_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src =3D { + .cmd_rcgr =3D 0xf038, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_ufs_phy_phy_aux_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb30_prim_mock_utmi_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0xf064, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_5, + .freq_tbl =3D ftbl_gcc_ufs_phy_phy_aux_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb3_prim_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_5, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_5), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_aggre_ufs_phy_axi_clk =3D { + .halt_reg =3D 0x770cc, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x770cc, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x770cc, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_aggre_ufs_phy_axi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_usb3_prim_axi_clk =3D { + .halt_reg =3D 0xf080, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xf080, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_aggre_usb3_prim_axi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk =3D { + .halt_reg =3D 0x38004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x38004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(10), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_boot_rom_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camera_hf_axi_clk =3D { + .halt_reg =3D 0xb028, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb028, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camera_hf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camera_sf_axi_clk =3D { + .halt_reg =3D 0xb02c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb02c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camera_sf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk =3D { + .halt_reg =3D 0xf07c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xf07c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_cfg_noc_usb3_prim_axi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cpuss_gnoc_clk =3D { + .halt_reg =3D 0x48064, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(29), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_cpuss_gnoc_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cpuss_rbcpr_clk =3D { + .halt_reg =3D 0x48004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x48004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_cpuss_rbcpr_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ddrss_gpu_axi_clk =3D { + .halt_reg =3D 0x71154, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x71154, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ddrss_gpu_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_gpll0_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(20), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_disp_gpll0_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gpll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_hf_axi_clk =3D { + .halt_reg =3D 0xb030, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb030, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_disp_hf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_sf_axi_clk =3D { + .halt_reg =3D 0xb034, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb034, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_disp_sf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk =3D { + .halt_reg =3D 0x64000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x64000, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gp1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_gp1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk =3D { + .halt_reg =3D 0x65000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x65000, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gp2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_gp2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp3_clk =3D { + .halt_reg =3D 0x66000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x66000, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gp3_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_gp3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(15), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gpu_gpll0_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gpll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_div_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(16), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gpu_gpll0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gpll0_out_even.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_iref_clk =3D { + .halt_reg =3D 0x8c014, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8c014, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gpu_iref_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_memnoc_gfx_clk =3D { + .halt_reg =3D 0x7100c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7100c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gpu_memnoc_gfx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk =3D { + .halt_reg =3D 0x71018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x71018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gpu_snoc_dvm_gfx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_axi_clk =3D { + .halt_reg =3D 0x4d008, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4d008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_npu_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_bwmon2_axi_clk =3D { + .halt_reg =3D 0x7000c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7000c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_npu_bwmon2_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_bwmon_axi_clk =3D { + .halt_reg =3D 0x70008, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x70008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_npu_bwmon_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_dma_clk =3D { + .halt_reg =3D 0x4d00c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4d00c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_npu_dma_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_gpll0_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(18), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_npu_gpll0_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gpll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_gpll0_div_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(19), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_npu_gpll0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gpll0_out_even.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm2_clk =3D { + .halt_reg =3D 0x3300c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3300c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_pdm2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_pdm2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_ahb_clk =3D { + .halt_reg =3D 0x33004, + .halt_check =3D BRANCH_HALT, + .hwcg_reg =3D 0x33004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x33004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_pdm_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_xo4_clk =3D { + .halt_reg =3D 0x33008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x33008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_pdm_xo4_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_prng_ahb_clk =3D { + .halt_reg =3D 0x34004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(13), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_prng_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_camera_nrt_ahb_clk =3D { + .halt_reg =3D 0xb018, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xb018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xb018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qmip_camera_nrt_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_camera_rt_ahb_clk =3D { + .halt_reg =3D 0xb01c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xb01c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xb01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qmip_camera_rt_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_disp_ahb_clk =3D { + .halt_reg =3D 0xb020, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xb020, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xb020, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qmip_disp_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_rt_disp_ahb_clk =3D { + .halt_reg =3D 0xb07c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xb07c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xb07c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qmip_rt_disp_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_video_cvp_ahb_clk =3D { + .halt_reg =3D 0xb010, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xb010, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xb010, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qmip_video_cvp_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_video_vcodec_ahb_clk =3D { + .halt_reg =3D 0xb014, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xb014, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xb014, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qmip_video_vcodec_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_2x_clk =3D { + .halt_reg =3D 0x23008, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(9), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_core_2x_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_clk =3D { + .halt_reg =3D 0x23000, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(8), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_core_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s0_clk =3D { + .halt_reg =3D 0x1700c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(10), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_s0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s1_clk =3D { + .halt_reg =3D 0x1713c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(11), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_s1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s2_clk =3D { + .halt_reg =3D 0x1726c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(12), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_s2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s3_clk =3D { + .halt_reg =3D 0x1739c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(13), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_s3_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s4_clk =3D { + .halt_reg =3D 0x174cc, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(14), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_s4_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s5_clk =3D { + .halt_reg =3D 0x175fc, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(15), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_s5_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_core_2x_clk =3D { + .halt_reg =3D 0x23140, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(18), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_core_2x_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_core_clk =3D { + .halt_reg =3D 0x23138, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(19), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_core_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s0_clk =3D { + .halt_reg =3D 0x1800c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(22), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_s0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s1_clk =3D { + .halt_reg =3D 0x1813c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(23), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_s1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s2_clk =3D { + .halt_reg =3D 0x1826c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(24), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_s2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s3_clk =3D { + .halt_reg =3D 0x1839c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(25), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_s3_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s4_clk =3D { + .halt_reg =3D 0x184cc, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(26), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_s4_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s5_clk =3D { + .halt_reg =3D 0x185fc, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(27), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_s5_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk =3D { + .halt_reg =3D 0x17004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(6), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap_0_m_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk =3D { + .halt_reg =3D 0x17008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x17008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(7), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap_0_s_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk =3D { + .halt_reg =3D 0x18004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(20), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap_1_m_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk =3D { + .halt_reg =3D 0x18008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x18008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(21), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap_1_s_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ahb_clk =3D { + .halt_reg =3D 0x26004, + .halt_check =3D BRANCH_HALT, + .hwcg_reg =3D 0x26004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x26004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc1_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_apps_clk =3D { + .halt_reg =3D 0x26008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x26008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc1_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_sdcc1_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ice_core_clk =3D { + .halt_reg =3D 0x2603c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2603c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc1_ice_core_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_sdcc1_ice_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_ahb_clk =3D { + .halt_reg =3D 0x14008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x14008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc2_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_apps_clk =3D { + .halt_reg =3D 0x14004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x14004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc2_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_sdcc2_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc4_ahb_clk =3D { + .halt_reg =3D 0x16008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x16008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc4_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc4_apps_clk =3D { + .halt_reg =3D 0x16004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x16004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc4_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_sdcc4_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_1x_clkref_clk =3D { + .halt_reg =3D 0x8c000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8c000, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_1x_clkref_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_ahb_clk =3D { + .halt_reg =3D 0x77018, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x77018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x77018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_axi_clk =3D { + .halt_reg =3D 0x77010, + .halt_check =3D BRANCH_HALT, + .hwcg_reg =3D 0x77010, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x77010, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_axi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_ice_core_clk =3D { + .halt_reg =3D 0x77064, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x77064, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x77064, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_ice_core_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_ice_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_phy_aux_clk =3D { + .halt_reg =3D 0x7709c, + .halt_check =3D BRANCH_HALT, + .hwcg_reg =3D 0x7709c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7709c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk =3D { + .halt_reg =3D 0x77020, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x77020, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_rx_symbol_0_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk =3D { + .halt_reg =3D 0x770b8, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x770b8, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_rx_symbol_1_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk =3D { + .halt_reg =3D 0x7701c, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x7701c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_tx_symbol_0_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_unipro_core_clk =3D { + .halt_reg =3D 0x7705c, + .halt_check =3D BRANCH_HALT, + .hwcg_reg =3D 0x7705c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7705c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_unipro_core_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_master_clk =3D { + .halt_reg =3D 0xf010, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xf010, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb30_prim_master_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_mock_utmi_clk =3D { + .halt_reg =3D 0xf01c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xf01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb30_prim_mock_utmi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_sleep_clk =3D { + .halt_reg =3D 0xf018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xf018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb30_prim_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_clkref_clk =3D { + .halt_reg =3D 0x8c010, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8c010, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb3_prim_clkref_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_aux_clk =3D { + .halt_reg =3D 0xf054, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xf054, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb3_prim_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_com_aux_clk =3D { + .halt_reg =3D 0xf058, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xf058, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb3_prim_phy_com_aux_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_pipe_clk =3D { + .halt_reg =3D 0xf05c, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0xf05c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb3_prim_phy_pipe_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_axi_clk =3D { + .halt_reg =3D 0xb080, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb080, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_video_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc ufs_phy_gdsc =3D { + .gdscr =3D 0x77004, + .pd =3D { + .name =3D "ufs_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc usb30_prim_gdsc =3D { + .gdscr =3D 0xf004, + .pd =3D { + .name =3D "usb30_prim_gdsc", + }, + .pwrsts =3D PWRSTS_RET_ON, +}; + +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc =3D { + .gdscr =3D 0x7d050, + .pd =3D { + .name =3D "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D VOTABLE, +}; + +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc =3D { + .gdscr =3D 0x7d058, + .pd =3D { + .name =3D "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D VOTABLE, +}; + +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc =3D { + .gdscr =3D 0x7d054, + .pd =3D { + .name =3D "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D VOTABLE, +}; + +static struct clk_regmap *gcc_sm7250_clocks[] =3D { + [GCC_AGGRE_UFS_PHY_AXI_CLK] =3D &gcc_aggre_ufs_phy_axi_clk.clkr, + [GCC_AGGRE_USB3_PRIM_AXI_CLK] =3D &gcc_aggre_usb3_prim_axi_clk.clkr, + [GCC_BOOT_ROM_AHB_CLK] =3D &gcc_boot_rom_ahb_clk.clkr, + [GCC_CAMERA_HF_AXI_CLK] =3D &gcc_camera_hf_axi_clk.clkr, + [GCC_CAMERA_SF_AXI_CLK] =3D &gcc_camera_sf_axi_clk.clkr, + [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] =3D &gcc_cfg_noc_usb3_prim_axi_clk.clkr, + [GCC_CPUSS_AHB_CLK_SRC] =3D &gcc_cpuss_ahb_clk_src.clkr, + [GCC_CPUSS_GNOC_CLK] =3D &gcc_cpuss_gnoc_clk.clkr, + [GCC_CPUSS_RBCPR_CLK] =3D &gcc_cpuss_rbcpr_clk.clkr, + [GCC_DDRSS_GPU_AXI_CLK] =3D &gcc_ddrss_gpu_axi_clk.clkr, + [GCC_DISP_GPLL0_CLK_SRC] =3D &gcc_disp_gpll0_clk_src.clkr, + [GCC_DISP_HF_AXI_CLK] =3D &gcc_disp_hf_axi_clk.clkr, + [GCC_DISP_SF_AXI_CLK] =3D &gcc_disp_sf_axi_clk.clkr, + [GCC_GP1_CLK] =3D &gcc_gp1_clk.clkr, + [GCC_GP1_CLK_SRC] =3D &gcc_gp1_clk_src.clkr, + [GCC_GP2_CLK] =3D &gcc_gp2_clk.clkr, + [GCC_GP2_CLK_SRC] =3D &gcc_gp2_clk_src.clkr, + [GCC_GP3_CLK] =3D &gcc_gp3_clk.clkr, + [GCC_GP3_CLK_SRC] =3D &gcc_gp3_clk_src.clkr, + [GCC_GPU_GPLL0_CLK_SRC] =3D &gcc_gpu_gpll0_clk_src.clkr, + [GCC_GPU_GPLL0_DIV_CLK_SRC] =3D &gcc_gpu_gpll0_div_clk_src.clkr, + [GCC_GPU_IREF_CLK] =3D &gcc_gpu_iref_clk.clkr, + [GCC_GPU_MEMNOC_GFX_CLK] =3D &gcc_gpu_memnoc_gfx_clk.clkr, + [GCC_GPU_SNOC_DVM_GFX_CLK] =3D &gcc_gpu_snoc_dvm_gfx_clk.clkr, + [GCC_NPU_AXI_CLK] =3D &gcc_npu_axi_clk.clkr, + [GCC_NPU_BWMON2_AXI_CLK] =3D &gcc_npu_bwmon2_axi_clk.clkr, + [GCC_NPU_BWMON_AXI_CLK] =3D &gcc_npu_bwmon_axi_clk.clkr, + [GCC_NPU_DMA_CLK] =3D &gcc_npu_dma_clk.clkr, + [GCC_NPU_GPLL0_CLK_SRC] =3D &gcc_npu_gpll0_clk_src.clkr, + [GCC_NPU_GPLL0_DIV_CLK_SRC] =3D &gcc_npu_gpll0_div_clk_src.clkr, + [GCC_PDM2_CLK] =3D &gcc_pdm2_clk.clkr, + [GCC_PDM2_CLK_SRC] =3D &gcc_pdm2_clk_src.clkr, + [GCC_PDM_AHB_CLK] =3D &gcc_pdm_ahb_clk.clkr, + [GCC_PDM_XO4_CLK] =3D &gcc_pdm_xo4_clk.clkr, + [GCC_PRNG_AHB_CLK] =3D &gcc_prng_ahb_clk.clkr, + [GCC_QMIP_CAMERA_NRT_AHB_CLK] =3D &gcc_qmip_camera_nrt_ahb_clk.clkr, + [GCC_QMIP_CAMERA_RT_AHB_CLK] =3D &gcc_qmip_camera_rt_ahb_clk.clkr, + [GCC_QMIP_DISP_AHB_CLK] =3D &gcc_qmip_disp_ahb_clk.clkr, + [GCC_QMIP_RT_DISP_AHB_CLK] =3D &gcc_qmip_rt_disp_ahb_clk.clkr, + [GCC_QMIP_VIDEO_CVP_AHB_CLK] =3D &gcc_qmip_video_cvp_ahb_clk.clkr, + [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] =3D &gcc_qmip_video_vcodec_ahb_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_2X_CLK] =3D &gcc_qupv3_wrap0_core_2x_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_CLK] =3D &gcc_qupv3_wrap0_core_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK] =3D &gcc_qupv3_wrap0_s0_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK_SRC] =3D &gcc_qupv3_wrap0_s0_clk_src.clkr, + [GCC_QUPV3_WRAP0_S1_CLK] =3D &gcc_qupv3_wrap0_s1_clk.clkr, + [GCC_QUPV3_WRAP0_S1_CLK_SRC] =3D &gcc_qupv3_wrap0_s1_clk_src.clkr, + [GCC_QUPV3_WRAP0_S2_CLK] =3D &gcc_qupv3_wrap0_s2_clk.clkr, + [GCC_QUPV3_WRAP0_S2_CLK_SRC] =3D &gcc_qupv3_wrap0_s2_clk_src.clkr, + [GCC_QUPV3_WRAP0_S3_CLK] =3D &gcc_qupv3_wrap0_s3_clk.clkr, + [GCC_QUPV3_WRAP0_S3_CLK_SRC] =3D &gcc_qupv3_wrap0_s3_clk_src.clkr, + [GCC_QUPV3_WRAP0_S4_CLK] =3D &gcc_qupv3_wrap0_s4_clk.clkr, + [GCC_QUPV3_WRAP0_S4_CLK_SRC] =3D &gcc_qupv3_wrap0_s4_clk_src.clkr, + [GCC_QUPV3_WRAP0_S5_CLK] =3D &gcc_qupv3_wrap0_s5_clk.clkr, + [GCC_QUPV3_WRAP0_S5_CLK_SRC] =3D &gcc_qupv3_wrap0_s5_clk_src.clkr, + [GCC_QUPV3_WRAP1_CORE_2X_CLK] =3D &gcc_qupv3_wrap1_core_2x_clk.clkr, + [GCC_QUPV3_WRAP1_CORE_CLK] =3D &gcc_qupv3_wrap1_core_clk.clkr, + [GCC_QUPV3_WRAP1_S0_CLK] =3D &gcc_qupv3_wrap1_s0_clk.clkr, + [GCC_QUPV3_WRAP1_S0_CLK_SRC] =3D &gcc_qupv3_wrap1_s0_clk_src.clkr, + [GCC_QUPV3_WRAP1_S1_CLK] =3D &gcc_qupv3_wrap1_s1_clk.clkr, + [GCC_QUPV3_WRAP1_S1_CLK_SRC] =3D &gcc_qupv3_wrap1_s1_clk_src.clkr, + [GCC_QUPV3_WRAP1_S2_CLK] =3D &gcc_qupv3_wrap1_s2_clk.clkr, + [GCC_QUPV3_WRAP1_S2_CLK_SRC] =3D &gcc_qupv3_wrap1_s2_clk_src.clkr, + [GCC_QUPV3_WRAP1_S3_CLK] =3D &gcc_qupv3_wrap1_s3_clk.clkr, + [GCC_QUPV3_WRAP1_S3_CLK_SRC] =3D &gcc_qupv3_wrap1_s3_clk_src.clkr, + [GCC_QUPV3_WRAP1_S4_CLK] =3D &gcc_qupv3_wrap1_s4_clk.clkr, + [GCC_QUPV3_WRAP1_S4_CLK_SRC] =3D &gcc_qupv3_wrap1_s4_clk_src.clkr, + [GCC_QUPV3_WRAP1_S5_CLK] =3D &gcc_qupv3_wrap1_s5_clk.clkr, + [GCC_QUPV3_WRAP1_S5_CLK_SRC] =3D &gcc_qupv3_wrap1_s5_clk_src.clkr, + [GCC_QUPV3_WRAP_0_M_AHB_CLK] =3D &gcc_qupv3_wrap_0_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_0_S_AHB_CLK] =3D &gcc_qupv3_wrap_0_s_ahb_clk.clkr, + [GCC_QUPV3_WRAP_1_M_AHB_CLK] =3D &gcc_qupv3_wrap_1_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_1_S_AHB_CLK] =3D &gcc_qupv3_wrap_1_s_ahb_clk.clkr, + [GCC_SDCC1_AHB_CLK] =3D &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] =3D &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC1_APPS_CLK_SRC] =3D &gcc_sdcc1_apps_clk_src.clkr, + [GCC_SDCC1_ICE_CORE_CLK] =3D &gcc_sdcc1_ice_core_clk.clkr, + [GCC_SDCC1_ICE_CORE_CLK_SRC] =3D &gcc_sdcc1_ice_core_clk_src.clkr, + [GCC_SDCC2_AHB_CLK] =3D &gcc_sdcc2_ahb_clk.clkr, + [GCC_SDCC2_APPS_CLK] =3D &gcc_sdcc2_apps_clk.clkr, + [GCC_SDCC2_APPS_CLK_SRC] =3D &gcc_sdcc2_apps_clk_src.clkr, + [GCC_SDCC4_AHB_CLK] =3D &gcc_sdcc4_ahb_clk.clkr, + [GCC_SDCC4_APPS_CLK] =3D &gcc_sdcc4_apps_clk.clkr, + [GCC_SDCC4_APPS_CLK_SRC] =3D &gcc_sdcc4_apps_clk_src.clkr, + [GCC_UFS_1X_CLKREF_CLK] =3D &gcc_ufs_1x_clkref_clk.clkr, + [GCC_UFS_PHY_AHB_CLK] =3D &gcc_ufs_phy_ahb_clk.clkr, + [GCC_UFS_PHY_AXI_CLK] =3D &gcc_ufs_phy_axi_clk.clkr, + [GCC_UFS_PHY_AXI_CLK_SRC] =3D &gcc_ufs_phy_axi_clk_src.clkr, + [GCC_UFS_PHY_ICE_CORE_CLK] =3D &gcc_ufs_phy_ice_core_clk.clkr, + [GCC_UFS_PHY_ICE_CORE_CLK_SRC] =3D &gcc_ufs_phy_ice_core_clk_src.clkr, + [GCC_UFS_PHY_PHY_AUX_CLK] =3D &gcc_ufs_phy_phy_aux_clk.clkr, + [GCC_UFS_PHY_PHY_AUX_CLK_SRC] =3D &gcc_ufs_phy_phy_aux_clk_src.clkr, + [GCC_UFS_PHY_RX_SYMBOL_0_CLK] =3D &gcc_ufs_phy_rx_symbol_0_clk.clkr, + [GCC_UFS_PHY_RX_SYMBOL_1_CLK] =3D &gcc_ufs_phy_rx_symbol_1_clk.clkr, + [GCC_UFS_PHY_TX_SYMBOL_0_CLK] =3D &gcc_ufs_phy_tx_symbol_0_clk.clkr, + [GCC_UFS_PHY_UNIPRO_CORE_CLK] =3D &gcc_ufs_phy_unipro_core_clk.clkr, + [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =3D + &gcc_ufs_phy_unipro_core_clk_src.clkr, + [GCC_USB30_PRIM_MASTER_CLK] =3D &gcc_usb30_prim_master_clk.clkr, + [GCC_USB30_PRIM_MASTER_CLK_SRC] =3D &gcc_usb30_prim_master_clk_src.clkr, + [GCC_USB30_PRIM_MOCK_UTMI_CLK] =3D &gcc_usb30_prim_mock_utmi_clk.clkr, + [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =3D + &gcc_usb30_prim_mock_utmi_clk_src.clkr, + [GCC_USB30_PRIM_SLEEP_CLK] =3D &gcc_usb30_prim_sleep_clk.clkr, + [GCC_USB3_PRIM_CLKREF_CLK] =3D &gcc_usb3_prim_clkref_clk.clkr, + [GCC_USB3_PRIM_PHY_AUX_CLK] =3D &gcc_usb3_prim_phy_aux_clk.clkr, + [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] =3D &gcc_usb3_prim_phy_aux_clk_src.clkr, + [GCC_USB3_PRIM_PHY_COM_AUX_CLK] =3D &gcc_usb3_prim_phy_com_aux_clk.clkr, + [GCC_USB3_PRIM_PHY_PIPE_CLK] =3D &gcc_usb3_prim_phy_pipe_clk.clkr, + [GCC_VIDEO_AXI_CLK] =3D &gcc_video_axi_clk.clkr, + [GPLL0] =3D &gpll0.clkr, + [GPLL0_OUT_EVEN] =3D &gpll0_out_even.clkr, + [GPLL6] =3D &gpll6.clkr, + [GPLL9] =3D &gpll9.clkr, +}; + +static struct gdsc *gcc_sm7250_gdscs[] =3D { + [UFS_PHY_GDSC] =3D &ufs_phy_gdsc, + [USB30_PRIM_GDSC] =3D &usb30_prim_gdsc, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =3D + &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] =3D + &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc, + [HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] =3D + &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc, +}; + +static const struct qcom_reset_map gcc_sm7250_resets[] =3D { + [GCC_DPM_BCR] =3D { 0x46000 }, + [GCC_GPU_BCR] =3D { 0x71000 }, + [GCC_MMSS_BCR] =3D { 0xb000 }, + [GCC_NPU_BWMON_BCR] =3D { 0x70000 }, + [GCC_NPU_BCR] =3D { 0x4d000 }, + [GCC_PDM_BCR] =3D { 0x33000 }, + [GCC_PRNG_BCR] =3D { 0x34000 }, + [GCC_QUPV3_WRAPPER_0_BCR] =3D { 0x17000 }, + [GCC_QUPV3_WRAPPER_1_BCR] =3D { 0x18000 }, + [GCC_QUSB2PHY_PRIM_BCR] =3D { 0x12000 }, + [GCC_SDCC1_BCR] =3D { 0x26000 }, + [GCC_SDCC2_BCR] =3D { 0x14000 }, + [GCC_SDCC4_BCR] =3D { 0x16000 }, + [GCC_UFS_PHY_BCR] =3D { 0x77000 }, + [GCC_USB30_PRIM_BCR] =3D { 0xf000 }, + [GCC_USB3_DP_PHY_PRIM_BCR] =3D { 0x50008 }, + [GCC_USB3_PHY_PRIM_BCR] =3D { 0x50000 }, + [GCC_USB3PHY_PHY_PRIM_BCR] =3D { 0x50004 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] =3D { 0x6a000 }, +}; + +static const u32 gcc_sm7250_critical_cbcrs[] =3D { + 0x0b004, /* GCC_VIDEO_AHB_CLK */ + 0x0b008, /* GCC_CAMERA_AHB_CLK */ + 0x0b00c, /* GCC_DISP_AHB_CLK */ + 0x0b038, /* GCC_VIDEO_XO_CLK */ + 0x0b03c, /* GCC_CAMERA_XO_CLK */ + 0x0b040, /* GCC_DISP_XO_CLK */ + 0x4d004, /* GCC_NPU_CFG_AHB_CLK */ + 0x52000, /* GCC_SYS_NOC_CPUSS_AHB_CLK */ + 0x70004, /* GCC_NPU_BWMON_CFG_AHB_CLK */ + 0x71004, /* GCC_GPU_CFG_AHB_CLK */ +}; + +static const struct clk_rcg_dfs_data gcc_sm7250_dfs_clocks[] =3D { + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), +}; + +static const struct regmap_config gcc_sm7250_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x9c100, + .fast_io =3D true, +}; + +static void gcc_sm7250_clk_regs_configure(struct regmap *regmap) +{ + /* + * Disable the GPLL0 active input to NPU and GPU + * via MISC registers. + */ + regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); + regmap_update_bits(regmap, 0x71028, 0x3, 0x3); + + /* + * Critical clocks that has same register with + * different mask + */ + regmap_update_bits(regmap, 0x52000, BIT(21), BIT(21)); /* GCC_CPUSS_AHB_C= LK */ +} + +static const struct qcom_cc_driver_data gcc_sm7250_driver_data =3D { + .clk_cbcrs =3D gcc_sm7250_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(gcc_sm7250_critical_cbcrs), + .dfs_rcgs =3D gcc_sm7250_dfs_clocks, + .num_dfs_rcgs =3D ARRAY_SIZE(gcc_sm7250_dfs_clocks), + .clk_regs_configure =3D gcc_sm7250_clk_regs_configure, +}; + +static const struct qcom_cc_desc gcc_sm7250_desc =3D { + .config =3D &gcc_sm7250_regmap_config, + .clks =3D gcc_sm7250_clocks, + .num_clks =3D ARRAY_SIZE(gcc_sm7250_clocks), + .resets =3D gcc_sm7250_resets, + .num_resets =3D ARRAY_SIZE(gcc_sm7250_resets), + .gdscs =3D gcc_sm7250_gdscs, + .num_gdscs =3D ARRAY_SIZE(gcc_sm7250_gdscs), + .use_rpm =3D true, + .driver_data =3D &gcc_sm7250_driver_data, +}; + +static const struct of_device_id gcc_sm7250_match_table[] =3D { + { .compatible =3D "qcom,sm7250-gcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_sm7250_match_table); + +static int gcc_sm7250_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gcc_sm7250_desc); +} + +static struct platform_driver gcc_sm7250_driver =3D { + .probe =3D gcc_sm7250_probe, + .driver =3D { + .name =3D "gcc-sm7250", + .of_match_table =3D gcc_sm7250_match_table, + }, +}; + +static int __init gcc_sm7250_init(void) +{ + return platform_driver_register(&gcc_sm7250_driver); +} +subsys_initcall(gcc_sm7250_init); + +static void __exit gcc_sm7250_exit(void) +{ + platform_driver_unregister(&gcc_sm7250_driver); +} +module_exit(gcc_sm7250_exit); + +MODULE_DESCRIPTION("QTI GCC SM7250 Driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Mon Sep 28 08:55:48 2026 Received: from mail-ot1-f51.google.com (mail-ot1-f51.google.com [209.85.210.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D36DC41E6D9 for ; Mon, 24 Aug 2026 13:05:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576758; cv=none; b=LTkOAZRd1uH20ohPczTyvx4BdQIunIaktfhVrwbqQsnLxBJ2i5FcCkS+F+umlqBybjU4u/r6M0W7f8OxCFntne3D6y85f3kROv1lGt+PqzAOMD5RjEQYUrT2nTP9ZqB5dcUSyVzkzMXcxcZ0B60dtjLohc/yyGT/s7T8cj6szMY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576758; c=relaxed/simple; bh=nZLd8IMnK+qlnesykBsMlKugO6FZefT2Z+rNkHuVLQw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aQB9qwtN1Mztx2VC4vFU92u579i0zLqm0mNhpdrYk0YPYAcrhjy0OFbUxbP9s8iC84kZo2maj1OMKLghEPOrcG6E+zCk/dDIAusXAMqMioZyvxfzso3kurRBi0HDtl3Nyr3mfi3DDDE5eymLrci/QpN0kn3Bg2vlk2jIDXOsUiI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=g0eK4lrn; arc=none smtp.client-ip=209.85.210.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="g0eK4lrn" Received: by mail-ot1-f51.google.com with SMTP id 46e09a7af769-7eb4d532e65so1872075a34.0 for ; Mon, 24 Aug 2026 06:05:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787576755; x=1788181555; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=3ckSz6fnME6Yn3dq6dpHlPLur72/KUgppRHgWdzen3s=; b=g0eK4lrnbTmgX0cFesKT00oS/Qd4bZWYYQDbTcTkFiuVgMrJWkg+EP1LF6vy9jm6fK WlniZLkTtHnrX+AltqnwsbGJ3kxtdkETHZjQIjckkru0ncVK+bnKUIt4pI5fUkmbGUwC vau/xUcSETA3LrDDkKYzGhpoYONLkaiwF6z4kp1bHUxr/gQ0Whgr8sDKWTvVbgmt0JJX BOClbS61zurkuYemuJIOqtGDh58j8dxl9XNLrqywu4L/kpytCWPlCthL+ocwmf5bWnLy xurJDp/KvE/gmAONkItd4+wibFKszjyvozzrlP8Y2SBwvhZEAfDvRiKCM6F5Qugly7ZD vQHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787576755; x=1788181555; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=3ckSz6fnME6Yn3dq6dpHlPLur72/KUgppRHgWdzen3s=; b=p7fjjH/G1EqhB/Hta/7ZhCt87yyPE8PqyG7MViXQf+BRWJF9NjalTBQBSstZROXl7j gO56zrVLeY0qjPRlT+0sD10lshSoDB1T05o9K7yl61cnGyyz2RBUlS/S6AztzAxqzGqC 2lNbup5BRM6ApeHRUvQjzt/VU6SR0V5T3YQpPRgaj9SvqWIUdc34r8ZZbAMxM12ESNWS Lk4HEkeJxY/V4gLbWL8K+Z05RZOcFrwimK5eSl+Zqmj/+f4Jw/Di7xx4ldRCS70zdERE 9KRg92BkNEbY6BK10/NmbOmWg5HmZDcO3/lI7kiwOtl5uzMpM5VBD/boJ9CRJD7HzQg5 Zh8w== X-Forwarded-Encrypted: i=1; AHgh+RoHnsEeMuHOtAp0iWS5XjdAl2msrB2EO4sZ3/2VheKreTm2jjUqTzxIviCGzls8EecadFR0vRXQL8LKw/U=@vger.kernel.org X-Gm-Message-State: AFuF++ke33yPoAgVHc34fD8rdm5vHgmQOyrmseZ7T+9swHe7iRiAjynJ YXQUoFYaImnAwNlqj6cEAOmgdJjxiG/6K6w4yLwvjaVjzc+2SE3Qq4UB X-Gm-Gg: AR+sD13UA87daIblip7Uno9/YPRnyXOdhq8aQ+MTNrJhAzmzKYbq56A7/tbHGuLvAsH py1xbdzF4166KCBW3jFcoRlqC2UWzDq0TaKGUdQvNiuO185na3mdKWTmE+nxZnSVaTMX3dgKT5f Fj9twqLkDv0q3cOBzc8DA4EPfup2v+End5iNyQO0zEHftdT1HIz1L34fDU0TXccKxyQqI57cQZv JQIKR3937Scqc6zO3x6o3/m5ENNUI9VThlv2kVwx16Z5GhJekrRejmtL3XHSauS7TCmBimdQhKq LA11OoCmmd1jGkfbZxcQ1YLesX5mmoMnFs46/5p0PGkMofABIBaOnYCS7DWmXUrKdXJySGW/8Y9 bgs8ZBNy67QvOKoYrMxskjN3YDLmyVRW/i0VJKCMEoqmZC+eXmye3O/ugSme1kgUEku2x1ROASv tp3ytboPIuftYZyHda+XxU/ewsdtGufCPfGEtVNJQlBy5TRecNycrkeEekHhQlXFnrSrL3+o5Z6 Pg+2w3TP+0A X-Received: by 2002:a05:6820:60b:b0:6b1:430f:1bd3 with SMTP id 006d021491bc7-6b16b1bef04mr16104300eaf.7.1787576753647; Mon, 24 Aug 2026 06:05:53 -0700 (PDT) Received: from localhost.localdomain ([152.59.223.115]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-327f92359c9sm26409711eec.27.2026.08.24.06.05.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 06:05:53 -0700 (PDT) From: Sreeshankar K To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, konradybcio@kernel.org, tglx@kernel.org, ulfh@kernel.org Cc: bmasney@redhat.com, radu@rendec.net, abel.vesa@oss.qualcomm.com, lpieralisi@kernel.org, taniya.das@oss.qualcomm.com, danila@mainlining.org, davidwronek@gmail.com, mani@kernel.org, robimarko@gmail.com, linux@gurudas.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K , Krzysztof Kozlowski Subject: [PATCH v5 05/13] dt-bindings: clock: qcom,rpmhcc: Document RPMHCC compatible for SM7250 Date: Mon, 24 Aug 2026 13:04:29 +0000 Message-ID: <20260824130437.2771-6-sreeshankar0910@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260824130437.2771-1-sreeshankar0910@gmail.com> References: <20260824130437.2771-1-sreeshankar0910@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document RPMHCC compatible for clock rpmh driver on Qualcomm SM7250 SoC. Acked-by: Krzysztof Kozlowski Signed-off-by: Sreeshankar K --- Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Doc= umentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index d344b3386..df9e37f90 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -38,6 +38,7 @@ properties: - qcom,sdx75-rpmh-clk - qcom,sm4450-rpmh-clk - qcom,sm6350-rpmh-clk + - qcom,sm7250-rpmh-clk - qcom,sm8150-rpmh-clk - qcom,sm8250-rpmh-clk - qcom,sm8350-rpmh-clk --=20 2.43.0 From nobody Mon Sep 28 08:55:48 2026 Received: from mail-oi1-f173.google.com (mail-oi1-f173.google.com [209.85.167.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A8A641F5DF for ; Mon, 24 Aug 2026 13:06:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576768; cv=none; b=Dldq8y0zFRosFrgQaPHw+wtfPcnjLlxAsHSJdKSeSgbyRWbqWzbgcMFtDZFmC6PNDBH+uZdLiuu442LYdoTj9xXZm9f3a5N+HkEgClrht8fCDJYwQwGz7vZipOFQ1bUEEYAz42uQm8VOtoOvMs2riN7ISd/WT850u7INGP4/OMc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576768; c=relaxed/simple; bh=GZpOUG3EXKO+QZK6dr4xOMkQjofCkY8f7CgoNTh+PnE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JmAWFdLFhXLc+Tza6rZWnOFTjo42yUmypPcNl1YmYH+a+A+4jO769g5mSdPZRxHmOZrxejWai/+p7hldva+tDFlpJfMYFspqF38CeP2iQF2cc6pTo1qlx3tUrDH7F6OY/1IvHBZr68Rz/EaLisx7j1zxBnCNvGYLtkiyvssn72w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=MN2SSsGA; arc=none smtp.client-ip=209.85.167.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="MN2SSsGA" Received: by mail-oi1-f173.google.com with SMTP id 5614622812f47-4b28df1f600so2707573b6e.2 for ; Mon, 24 Aug 2026 06:06:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787576765; x=1788181565; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=LgYAs0kfLDJbR97gF8B5vdewU847vzvHuLjE+TGmj38=; b=MN2SSsGAmFUOafXMXwNjHhgFVB74oZXbNt8iBYJY7K9XUt7C8fcPQtbSDFFlPvE/5P FrUHJHs/cZop1RMKz3FaPgoFF/VmGsV6zzVPh0Rvdhq6qRr7I9ZLLdcem22K96CVzsJR KYJLo+Vv2g+viIxPJgVkxqvakAf9jHZdiIFKJgWALsWBnQDgICzJT4iGXpCAmUG4SbZz r0g9skwZayV/oj1B1VdJDQvgTuYQGqPcEAInpVs5dgGYxV3mtstPJvuKJb7OB+6qJUIk PNHn21m9fcvzU01gpHTGYVVnkj87xY1rC3XnGWwIRQ203+/PPOyefzS7C3cwf+EsDqj+ WZBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787576765; x=1788181565; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=LgYAs0kfLDJbR97gF8B5vdewU847vzvHuLjE+TGmj38=; b=ga4tqxnYs9aipJ+/yn7Ugr+4snHfUOD4L1+I9xZf2Era4+Y3zfwhTEji5P9dMklPo4 EqwQecoKVxchBCFBC5jWoKVyOybQ2vdAr3JAUDaW/aCGWZTukCLilBdrlVSI35eVVmev OkFXYg+704CcRDEQM4I3HbuAOHZFdnt5w5a3VcxdlRQpKTwxeXNS2vjaZG/f50WUxh5A FDSIQ9WR3rr3LgbANBnrjpM6bSGVQ3Vuwdu7YWQTK6V+W3QOroUzXYXh2wpiDLS2lnnC BFpph2m+xDtrzROh5ihJKnhi+70PPrCQKVPXtMBu6+o6+/sIooFjBnGCH1VHsnbR/f2i bSpw== X-Forwarded-Encrypted: i=1; AHgh+Rrc/Be3voW916C2C07vXPUGnC+bnurvKOLCsQd3EHb/xfyoYNOM+jF76DUrZF+kV8qw/QwgKLHkzdQ+8JA=@vger.kernel.org X-Gm-Message-State: AFuF++nvS6uOWaNM2RVi25CuY+CasnxGSa+8FNu6Ram4OCPd3eub510Z 7MGf0CGX679CttadCnRRvWLQ55TlWdcXWp6MIX0oyAQw3sLNfOCX3l33 X-Gm-Gg: AR+sD10T9R95vwEsWligXvqEEAz3ZzV2l6CmjfWhOVumhisvNw5ZQV5D3uYC/xRPPrV s/q7xK+2EPPgTcKYzBoDreun7+sNPVFKKRXIsH2k8ffskYZeg+DohYXq9WM/ikjm2Y4Mogbqh+t u7Aae5R9YNDaDbddEVF75aoH9J7ww+9tnEYPNS1qKq0Ir1iIgvY+VHQuReU1dWkC+chB6F6fA+m YZdjagtWspphAawQeRCbYtIGz+jAkfTq2vu4yWjfMssIyc6aOTFLii5sl8zFcvqay50fNwpqWt5 axEn/dyyKIwvQzUzfgCgJElvn/y+E8fDC3olLYs0PKpsdr1BdiojJ8ahtDP9D9xCFKu1Ro3aCsA 6rNrJAcswMpNvhTbiYxGhpcaWTQc99qFaASn9hNATTBca33q+xlKq8fbheMKTqEuFQO+MK5Omri XasouB9xWA8yIbrvWec8xPJjLi56IPrD8VwLjkxJDrZwf6AOuzb4E2HihA1hUmcxTg5ibQQb0mA E7XdPptchZK X-Received: by 2002:a05:6820:1c99:b0:6b1:5c8b:c0b9 with SMTP id 006d021491bc7-6b15c8bd304mr19796060eaf.3.1787576765018; Mon, 24 Aug 2026 06:06:05 -0700 (PDT) Received: from localhost.localdomain ([152.59.223.115]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-327f92359c9sm26409711eec.27.2026.08.24.06.05.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 06:06:04 -0700 (PDT) From: Sreeshankar K To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, konradybcio@kernel.org, tglx@kernel.org, ulfh@kernel.org Cc: bmasney@redhat.com, radu@rendec.net, abel.vesa@oss.qualcomm.com, lpieralisi@kernel.org, taniya.das@oss.qualcomm.com, danila@mainlining.org, davidwronek@gmail.com, mani@kernel.org, robimarko@gmail.com, linux@gurudas.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K , Dmitry Baryshkov , Konrad Dybcio Subject: [PATCH v5 06/13] clk: qcom: rpmh: Add SM7250 rpmh clocks Date: Mon, 24 Aug 2026 13:04:30 +0000 Message-ID: <20260824130437.2771-7-sreeshankar0910@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260824130437.2771-1-sreeshankar0910@gmail.com> References: <20260824130437.2771-1-sreeshankar0910@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the RPMH clocks present in SM7250 SoC. Reviewed-by: Dmitry Baryshkov Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Signed-off-by: Sreeshankar K --- drivers/clk/qcom/clk-rpmh.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 6367b2a5a..f4cafa274 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -1011,6 +1011,29 @@ static const struct clk_rpmh_desc clk_rpmh_hawi =3D { .num_clks =3D ARRAY_SIZE(hawi_rpmh_clocks), }; =20 +static struct clk_hw *sm7250_rpmh_clocks[] =3D { + [RPMH_CXO_CLK] =3D &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] =3D &clk_rpmh_bi_tcxo_div2_ao.hw, + [RPMH_LN_BB_CLK2] =3D &clk_rpmh_ln_bb_clk2_a2.hw, + [RPMH_LN_BB_CLK2_A] =3D &clk_rpmh_ln_bb_clk2_a2_ao.hw, + [RPMH_LN_BB_CLK3] =3D &clk_rpmh_ln_bb_clk3_a2.hw, + [RPMH_LN_BB_CLK3_A] =3D &clk_rpmh_ln_bb_clk3_a2_ao.hw, + [RPMH_RF_CLK1] =3D &clk_rpmh_rf_clk1_d.hw, + [RPMH_RF_CLK1_A] =3D &clk_rpmh_rf_clk1_d_ao.hw, + [RPMH_RF_CLK2] =3D &clk_rpmh_rf_clk2_d.hw, + [RPMH_RF_CLK2_A] =3D &clk_rpmh_rf_clk2_d_ao.hw, + [RPMH_RF_CLK3] =3D &clk_rpmh_rf_clk3_d.hw, + [RPMH_RF_CLK3_A] =3D &clk_rpmh_rf_clk3_d_ao.hw, + [RPMH_RF_CLK4] =3D &clk_rpmh_rf_clk4_d.hw, + [RPMH_RF_CLK4_A] =3D &clk_rpmh_rf_clk4_d_ao.hw, + [RPMH_IPA_CLK] =3D &clk_rpmh_ipa.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_sm7250 =3D { + .clks =3D sm7250_rpmh_clocks, + .num_clks =3D ARRAY_SIZE(sm7250_rpmh_clocks), +}; + static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, void *data) { @@ -1120,6 +1143,7 @@ static const struct of_device_id clk_rpmh_match_table= [] =3D { { .compatible =3D "qcom,sdx75-rpmh-clk", .data =3D &clk_rpmh_sdx75}, { .compatible =3D "qcom,sm4450-rpmh-clk", .data =3D &clk_rpmh_sm4450}, { .compatible =3D "qcom,sm6350-rpmh-clk", .data =3D &clk_rpmh_sm6350}, + { .compatible =3D "qcom,sm7250-rpmh-clk", .data =3D &clk_rpmh_sm7250}, { .compatible =3D "qcom,sm8150-rpmh-clk", .data =3D &clk_rpmh_sm8150}, { .compatible =3D "qcom,sm8250-rpmh-clk", .data =3D &clk_rpmh_sm8250}, { .compatible =3D "qcom,sm8350-rpmh-clk", .data =3D &clk_rpmh_sm8350}, --=20 2.43.0 From nobody Mon Sep 28 08:55:48 2026 Received: from mail-pj1-f52.google.com (mail-pj1-f52.google.com [209.85.216.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBF8642047A for ; Mon, 24 Aug 2026 13:06:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576777; cv=none; b=a2bBEsm5/ruawu+FXUlGb1N/vG8VbHaByhPX4Pz/xKfhApWa8T63dp3mjzGMBip9y5/PiG7zzLCHOvCcOhhIBZBsiK6Dn4cfXjLeVqN7FkEyhZHVhbczZ2TkaEhqVczqEdVEWAPm7/ryEg6SA9CUPXHMvojsiPNiTHPTF7b7/3o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576777; c=relaxed/simple; bh=jKh+XPUoJmr7fIpNbx8/2EaPd/67MsZW4ebNDZ/8MPE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PkGPiT0foso8mnzd4lzQV696GcuDUH/tAKhb5EdjcEpbpyGz22U5fdDe8bixg7eRBp1jh/h0pG8nklT1MuHmG2+d1qSa65D288ArmoqdAh6LdFnv8z2XxTapvW4scwbDh4IrCilRrAWrBIGYXIZEX/nW6T5kvVAmy6GhrSN0D/A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=EZUZvbRo; arc=none smtp.client-ip=209.85.216.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="EZUZvbRo" Received: by mail-pj1-f52.google.com with SMTP id 98e67ed59e1d1-395cf2535acso2964457a91.1 for ; Mon, 24 Aug 2026 06:06:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787576775; x=1788181575; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=QQnqfdvjWzHpIFqKpmfnZN4AvVDc8IQ+C2JI25EK8GQ=; b=EZUZvbRou2Xr7NLyyOa9VczdO3YZSlEpiVXkPK6fzNAWVUvvpEoUZvFTezWV5v7ktJ jFoHb/9DORa8sTyg+yTNAoaXxgugfUDmdNCji3q8lMjHUjhR5C3Ky84112zZ9Sd0BSG2 iaAwT6u6mXQVshuR2/o6QIpM8gRpoQThnOmtFQqnj5+0ztiSW36YggHoY1IFmsIZ2f3a RbnIC8qaw0p/pIi9loXDuIMKkLdVKIHqg06jXLEYg8+NsDI9TWDMxyPVTjGNJeLhL/si jxnyrtQkk+whJTMP3lnQ8/E0cB+fECCNSgKSA3y6hSXx8yFq+xEA01hu/Q6gGWYowr3v AiDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787576775; x=1788181575; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=QQnqfdvjWzHpIFqKpmfnZN4AvVDc8IQ+C2JI25EK8GQ=; b=Y8qT+UeD5qu2LxO0ZWx/w3y0n+zUZseq33sQCU7Rn/Gev6c3J1ST8N4M32acsjL7lJ xq7vqzf6ngVtbk/tX+s0Ack42Z6neAa8rFlPz7FBCPfjEht9Z4PpOldq6FPmdGHkhOdi Kilxs41/pTbSFuBTpfjNNmeavg3yymrjiWHFnhOmcKkjdhgFX9bduXH25+XkmwNAsbR/ R+47s3wwosKeDIuF7g0Yf+BEsCpnhhJfQrn0nc0wSYDw3ZHF8fP3Qe4p80SgVCHbOgjq kYQVp0zyT3F3OzUsFiz+2uZ1d9RIAxZY9aQvCy4bJz2uuUzZiCScNzA3Oxo0c9oxbURa 1+1g== X-Forwarded-Encrypted: i=1; AHgh+RriizSvbYKurQHMyHwE8SsquxNSS8RUEXjPVx1lk3AGWzbb+uEQIEE/uNBmAmgBNFSiXK1f5vqQc3AMzdA=@vger.kernel.org X-Gm-Message-State: AFuF++ma7Xh/PP22S/fI1BqG7UFeODJIJfkm0qNYDLV68MbbvTW3bxDd L73MqN0QPZVRTS/pOLljitW0CWMFaG8PLT3lUnUpZADsV6sQqu7vwZ6f X-Gm-Gg: AR+sD13/N7v/IOaSnojWvYfwRiMOcFejKnMI/0EdomJw2wjgJHmjh5zYXdXUUMBAxqX bszS2wvMKk9u5fOl88XWtOIp19EXgh2sBJ9hLcXeE3AxeZ64Dc+w+2VK9WbzIMW+NQW/wuVmEhh TcUXuXrlMVfS5wJctvHA8sbNTIfPbUUMYL6Ml6WTIlQym6BgqC3DE05Av3W8kEVVxedG0BFFYGt lCsgTrQpbwdLOCWUtWpSCFBIRXZ//IJmXW1m3RVeJtgfeLDSzGeQ/kNGtTE++2kEtD8Kq7iSde+ w471lJSVs/zq+RBwlPdSB5UrVj39Z6qYz5dnTRb6CgVKr8r8B35JmuMbv6R8qa6YMC7ndczBc1v HyzaUFbRrWada+DQNM1AEYQSUDbnWwQ0Ub84qP+Xd1kl1ju39F7O9nM8NjDVBsC53pqHX6xS2kY HjIodRQNtm1oPHHApuhY8mhAOy7H0MkoEkvp6hc8gqbsr8k7upZFM7zDr8eC8XnoU43fL3sSLO8 3H+1OnsOKzJ X-Received: by 2002:a17:90b:524a:b0:380:86d8:8162 with SMTP id 98e67ed59e1d1-395a07022b9mr41041319a91.18.1787576774842; Mon, 24 Aug 2026 06:06:14 -0700 (PDT) Received: from localhost.localdomain ([152.59.223.115]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-327f92359c9sm26409711eec.27.2026.08.24.06.06.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 06:06:14 -0700 (PDT) From: Sreeshankar K To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, konradybcio@kernel.org, tglx@kernel.org, ulfh@kernel.org Cc: bmasney@redhat.com, radu@rendec.net, abel.vesa@oss.qualcomm.com, lpieralisi@kernel.org, taniya.das@oss.qualcomm.com, danila@mainlining.org, davidwronek@gmail.com, mani@kernel.org, robimarko@gmail.com, linux@gurudas.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K Subject: [PATCH v5 07/13] dt-bindings: power: qcom,rpmhpd: Document RPMh power domain for SM7250 Date: Mon, 24 Aug 2026 13:04:31 +0000 Message-ID: <20260824130437.2771-8-sreeshankar0910@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260824130437.2771-1-sreeshankar0910@gmail.com> References: <20260824130437.2771-1-sreeshankar0910@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the RPMh power domain for SM7250 SoC. Signed-off-by: Sreeshankar K --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Docu= mentation/devicetree/bindings/power/qcom,rpmpd.yaml index 0a45e1f55..e08441915 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -63,6 +63,7 @@ properties: - qcom,sm6350-rpmhpd - qcom,sm6375-rpmpd - qcom,sm7150-rpmhpd + - qcom,sm7250-rpmhpd - qcom,sm8150-rpmhpd - qcom,sm8250-rpmhpd - qcom,sm8350-rpmhpd --=20 2.43.0 From nobody Mon Sep 28 08:55:48 2026 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBD2A420468 for ; Mon, 24 Aug 2026 13:06:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576787; cv=none; b=OAMZ8bB8K0OKP2w0igEBMiW43MNxj/SRyY6OUcTSHGxlXLMTNFQaumMeTaM0EFacGuf16Ev85DQ0UdINjdfM6uPhoT1H6CskiveuFbz/9WuTrFXQdsPGZNKoCLCaHFlrFYklx2DXb0GRmD9Lyvww8izEP3x8PeHczNvQWAaxU4o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576787; c=relaxed/simple; bh=9Rs+ll41NKEFlOm3FoL6ceFLLpdJXgRekcTbFNLh3NY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XAn8MfaG+WmPRkqpUpA6hewbYz0hTbXBvZkqbmKsyNqs3qlhZw8I/o4yqj1/SYVdwnShIeKun6P9LfId5z0UEXn7i3SHQWp/AHOmKNY7RLmdbANf1e4oK24ebN8r6U71pbIWQTf00a9UELClU6VNh7qvnjZ1C2kUFIWefD2yI24= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=qum1La/7; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="qum1La/7" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-2cace91f112so39530785ad.0 for ; Mon, 24 Aug 2026 06:06:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787576785; x=1788181585; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=leXltbiOaTHy4a8AzjEvY38i+F2Jzsbl2HWjNkp0y+k=; b=qum1La/7h9/4tapE+kuH/r/Yo0F1th/ZMtHB6IzU7oEXgLm+xDhlmHShgbzIm+hjV0 SBCSEhtR7mvxnJMCtDq6d+QVbnmoIKUyCbiu/NZC26DvBZThkqM5KEUaRQ3RFo74PG3H 7jUJxtxYdbTjqc+GyKI6ve9bZd68/OYLm3QwSnlW1WO6tVFUko4i7PNG+kjcqUW5EVYJ Y9/Ck/rZqxwPc4vybvAGG5UCMUahIh05QDbTwFjwgL6Idlf769q66eKg/ZsUjhnkca/8 tFGDnZ26H/MxzoaigCUAj/VxtPEQbnPzFh0DW0mf8XesmMbPp44x2Rxb3QFyC/52wLZP cU5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787576785; x=1788181585; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=leXltbiOaTHy4a8AzjEvY38i+F2Jzsbl2HWjNkp0y+k=; b=aK3R1hnwiw1hpI006SLVxHa+3Ez35Ls8UbCJt68Z+FuC7qeuKUDBy9gmQJXgl88hTH TmX3uLsXMH9PIlMeZMl/5XSUPHiRnw8PRdKoavxzWzTgxtv7BMaDt+JwCqcquKbcE6Cd ubHQZ4U9vwXygijPPVKXxOu8aphKoIOaf83xVIX9eBZA4KhrNekUGFxfv5irwiv3IDg/ HoLaq0aPUFZzmCdALEXsiqzsF8E7nmhH8kh0ZsAl7fytk857RkfSrVFuSOiFHYSSEtWx 8Fq1K/xVRJlqqhshvGIQ67CB9A3+e2JTfPVe0pnqMEWWysRxbtGa06UErO6PujX8SASv 2nlg== X-Forwarded-Encrypted: i=1; AHgh+Rp4PFfTNDpgJW2gTDmPEVK6vixDu+NWcMAvx/TvXrziPkju3w8Wqi+/1NyIMX7wi88EPzknsUD4FD8n8U4=@vger.kernel.org X-Gm-Message-State: AFuF++m5tRHu0A2ehQnfP4jPJOaCEzu0ms57t0+tY1RkX6Ri2IiJB2v4 mP5NS6QonasWRoJKcsEBkBxGX6j39UlSMV7VL6rxN5tZARh0KYYIps4S X-Gm-Gg: AR+sD12HCBLlcJHaHZk5h6AcGVqL3HSmtw8dupG+vePzuKDNzyyV95IQ+0d0JznFTF5 mN7X0TRCJhKoPmflFanyfiX5r+92RgN7mUGdyFFdBH2M4Y2sx+NcnNuM7atZGUbwTmTJJPOpRLg v8EpR/HDoJ/aRB0ALkZlXa1byap2g8uRjBSltdnsmA15C7QS7ONGSJTF02RzyessxAXNP562D3W 57dnP9b2wKuJx1UFXYeCfXs8nb9R2NjBpxGs/pKaQ8zX6tBWyo6HBKOXvc+AFLnb9OVR81bqTrW ColfI9BoTkuvL/1nPwMqZfm+LtmYD77csF1uJTcCa4PZGq+G3YEcm8LJO9NwXqDa/avWE9vB7+Z AHebh7qNcWFDcyQ3EOyQINkw26UVeFrwGbkid/TkpV8eW38oLuoi6fMovJN6vyipL84ZY6js7/Q BTxM7L+2VE+V+PLmzqRO9q1F0C9P4QFNksZhB/6Jl5q5GkV8+fMnBXkdssnGnc7SxC2lguc+pDw 39h+GSbjRd/ X-Received: by 2002:a17:903:2ec8:b0:2ca:e62c:9e96 with SMTP id d9443c01a7336-2d670b9ba58mr347409935ad.5.1787576785252; Mon, 24 Aug 2026 06:06:25 -0700 (PDT) Received: from localhost.localdomain ([152.59.223.115]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-327f92359c9sm26409711eec.27.2026.08.24.06.06.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 06:06:24 -0700 (PDT) From: Sreeshankar K To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, konradybcio@kernel.org, tglx@kernel.org, ulfh@kernel.org Cc: bmasney@redhat.com, radu@rendec.net, abel.vesa@oss.qualcomm.com, lpieralisi@kernel.org, taniya.das@oss.qualcomm.com, danila@mainlining.org, davidwronek@gmail.com, mani@kernel.org, robimarko@gmail.com, linux@gurudas.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K , Konrad Dybcio Subject: [PATCH v5 08/13] pmdomain: qcom: rpmhpd: Add RPMh power domains for SM7250 Date: Mon, 24 Aug 2026 13:04:32 +0000 Message-ID: <20260824130437.2771-9-sreeshankar0910@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260824130437.2771-1-sreeshankar0910@gmail.com> References: <20260824130437.2771-1-sreeshankar0910@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add RPMh power domains for SM7250 SoC. Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Signed-off-by: Sreeshankar K --- drivers/pmdomain/qcom/rpmhpd.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/pmdomain/qcom/rpmhpd.c b/drivers/pmdomain/qcom/rpmhpd.c index 96e4bd2f5..70d0ff5cc 100644 --- a/drivers/pmdomain/qcom/rpmhpd.c +++ b/drivers/pmdomain/qcom/rpmhpd.c @@ -490,6 +490,24 @@ static const struct rpmhpd_desc sm7150_desc =3D { .num_pds =3D ARRAY_SIZE(sm7150_rpmhpds), }; =20 +/* SM7250 RPMH powerdomains */ +static struct rpmhpd *sm7250_rpmhpds[] =3D { + [RPMHPD_CX] =3D &cx_w_mx_parent, + [RPMHPD_CX_AO] =3D &cx_ao_w_mx_parent, + [RPMHPD_EBI] =3D &ebi, + [RPMHPD_GFX] =3D &gfx, + [RPMHPD_LCX] =3D &lcx, + [RPMHPD_LMX] =3D &lmx, + [RPMHPD_MSS] =3D &mss, + [RPMHPD_MX] =3D &mx, + [RPMHPD_MX_AO] =3D &mx_ao, +}; + +static const struct rpmhpd_desc sm7250_desc =3D { + .rpmhpds =3D sm7250_rpmhpds, + .num_pds =3D ARRAY_SIZE(sm7250_rpmhpds), +}; + /* SM8150 RPMH powerdomains */ static struct rpmhpd *sm8150_rpmhpds[] =3D { [SM8150_CX] =3D &cx_w_mx_parent, @@ -910,6 +928,7 @@ static const struct of_device_id rpmhpd_match_table[] = =3D { { .compatible =3D "qcom,sm4450-rpmhpd", .data =3D &sm4450_desc }, { .compatible =3D "qcom,sm6350-rpmhpd", .data =3D &sm6350_desc }, { .compatible =3D "qcom,sm7150-rpmhpd", .data =3D &sm7150_desc }, + { .compatible =3D "qcom,sm7250-rpmhpd", .data =3D &sm7250_desc }, { .compatible =3D "qcom,sm8150-rpmhpd", .data =3D &sm8150_desc }, { .compatible =3D "qcom,sm8250-rpmhpd", .data =3D &sm8250_desc }, { .compatible =3D "qcom,sm8350-rpmhpd", .data =3D &sm8350_desc }, --=20 2.43.0 From nobody Mon Sep 28 08:55:48 2026 Received: from mail-pg1-f173.google.com (mail-pg1-f173.google.com [209.85.215.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45D8141F5DF for ; Mon, 24 Aug 2026 13:06:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576798; cv=none; b=YQKXvYYEe6GhfLZrdUfW9dSoutd9o9Dtam+WYA8MqRRJ12fOFxCR/Hlpk6hLh7z/IrgZnzVKfj9W2eKyLQxb7ATzeHY26vozdOaCmeK4Z4In2VdgyMPve0gBLp6zmRs8tShPIbRgBP+RBwEiRte3Tdj7/Cp1+Y8MU8rq2mie2M8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576798; c=relaxed/simple; bh=Unl00eAfFi9To3aFPzg9GlTfdXTVfm9Q5VowGJ6jvsU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=j73ShCkglIUdotw0SJL5lwmW9xRfkfaZZWAmQh1zDLAmwGO9zjCVC8I5ZqFXMR+giXKSdFja12VWmcJN0EBUQruRc093qDiLZac9yRfL/BtcKVrXSqyJIA2k8d4yV9EyiYN4xvl3gA4a3Y0R8s9Ns0rL/uA7Swkbwcyp8XQZUSo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=BOn8zvgx; arc=none smtp.client-ip=209.85.215.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="BOn8zvgx" Received: by mail-pg1-f173.google.com with SMTP id 41be03b00d2f7-cbe6295f05bso3023537a12.1 for ; Mon, 24 Aug 2026 06:06:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787576795; x=1788181595; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=iR99/HU1Sv6a6aJcZCVFplbKZQ+GSq64X/oQnCgwbZk=; b=BOn8zvgx8OR00F/IRRPkOS6UfJx55Fwk5teZsIj/GZyVjxbqpjlwH9f1bUTGpVhTPM PistBs8F0beWFzNyfvjNIFCRbVuPBF2VL6FvCq+OkTatN/VW0j0g3TMzyjGGVPRMKDSi QBR9V910IwdUQxze+YHHzgvooFmNWU0IKMrl2DQBY//EGA9fr4KBpSER8C0krBkHKBbz 5r853GF41gRmBQG6mzSkO8+I7NQerUYB3kqaIl7b94TrCP25hWt+H24jEuCMy5mDSFPP wjZYgSCnELUXOZTUKQ/jAV/PeWsBEdqC+IgofyVCDBI35ziTx93Xmg8La5FXrI+Omhhj uyPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787576795; x=1788181595; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=iR99/HU1Sv6a6aJcZCVFplbKZQ+GSq64X/oQnCgwbZk=; b=geDtLOR+9KY1GSae4rtuAE9prkse7RUqgvmael5ojoxmPqVjxYT7P0Z6Sr5OImDmeQ pX4D7nE72EWzCTnSmEIxEN4tkBjzXokmNM/HgOOwa/69FpZ5e3Axvqstl21G+07HKFqs 4wZit6RDIU+GZ8PXLVC6zNVuji5LcEf7/mWaFvPoOAl5ysA3dXP+q4a84n77RgODSZgG mEMQ5VOfHBqabfOdMgFTbUGflCLoaxR4NHZ5uKranAN3Kxx2ppVl/3P/EB0UeToP+B8L 1qLb6vZ1aoLTYfA6a/09nYKqpHf/NNCft0nHEsP0rTHIWkLdJglgAyNgCxPY4BuDIkTD 82TA== X-Forwarded-Encrypted: i=1; AHgh+RqHIkj79q/mt/5SyQ89QB41mD8w86AvE57mt9gDAVL/7gy+Cp5tEEyp2O1ixJjcSj8Qq4OHC0mM0eII9f8=@vger.kernel.org X-Gm-Message-State: AFuF++mnxGng1Epx5B7quwpl/5i9dgDRLhk89hoWHoQTPpJ8k96NQv98 o7tDJPqRz0RIkXNFDNt+4t5FX1YKTCSomLi6Xr3ps1xIGFdkjGwI6NkF X-Gm-Gg: AR+sD12CeUNH1SBibomew0ZJfwlJQAJa1aMDqXEViuPNNXC3oSah80WIlafp9x7xwcu c8MA7JWTI73uRUMMrNxcL5cjfHIIJv0wEvie+1DGKdx//PgwnXH6yHgMVeaOEw2IG3dEl1k0HCG 7L7pq1rsAhJ9PoLA0MVIxhz86D29PKGn0MYGQaLeRwIDXhT6Q9meNy7O5OzmifBaf0zT8v1fcEO lXKVjFT9lFXDOX2iEk29fKL5KHEnkRMorOpyFR+iHLkL1CW969r6Mi4JIVF2H36A5q327EZAioE WwW+k+iOq92SsEzFEhel2AzPvH9Osbcn8mUBDrPnfs6Om3HZOLnDyEdJmCmjvnCiHRWAxir/S2d dwfVQscsMulwjU7YJlCio/1K/IIvL7zzViTgdDRWWBMI3m2SBt01eoQkdYLs50m1XC0/wk1Bdr8 JZHRsAmQB+w4XR/u6EPMwuy2lgxl7lbrER/UYrm0aqhPug5mUou2YT1uE+x3BGCRIEkNfIYVk7g zlK0DXMuIzH X-Received: by 2002:a17:90b:3902:b0:38e:a52e:a3c9 with SMTP id 98e67ed59e1d1-395a04ea8f7mr37077108a91.8.1787576795390; Mon, 24 Aug 2026 06:06:35 -0700 (PDT) Received: from localhost.localdomain ([152.59.223.115]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-327f92359c9sm26409711eec.27.2026.08.24.06.06.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 06:06:34 -0700 (PDT) From: Sreeshankar K To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, konradybcio@kernel.org, tglx@kernel.org, ulfh@kernel.org Cc: bmasney@redhat.com, radu@rendec.net, abel.vesa@oss.qualcomm.com, lpieralisi@kernel.org, taniya.das@oss.qualcomm.com, danila@mainlining.org, davidwronek@gmail.com, mani@kernel.org, robimarko@gmail.com, linux@gurudas.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K Subject: [PATCH v5 09/13] dt-bindings: arm: cpus: Document Kryo 475 CPUs Date: Mon, 24 Aug 2026 13:04:33 +0000 Message-ID: <20260824130437.2771-10-sreeshankar0910@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260824130437.2771-1-sreeshankar0910@gmail.com> References: <20260824130437.2771-1-sreeshankar0910@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document Kryo 475 CPUs found in Qualcomm SM7250 SoC. Signed-off-by: Sreeshankar K --- Documentation/devicetree/bindings/arm/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentatio= n/devicetree/bindings/arm/cpus.yaml index 5be89c584..2a90af67c 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -212,6 +212,7 @@ properties: - qcom,kryo465 - qcom,kryo468 - qcom,kryo470 + - qcom,kryo475 - qcom,kryo485 - qcom,kryo560 - qcom,kryo570 --=20 2.43.0 From nobody Mon Sep 28 08:55:48 2026 Received: from mail-pj1-f42.google.com (mail-pj1-f42.google.com [209.85.216.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CF2941F35C for ; Mon, 24 Aug 2026 13:06:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576808; cv=none; b=VUqKW5m9aZC6HaDIhd7d6DqR3XZX9Y82Y2etMh9i85OzOBtB0w5F8+NKpdX1F+P/qLZWE3/TF2HXJHxthGvZme6XrSPSaIZ8a0QKCOqOZiu7L2GWsd4CCnEWAMzzCEywyAuNp+PA+R7vRV0arHa9gdh3Qula5UN3ObxZgJ/4Bzc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576808; c=relaxed/simple; bh=iyIt2VTzEWJFddhlukajc/L6+s0oCbiYJdxmCZQgWaI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Lh/7ek9OXr9u9Kc2idPtYdXyerDcQF43yg+p6+7mAh24hH+zgzYGg3qsdcgYfavWV3Hpj9qj/8ISBomy8hisXeRe0rnOM59bf9qe0QHAgNTZrd1S+NsdADrAF2I3IIqs+WebCuohmdTSe+kDD+/2lb3AEVe3oXaBkopBNyz+MVQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=qQ+ZNjxr; arc=none smtp.client-ip=209.85.216.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="qQ+ZNjxr" Received: by mail-pj1-f42.google.com with SMTP id 98e67ed59e1d1-395cf2535acso2965701a91.1 for ; Mon, 24 Aug 2026 06:06:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787576806; x=1788181606; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=CRwL2GsSIS/j4FawlFSo6ds2Awqey70m0LWn3uJFJ0Y=; b=qQ+ZNjxrt9TCZP7krXpKT3XtkPWwGXThNVY8pamUDRY7RpthSuS7emqbqg+Z0vz1hO T/Q0U2+N8XUXCkZ3wgIv5fWgEZGEbcA3AFbXDW7nMvOYu4qfO7GGJhMW/5DgtWbxvjdS iMft9LPMbLYnCRwts1cQizR7LXrfe4njfyq11lN67Fp/oCfeB7xj2lamC18bD1e9nphg QLiefDzftZahxK+tjIsf5gxT6aEeDJDNah1FuN+pJ0/1sOgRhviQ0GUh//RCSmpPlAkP JSYaOYnza35VWNhIiPS6eHgsdZOUJoxx3nU4VjGrdEEUV9NIc5Lo3zMhRNtohxCkXMsF 7Svw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787576806; x=1788181606; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=CRwL2GsSIS/j4FawlFSo6ds2Awqey70m0LWn3uJFJ0Y=; b=iR8DKOo/Ko9glSxRx/NhLHQJ9gwBDgt7S7KF/4TOd1jYm7MwHTUyYgH+IqkCl2iky4 hLlbcugyBXvkY7z+jDS+aQcLF1u2015wxafF3Gaul+X+cwtznOCWl338Q/lNKTLOP0eO 7pwrOTMEIkLqkQDZ16uw3svfXi2vUCDhfM2dd5RDWFSh4wyTwYW8SYRQS1HjvA1O71Ms oNUbpsAHANyunRJynzTuuPi2+AXg59u4I51KndqzzGamDY7OXitlDWqU2vEB87HWaIS0 2E8OC/b3vDZMmRf2cmUPMBkwz9yn0h5E/8Um/FUZHwBG7KSz3nREB++27XhYDPshmcRC yPLQ== X-Forwarded-Encrypted: i=1; AHgh+RpfA7IBlGkBOdrdSgfv8NfehTb5h3oUkxzS2oiFGsBja1iR+Rga1BtXNwYA5DjGYroHeS9NISXD5dqrF60=@vger.kernel.org X-Gm-Message-State: AFuF++nyA6FKGronL0RAFS1a7iSV7rocLKhe0US7D6MRxj2MY9gJaXTP m/sP27lKbA9qpdtU86sRUJVaO1TF2EzRzxe/jzW7do4VNwfBMKq+ye4R X-Gm-Gg: AR+sD11z1qfbO2nyrm+F9fEgLU3Qg4v2+gdufNNBD70c/h5O6DYJGmy4Tvo03egH+2a c2sPEgyo00JoklzAmigBRbrDLpLEdAeBs93DIqRHCk+Y8JX7GG7gn9aQqxQTgTHI+4tu0oRYq2p fXnee4WIdr2YMa66Jbm0Vwx11d+dbDLUrxzSuSAnSy3Zq+U1jkKP79kB5egDJhaEq0f63av1Yj2 sqRhbh/GR3Ed48shvjxD0sPsarwYWR8Fn+WMh9ZH6n865vzl2AhFxQGJVSW6ejz9Qd+Q3Ujhu4o sfHCvPkp+QH/6pnbplolflex6vlM5UncXUqWvTDsX31+sTJy2mL4hZFHcvgjxNgfQ0zm78whpnw /cVH7BLn9O2UWKpJAOiCvgy5XlpenQpNcjrhORpFO6NorPx92eaIlxujMK1yldS7CLVzFuxSgHC f8QqsX8/CxK+rlOWNz8lWg0kSAzeJ7c6mGGEsPLtpQAzMefw2gPE6vHAGS1F4ByFLqoklhHeE1o ts6JD8tb3Iv X-Received: by 2002:a17:90b:3bcc:b0:37f:a913:1554 with SMTP id 98e67ed59e1d1-395a06bc47amr39222445a91.16.1787576805712; Mon, 24 Aug 2026 06:06:45 -0700 (PDT) Received: from localhost.localdomain ([152.59.223.115]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-327f92359c9sm26409711eec.27.2026.08.24.06.06.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 06:06:45 -0700 (PDT) From: Sreeshankar K To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, konradybcio@kernel.org, tglx@kernel.org, ulfh@kernel.org Cc: bmasney@redhat.com, radu@rendec.net, abel.vesa@oss.qualcomm.com, lpieralisi@kernel.org, taniya.das@oss.qualcomm.com, danila@mainlining.org, davidwronek@gmail.com, mani@kernel.org, robimarko@gmail.com, linux@gurudas.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K , Krzysztof Kozlowski Subject: [PATCH v5 10/13] dt-bindings: firmware: qcom,scm: Document SM7250 SCM Date: Mon, 24 Aug 2026 13:04:34 +0000 Message-ID: <20260824130437.2771-11-sreeshankar0910@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260824130437.2771-1-sreeshankar0910@gmail.com> References: <20260824130437.2771-1-sreeshankar0910@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the SCM compatible for Qualcomm SM7250 SoC. Acked-by: Krzysztof Kozlowski Signed-off-by: Sreeshankar K --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Doc= umentation/devicetree/bindings/firmware/qcom,scm.yaml index 037d4ad8f..0cbdb3b2f 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -74,6 +74,7 @@ properties: - qcom,scm-sm6350 - qcom,scm-sm6375 - qcom,scm-sm7150 + - qcom,scm-sm7250 - qcom,scm-sm8150 - qcom,scm-sm8250 - qcom,scm-sm8350 --=20 2.43.0 From nobody Mon Sep 28 08:55:48 2026 Received: from mail-pj1-f43.google.com (mail-pj1-f43.google.com [209.85.216.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A3BF41E6C5 for ; Mon, 24 Aug 2026 13:06:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576821; cv=none; b=DNb9TUoeqpWymPLa2nrFcyC1Se42Kilf2ZzKuqVc4KEQaugOyYN5xJsF6afhR0sQUKbLroorSRuNQXrFY5zMa3Y3xoah8qCCryxXuxWgQSJTe4WNr9tZRNwawv1nuWHwFF5VlMUY5bbfU9IglTkAzt5B1cIBdplO7yVc/Exz1KU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576821; c=relaxed/simple; bh=S4gVIUWwuoALYuzwzRm82WuAYzYN5KLWtNbqZ/oM/+w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YiA/oH01IhftXGRiXHc8Vmm6n3em8QKNdh5zXilEJnSzwOZ8XunBOO8pmt0ymGSBfsbQuGk3dZP9s6hMbPhr14aFsrZO7mYz0HqIW8DBXvn7xVFPz/rVg34+RqBQkTT4E/NlHqNYXGpYKfTh/S3toJHd9Ww4/SIUq3GhWT9VrF8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=FR4ldn4+; arc=none smtp.client-ip=209.85.216.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="FR4ldn4+" Received: by mail-pj1-f43.google.com with SMTP id 98e67ed59e1d1-3856d6fbcb3so2918692a91.2 for ; Mon, 24 Aug 2026 06:06:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787576815; x=1788181615; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=g3FdfDbvToHSgtTrj8YFlW83QqqTfihaw6vnLz7PZc8=; b=FR4ldn4+0piraMrYiGpAT5yAvUsgGTNMIaDUDHRkGNjLabNaCiuNYz+yhgFO+uZ7KD ljgQklwBfFcEK9uisZYjF80BfeHVWFKfXJoXSt6Ef6aBfse63Dr+Q6gTeSG1lsiq8E1e A9FpuflxRcLf7WghoNBUAPW7OHg3kBuNn9/aFfdK16tJ7fSk0mLlCa0neGIue8pTbTMU RMr70B8unMIaTnTJSItezUK6+a6Z5pCivH/SSckiq7MTNphl9eMhDdRbxpX+8ebZfWTa BXPhobbTkcMwI59YLzliwRJ/mF6u/+197G/jYZN04v6fIDqX13LinD2N7HtSLEy/sYGj WEKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787576815; x=1788181615; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=g3FdfDbvToHSgtTrj8YFlW83QqqTfihaw6vnLz7PZc8=; b=C+cgejz3L3Vswdzt/hUmRrldJ3v+kuqBAC1+ffSU2+pNMriJ7KxEyUdpjY9gMIVyp3 3vtDTrMtGd+c2JGs/uHwT8UjedVxRGhD+/SswdadStPzaqGhqLExzZqrIfQMSs39yQPO FSuvY//H5+RW5BFvxZ0X/Q6vzv5MMinsrKhYGUqP/89kUaiqvLWcmmatdWWET9cg6q3J RpSRdqWseItFckiqXwbNCgvtPUhhoCCqPE8xNGXbxZSsG6J03X7/gqr3r+S5H460jfSu ZlGuXhFSthOgZcJZ/UvIemxhMRieXRjaHlTFnzOLrwddDzqYY722sBk73RuLfEAebDO8 yvBg== X-Forwarded-Encrypted: i=1; AHgh+RpO9o5t6GL3Ppco2O6i2D6t0hGGuTTW0Ls1FpGjEyRM1rR3XX7v/FtRx2NXsuBw0mAC+s/iBQWYSVNCcrQ=@vger.kernel.org X-Gm-Message-State: AFuF++nNvdD35t+XCoFuG2+0mLoS3ZndAoFhA5PPXNTnfODKFLWKOK/K Yo7+zAcDa5TzZKpr0v1FS1TkF5Wi5bMDN82Vly5hIFihE8XZHOLQrEWP X-Gm-Gg: AR+sD12Ig/mM6XJofvOD7fuYT6yp3svjofvdBZWSDz5A/r8qLkcD/ohx3anJIcPLXKJ mcVO9DOn2n9pRSiUraGm11YEmE8+cSS3x0uvEErpgDHCykgDRy2JEUmbyIWUrDMgoH/MTPY/CWS D6dUxPef3rFst9/xwxROLdwe1BHsO4O61DNZleMLHlU1RNKveWT3bXLzDh5ACE7dVQM2z1FGVHN xdpecY8vuE25bzcuyt6SqdRI0gTecZxyPY6cXLsP46lMuNwBH8EpFs9cP0v0+bjYq6tkYz/E001 V06StgPKtmH/VQv78kdUYFqqf+uNtN9HZzi+TUZZb2QR1vZR/wnKpHoZ5V/y5g+a6R6VKS381Wr 65q2Ex/e1gEBrFUexAeRvXQEejA9YONQl6XGGQLy20WOhHzOqbKLMoHHDNVlS7eS/Awi/GgcdFJ r+Jxd08dQ4OQYxRPO0pBAkh+ibqVW20uZOD68lmoM+OVjjh0bB3O58QX+NvZDnm+m6PoObE/NJ4 P7OyN+PyucwjYJPVLwjrajd X-Received: by 2002:a17:90b:33c2:b0:38e:c232:9d3f with SMTP id 98e67ed59e1d1-395c3597c56mr43924218a91.5.1787576815440; Mon, 24 Aug 2026 06:06:55 -0700 (PDT) Received: from localhost.localdomain ([152.59.223.115]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-327f92359c9sm26409711eec.27.2026.08.24.06.06.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 06:06:55 -0700 (PDT) From: Sreeshankar K To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, konradybcio@kernel.org, tglx@kernel.org, ulfh@kernel.org Cc: bmasney@redhat.com, radu@rendec.net, abel.vesa@oss.qualcomm.com, lpieralisi@kernel.org, taniya.das@oss.qualcomm.com, danila@mainlining.org, davidwronek@gmail.com, mani@kernel.org, robimarko@gmail.com, linux@gurudas.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K Subject: [PATCH v5 11/13] dt-bindings: interrupt-controller: qcom,pdc: Document SM7250 PDC Date: Mon, 24 Aug 2026 13:04:35 +0000 Message-ID: <20260824130437.2771-12-sreeshankar0910@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260824130437.2771-1-sreeshankar0910@gmail.com> References: <20260824130437.2771-1-sreeshankar0910@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the PDC block on the SM7250 SoC. Signed-off-by: Sreeshankar K --- .../devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pd= c.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.ya= ml index 8162a49d4..c30b88589 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -50,6 +50,7 @@ properties: - qcom,sdx75-pdc - qcom,sm4450-pdc - qcom,sm6350-pdc + - qcom,sm7250-pdc - qcom,sm8150-pdc - qcom,sm8250-pdc - qcom,sm8350-pdc --=20 2.43.0 From nobody Mon Sep 28 08:55:48 2026 Received: from mail-oa1-f50.google.com (mail-oa1-f50.google.com [209.85.160.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACB333254B0 for ; Mon, 24 Aug 2026 13:07:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576828; cv=none; b=NZcAZkSjMgxtkOxNdteMWGKBh9AyF38WHwsW+9L7R7OHqlW9ZbBMKsyX9nSHnZhrgGuH1GpjL8s3wJ3Y9iu7oG01aX1yRINItIqXTrvvY4Iefp89hcVAE0Mulot1ugA84jGMGB9QpGBc6ZJkOvC3U1yUr3ln7+pvqsYwHwyBOUk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576828; c=relaxed/simple; bh=4RIma+Y+HLa539L6LCBdujL9cmImh2ch5UAVuCX8GcQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qGS1G3IOGCZj3Bg/fzgvMipRfgP6ZaxWhd1AbrZuC+zNpX4T7QHKGEixGvua2SayX8DrdpGBN274lckk1N9SmP+5rlBskKqX1bChFydvn9IS/+6xJFOOVGwXaUWcSXU4Zr90a9K6RqDuV9aF5jzi7Ci/pB31b2kGtLYeIah3NI0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Bffr6PrZ; arc=none smtp.client-ip=209.85.160.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Bffr6PrZ" Received: by mail-oa1-f50.google.com with SMTP id 586e51a60fabf-44cf70de986so2302089fac.0 for ; Mon, 24 Aug 2026 06:07:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787576826; x=1788181626; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=FyimhIuXwBU1D0482FUuZm2aPAmZo3McPam/rouEA1c=; b=Bffr6PrZnY9Goe/SQao/FHiRWG23Y7ymKvkiMomxRf20s06ddC0HX4RiTVkKPrxcJI rH2FyPbTO58JNxMsaiKlMYQ7xtdauRm8nekzbPqZjtOzNouCIzMrHWQ+BI7t0NknzZiy 1zR7XXU1N8yZI+LvWHwgmw8MpadIpc/TQAiIO/MHdRdvbRbImT69AU2oU+oek9nlvHZm KeV8qe17+hVBq1W+TqqNATU6ZrHCiyJoY8A6yShG0O5kjFaaR3cWBBuizCPlzbK/Mins Gi/3Ch3p4rlJ0PNW19pYCsEpZ7Bx27v0LhpFefMnuyaFepO7X0u7Fmh81Q0hSw4r4FQL 9qSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787576826; x=1788181626; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=FyimhIuXwBU1D0482FUuZm2aPAmZo3McPam/rouEA1c=; b=e+3mjW5oHtECH3m2YmFpAhJa/uHfWza+5FQIxEL/bUmH8U4I4bcuOYee72m+j3PQ08 FUUauQXAGS+4NR/Alce8ojVAWr2s8yeC02ycuEkafr2lCt7cSC1bohbDfnodK2IKBDu/ 4iG+Qc2XtmfRVjVYe8QtM9WWzu/qrwTzwofgwxaRDXrVdGZtfuwZEjBlFWv3JbInfwtq 8TCZkWv0zTwUfxeZ9B8g9u1lQ5MCNJBSPDuU2JsB5QjJb/dz4CjhWVikQGzwd1lZdgIQ P7JH+eC/uv839RqSdzj1qCsx/Fis8o7304g4p37pgW8aVv8b4yPEwWxQ50nI+vkwiqxZ wiag== X-Forwarded-Encrypted: i=1; AHgh+RrleJhNjzT7VU6yrUSbY8NtAcU3HznRNVmR1CfzKT77J5ewckvorlcrQNiKfBmzDVDyzSAwdB+EYdB+dD0=@vger.kernel.org X-Gm-Message-State: AFuF++ngWLKUfMT4PhcJkojrItwF+XJOxqCx6wz91QWqTnv2wEh2o0Uj VpdXbeJmd7KzL1rQzh+9gol6dHJYR/vIyclTrhD52tE3kvBatW+iL6/L X-Gm-Gg: AR+sD1200gJNo4gnm6/+p0ymoVsoHobmV2+3d4GBJslQjTJ1Y6Cx9vQDul17ljnC0c+ 1QkRIk7Cx7bfZFv9s1lLOUmjoV/j1ixY65446J9pPvNQ14ESt2OFSz1xml+0f6t3KsrNwxfUZr1 bnNFLhi1jFK+yPO6hMNCMxX7Ob9Ntw8xh1m65pzueYFVEcKE+sVKhBm0fEwxTIKPGKbILX70qAI FT/GnlPFFV1XoFyoRFIovuMnw0hCFftBDM4FKLkF/5io2B2pghUnxGhu0J4Ulfq+Rp+lP9Bj8H0 ynuJwTZPur6B8C++yI1kemO3c1My8xUfuStUvFhMTRVXBpmnb1RVVHU+k8G7fFWIwiWx+DJeEaZ im6a4ZXC/nUBMRFXjDmNyWSCAOKaxTaASHgsVmnka5NJDhdOhIT7Igi27+qi/O2VgslE84Smzf8 fxP/A3u00bDRuoIQ3y+AUEAj6TlxYog6rpFjje71i0sRfGZG4lNrEyzsxST/tU4/XGycdsKnolm HlXvpXwI9/gzcldO7wZVcM= X-Received: by 2002:a05:6820:4089:b0:6b1:37e6:92ca with SMTP id 006d021491bc7-6b16b1f9ea8mr14908866eaf.3.1787576825665; Mon, 24 Aug 2026 06:07:05 -0700 (PDT) Received: from localhost.localdomain ([152.59.223.115]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-327f92359c9sm26409711eec.27.2026.08.24.06.06.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 06:07:05 -0700 (PDT) From: Sreeshankar K To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, konradybcio@kernel.org, tglx@kernel.org, ulfh@kernel.org Cc: bmasney@redhat.com, radu@rendec.net, abel.vesa@oss.qualcomm.com, lpieralisi@kernel.org, taniya.das@oss.qualcomm.com, danila@mainlining.org, davidwronek@gmail.com, mani@kernel.org, robimarko@gmail.com, linux@gurudas.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K Subject: [PATCH v5 12/13] dt-bindings: cpufreq: qcom-hw: Document SM7250 cpufreq hardware Date: Mon, 24 Aug 2026 13:04:36 +0000 Message-ID: <20260824130437.2771-13-sreeshankar0910@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260824130437.2771-1-sreeshankar0910@gmail.com> References: <20260824130437.2771-1-sreeshankar0910@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the cpufreq hardware on the SM7250 SoC. Acked-by: Viresh Kumar Signed-off-by: Sreeshankar K --- Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml= b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index 98eb36bff..2dc2c265c 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -29,6 +29,7 @@ properties: - qcom,sdm845-cpufreq-hw - qcom,sm6115-cpufreq-hw - qcom,sm6350-cpufreq-hw + - qcom,sm7250-cpufreq-hw - qcom,sm8150-cpufreq-hw - const: qcom,cpufreq-hw =20 --=20 2.43.0 From nobody Mon Sep 28 08:55:48 2026 Received: from mail-oa1-f41.google.com (mail-oa1-f41.google.com [209.85.160.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C705741E6D9 for ; Mon, 24 Aug 2026 13:07:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576839; cv=none; b=tK7WHZzCYNqAkvCUr9lGB81jouH40nJtSEFGZo7kLhBndL+biZrF8UhIzG/aFuOXqSC4VhZXBgYzwxuFlQcO9q2udbga5qcKjN5XF0RymCZ6FJnkC0x0opRuCtReTbQDSfsc2Kvxhq49gY431k3dnluochpENPlYcly8Cw+Sens= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576839; c=relaxed/simple; bh=omTUUTAowhGhfkGHRKI06S6BOTzLG5wZwbvRWZmw2h8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=H1ItwD7Frxh1+lU2M9Z9i+6VygG6Urh6deIBdmCt5XdH4Al32oMU1k8E5+z9J/aBKQPL4d76TvRLsskxImvBnAQ84mqK5JJq6iVrUxMH/Z5BTbDEytjuAm9Bti0yAkkB1DMJDeInhpNyo7zEU04ek3X+2jg7uFEaC8jU9Y5Hcrs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=I94wHaoz; arc=none smtp.client-ip=209.85.160.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="I94wHaoz" Received: by mail-oa1-f41.google.com with SMTP id 586e51a60fabf-44cb057311bso3095046fac.0 for ; Mon, 24 Aug 2026 06:07:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787576836; x=1788181636; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=icIYTLAJwZUHunq5OF9oQIZnNmh7Jr65mjbVyEYcdC8=; b=I94wHaoz7vLXODwNoVJuQDqHalapSA8wwr58RM4+XSqz6TBDzOWM7BwWitcGrw5qwH AC45Wl3gC96vqPuFlTwEO+63nLnuUdkeYffD7bJyKIWYfx1FfZ07zHinaiC0os6VlsnF 6ghBS/cq0GlG3IDL3+573R9236ehJI7sRUixc0upH24PgijMqODqdOkUGqvJ28ZsnhSt v5I6xlK9q4DRTBfG0gl/xo7xtmQx8rP818TGwd/hGZiJLMGe00hEUyeLOgZdsiqniVDp TB/5j+U+ndc4l78d5zvCdQQ9pCDAq3fjjy4Y2+sHv+Z/HDPOKX+2/zegpIt4f9HuHHk+ KyPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787576836; x=1788181636; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=icIYTLAJwZUHunq5OF9oQIZnNmh7Jr65mjbVyEYcdC8=; b=PehK6qfhAG9SIv4ODIeHPhpBj/sdhC2Ft37hJx7x6B6ljrP1K3wr68DASiBHr1CTV4 aSCb4FUzYZTQ3buN+OIxamq679jV34VGHjsri9W2NXiuO4st7rOz3ydT7qoVd435DF05 Ov9mYriAFDzIzSpSpe+svMMMq1yI49+bh82Im5ADY5TrU7ovXlvEqvTWuEu2lLrETBS5 oVNxZyYAqrIHkHsEjpHQN9MPJXcPeFgXtRe3woV++JgSF/eLHwn0tEn/HN2Hpq4488b/ sM15UlV5hRvunzGnhK3wxYaRTMpwg2k+94fUq6uD23wHb0nDwO+bXKbDJ71DnMpDjhxC wG1g== X-Forwarded-Encrypted: i=1; AHgh+RoFrXdElk71FrYpCjfis8I6quQJVtA+ivP0x8caRbtVGbfh02srVdeAsi6G7AzE1Vxjz4zzoiJIEBcNxdk=@vger.kernel.org X-Gm-Message-State: AFuF++khqoS85sctGmqMjPGfRBuX9fqeODwbzvH8ZAfi3t71hEMWqO70 YN6Xy0+/QG5/LHcOsd0NtU/VqFJjj2z6GROKhUlkEaD6NLI18dxxsAkf X-Gm-Gg: AR+sD122E3Ker66hcTR8ZzgeiGNA2Vn7VPdouw4RfeH3pI9SaVfvLhYEtJ1ZsIALoep ctpCGwWSfQV1B77/XstKFk6BNdz+4mJprKn4kvhKk6B0LInfwqWdRhmk+8LebP8qDr2YGcc7HJJ iyDBSxa/a7YTmd1Lk/zGevySUeD8yN8CJXSJMoElaeNF0WegNKtmUYT9RyGSGookaQYwCCl9I9U q55jxRl+b2PBF33CzLcOHtE8DAL7nLr2cmHGwWG5+qMcFBJwHCkWqdGi43swKjO8o79wzQAN7ru 4ciOE/GAdORHar1WvfIuMULuY1TqD/WYx37RmB0kXRLppWIN8whTIROP8i1hgOpdkwNuTZcXmmd k7pKMpTJZR5bmo4uTQ+hLx1kQiq1gEwihTXAWPu+TRjpKyPtzRiUmUrl81/48/JLWG28Um4II3s V1J6HunCTbhUhxIFkBAorxjC8K4VGX96GyQwGdkXo9brtQDmB+/YBj/7SAu8Y0Oo3M88SiZYQtO oKFGMsLmuGtyTOwTWLtSFQ= X-Received: by 2002:a05:6820:1891:b0:6b1:63d8:261d with SMTP id 006d021491bc7-6b163d8278cmr21276505eaf.17.1787576835565; Mon, 24 Aug 2026 06:07:15 -0700 (PDT) Received: from localhost.localdomain ([152.59.223.115]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-327f92359c9sm26409711eec.27.2026.08.24.06.07.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 06:07:15 -0700 (PDT) From: Sreeshankar K To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, konradybcio@kernel.org, tglx@kernel.org, ulfh@kernel.org Cc: bmasney@redhat.com, radu@rendec.net, abel.vesa@oss.qualcomm.com, lpieralisi@kernel.org, taniya.das@oss.qualcomm.com, danila@mainlining.org, davidwronek@gmail.com, mani@kernel.org, robimarko@gmail.com, linux@gurudas.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K Subject: [PATCH v5 13/13] arm64: dts: qcom: Add SM7250 devicetree file Date: Mon, 24 Aug 2026 13:04:37 +0000 Message-ID: <20260824130437.2771-14-sreeshankar0910@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260824130437.2771-1-sreeshankar0910@gmail.com> References: <20260824130437.2771-1-sreeshankar0910@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add base devicetree file for SM7250 SoC. This file adds the basic nodes like cpu, psci and other required configuration for booting up to the serial console. Signed-off-by: Sreeshankar K --- arch/arm64/boot/dts/qcom/sm7250.dtsi | 771 +++++++++++++++++++++++++++ 1 file changed, 771 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm7250.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm7250.dtsi b/arch/arm64/boot/dts/qco= m/sm7250.dtsi new file mode 100644 index 000000000..48480e685 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7250.dtsi @@ -0,0 +1,771 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026, Sreeshankar K + */ + +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + clocks { + xo_board: xo-board { + compatible =3D "fixed-clock"; + clock-frequency =3D <38400000>; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <32764>; + #clock-cells =3D <0>; + }; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo475"; + reg =3D <0x0 0x0>; + clocks =3D <&cpufreq_hw 0>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + next-level-cache =3D <&l2_0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + power-domains =3D <&cpu_pd0>; + power-domain-names =3D "psci"; + #cooling-cells =3D <2>; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x20000>; + cache-unified; + next-level-cache =3D <&l3_0>; + + l3_0: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-size =3D <0x200000>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo475"; + reg =3D <0x0 0x100>; + clocks =3D <&cpufreq_hw 0>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + next-level-cache =3D <&l2_100>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + power-domains =3D <&cpu_pd1>; + power-domain-names =3D "psci"; + #cooling-cells =3D <2>; + + l2_100: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x20000>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo475"; + reg =3D <0x0 0x200>; + clocks =3D <&cpufreq_hw 0>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + next-level-cache =3D <&l2_200>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + power-domains =3D <&cpu_pd2>; + power-domain-names =3D "psci"; + #cooling-cells =3D <2>; + + l2_200: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x20000>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo475"; + reg =3D <0x0 0x300>; + clocks =3D <&cpufreq_hw 0>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + next-level-cache =3D <&l2_300>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + power-domains =3D <&cpu_pd3>; + power-domain-names =3D "psci"; + #cooling-cells =3D <2>; + + l2_300: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x20000>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo475"; + reg =3D <0x0 0x400>; + clocks =3D <&cpufreq_hw 0>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + next-level-cache =3D <&l2_400>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + power-domains =3D <&cpu_pd4>; + power-domain-names =3D "psci"; + #cooling-cells =3D <2>; + + l2_400: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x20000>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo475"; + reg =3D <0x0 0x500>; + clocks =3D <&cpufreq_hw 0>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + next-level-cache =3D <&l2_500>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + power-domains =3D <&cpu_pd5>; + power-domain-names =3D "psci"; + #cooling-cells =3D <2>; + + l2_500: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x20000>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu6: cpu@600 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo475"; + reg =3D <0x0 0x600>; + clocks =3D <&cpufreq_hw 1>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1740>; + dynamic-power-coefficient =3D <341>; + next-level-cache =3D <&l2_600>; + qcom,freq-domain =3D <&cpufreq_hw 1>; + power-domains =3D <&cpu_pd6>; + power-domain-names =3D "psci"; + #cooling-cells =3D <2>; + + l2_600: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x40000>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu7: cpu@700 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo475"; + reg =3D <0x0 0x700>; + clocks =3D <&cpufreq_hw 2>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1740>; + dynamic-power-coefficient =3D <375>; + next-level-cache =3D <&l2_700>; + qcom,freq-domain =3D <&cpufreq_hw 2>; + power-domains =3D <&cpu_pd7>; + power-domain-names =3D "psci"; + #cooling-cells =3D <2>; + + l2_700: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + + core4 { + cpu =3D <&cpu4>; + }; + + core5 { + cpu =3D <&cpu5>; + }; + }; + + cluster1 { + core6 { + cpu =3D <&cpu6>; + }; + }; + + cluster2 { + core7 { + cpu =3D <&cpu7>; + }; + }; + }; + + domain-idle-states { + cluster_sleep_pc: cluster-sleep-0 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41000044>; + entry-latency-us =3D <2752>; + exit-latency-us =3D <3048>; + min-residency-us =3D <6118>; + }; + + cluster_sleep_cx: cluster-sleep-1 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41001244>; + entry-latency-us =3D <3638>; + exit-latency-us =3D <4562>; + min-residency-us =3D <8467>; + }; + + cluster_sleep_aoss: cluster-sleep-2 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x4100b244>; + entry-latency-us =3D <3263>; + exit-latency-us =3D <6562>; + min-residency-us =3D <9826>; + }; + }; + + idle-states { + entry-method =3D "psci"; + + little_cpu_sleep_0: cpu-sleep-0-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "little-power-collapse"; + arm,psci-suspend-param =3D <0x40000003>; + entry-latency-us =3D <549>; + exit-latency-us =3D <901>; + min-residency-us =3D <1774>; + local-timer-stop; + }; + + little_cpu_sleep_1: cpu-sleep-0-1 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "little-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <702>; + exit-latency-us =3D <915>; + min-residency-us =3D <4001>; + local-timer-stop; + }; + + big_cpu_sleep_0: cpu-sleep-1-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "big-power-collapse"; + arm,psci-suspend-param =3D <0x40000003>; + entry-latency-us =3D <523>; + exit-latency-us =3D <1244>; + min-residency-us =3D <2207>; + local-timer-stop; + }; + + big_cpu_sleep_1: cpu-sleep-1-1 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "big-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <526>; + exit-latency-us =3D <1854>; + min-residency-us =3D <5555>; + local-timer-stop; + }; + }; + }; + + firmware { + scm: scm { + compatible =3D "qcom,scm-sm7250", "qcom,scm"; + #reset-cells =3D <1>; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible =3D "arm,armv8-pmuv3"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>, + <&little_cpu_sleep_1>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>, + <&little_cpu_sleep_1>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>, + <&little_cpu_sleep_1>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>, + <&little_cpu_sleep_1>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>, + <&little_cpu_sleep_1>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0>, + <&little_cpu_sleep_1>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>, + <&big_cpu_sleep_1>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0>, + <&big_cpu_sleep_1>; + }; + + cluster_pd: power-domain-cpu-cluster0 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_sleep_pc>, + <&cluster_sleep_cx>, + <&cluster_sleep_aoss>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + hyp_mem: hyp@80000000 { + reg =3D <0x0 0x80000000 0x0 0x600000>; + no-map; + }; + + xbl_aop_mem: xbl-aop@80700000 { + reg =3D <0x0 0x80700000 0x0 0x160000>; + no-map; + }; + + cmd_db: cmd-db@80860000 { + compatible =3D "qcom,cmd-db"; + reg =3D <0x0 0x80860000 0x0 0x20000>; + no-map; + }; + + xbl_uefi_mem: xbl-uefi@80880000 { + reg =3D <0 0x80880000 0 0x14000>; + no-map; + }; + + smem_mem: smem@80900000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x80900000 0x0 0x200000>; + no-map; + hwlocks =3D <&tcsr_mutex 3>; + }; + + removed_mem: removed@80b00000 { + reg =3D <0x0 0x80b00000 0x0 0x1300000>; + no-map; + }; + + camera_mem: camera@86000000 { + reg =3D <0x0 0x86000000 0x0 0x500000>; + no-map; + }; + + npu_mem: npu@86500000 { + reg =3D <0x0 0x86500000 0x0 0x500000>; + no-map; + }; + + video_mem: video@86a00000 { + reg =3D <0x0 0x86a00000 0x0 0x500000>; + no-map; + }; + + cdsp_mem: cdsp@87400000 { + reg =3D <0x0 0x87400000 0x0 0x1e00000>; + no-map; + }; + + adsp_mem: adsp@89200000 { + reg =3D <0x0 0x89200000 0x0 0x2800000>; + no-map; + }; + + wlan_fw_mem: wlan-fw@8ba00000 { + reg =3D <0x0 0x8ba00000 0x0 0x200000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@8bc00000 { + reg =3D <0x0 0x8bc00000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@8bc10000 { + reg =3D <0x0 0x8bc10000 0x0 0x5400>; + no-map; + }; + + gpu_mem: gpu@8bc15400 { + reg =3D <0x0 0x8bc15400 0x0 0x2000>; + no-map; + }; + + modem_wlan_mem: modem-wlan@8c000000 { + reg =3D <0x0 0x8c000000 0x0 0xf800000>; + no-map; + }; + + cdsp_sec_mem: cdsp-sec@9f400000 { + reg =3D <0x0 0x9f400000 0x0 0xc00000>; + no-map; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0 0 0 0 0x10 0>; + dma-ranges =3D <0 0 0 0 0x10 0>; + + gcc: clock-controller@100000 { + compatible =3D "qcom,sm7250-gcc"; + reg =3D <0x0 0x00100000 0x0 0x1f0000>; + clock-names =3D "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + qupv3_id_1: geniqup@9c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x009c0000 0x0 0x6000>; + clock-names =3D "m-ahb", "s-ahb"; + clocks =3D <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + uart2: serial@988000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0 0x00988000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts =3D ; + status =3D "disabled"; + }; + }; + + intc: interrupt-controller@17a00000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + #interrupt-cells =3D <3>; + interrupt-controller; + interrupts =3D ; + }; + + pdc: interrupt-controller@b220000 { + compatible =3D "qcom,sm7250-pdc", "qcom,pdc"; + reg =3D <0 0xb220000 0 0x30000>, <0 0x17c000f0 0 0x60>; + qcom,pdc-ranges =3D <0 480 42>, + <42 612 28>, + <70 63 1>, + <71 640 15>, + <86 522 52>; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&intc>; + interrupt-controller; + }; + + spmi_bus: spmi@c440000 { + compatible =3D "qcom,spmi-pmic-arb"; + reg =3D <0x0 0x0c440000 0x0 0x0001100>, + <0x0 0x0c600000 0x0 0x2000000>, + <0x0 0x0e600000 0x0 0x0100000>, + <0x0 0x0e700000 0x0 0x00a0000>, + <0x0 0x0c40a000 0x0 0x0026000>; + reg-names =3D "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupt-names =3D "periph_irq"; + interrupts-extended =3D <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee =3D <0>; + qcom,channel =3D <0>; + #address-cells =3D <2>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <4>; + }; + + apps_rsc: rsc@18200000 { + compatible =3D "qcom,rpmh-rsc"; + reg =3D <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names =3D "drv-0", + "drv-1", + "drv-2"; + interrupts =3D , + , + ; + label =3D "apps_rsc"; + qcom,tcs-offset =3D <0xd00>; + qcom,drv-id =3D <2>; + qcom,tcs-config =3D , , + , ; + power-domains =3D <&cluster_pd>; + + rpmhcc: clock-controller { + compatible =3D "qcom,sm7250-rpmh-clk"; + #clock-cells =3D <1>; + clock-names =3D "xo"; + clocks =3D <&xo_board>; + }; + + rpmhpd: power-controller { + compatible =3D "qcom,sm7250-rpmhpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level =3D ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level =3D ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level =3D ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level =3D ; + }; + }; + }; + + apps_bcm_voter: bcm-voter { + compatible =3D "qcom,bcm-voter"; + }; + }; + + cpufreq_hw: cpufreq@18323000 { + compatible =3D "qcom,sm7250-cpufreq-hw", "qcom,cpufreq-hw"; + reg =3D <0 0x18323000 0 0x1000>, + <0 0x18325800 0 0x1000>, + <0 0x18327800 0 0x1000>; + reg-names =3D "freq-domain0", + "freq-domain1", + "freq-domain2"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; + #freq-domain-cells =3D <1>; + #clock-cells =3D <1>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x01f40000 0x0 0x40000>; + #hwlock-cells =3D <1>; + }; + + timer@17c20000 { + compatible =3D "arm,armv7-timer-mem"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + reg =3D <0x0 0x17c20000 0x0 0x1000>; + + frame@17c21000 { + frame-number =3D <0>; + interrupts =3D , + ; + reg =3D <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + }; + + frame@17c23000 { + frame-number =3D <1>; + interrupts =3D ; + reg =3D <0x17c23000 0x1000>; + status =3D "disabled"; + }; + + frame@17c25000 { + frame-number =3D <2>; + interrupts =3D ; + reg =3D <0x17c25000 0x1000>; + status =3D "disabled"; + }; + + frame@17c27000 { + frame-number =3D <3>; + interrupts =3D ; + reg =3D <0x17c27000 0x1000>; + status =3D "disabled"; + }; + + frame@17c29000 { + frame-number =3D <4>; + interrupts =3D ; + reg =3D <0x17c29000 0x1000>; + status =3D "disabled"; + }; + + frame@17c2b000 { + frame-number =3D <5>; + interrupts =3D ; + reg =3D <0x17c2b000 0x1000>; + status =3D "disabled"; + }; + + frame@17c2d000 { + frame-number =3D <6>; + interrupts =3D ; + reg =3D <0x17c2d000 0x1000>; + status =3D "disabled"; + }; + }; + + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; +}; --=20 2.43.0