From nobody Mon Sep 28 08:47:22 2026 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2263A306B08 for ; Mon, 24 Aug 2026 12:55:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576141; cv=none; b=ofEKrN+lAJ/Nream74mcsXqOCoX1SxNegZ5r2HWxvWNIjcBU1nwj+cVGgk2jIp5XeM/OXQTmx3bdKULnOfOZhWx6ORoK3QuZBesM8m1gccAmUDmb7uVBFxu3pDO8KjzLhlaEOsuZ+M5J5Cm8hOmjU2gK8oEMzTaaq4Ay8tuwMfY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576141; c=relaxed/simple; bh=yYMxWP4A+NRrpVCC8gDaREvOylF196wwLNFk89y0MU0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=CHBa4sPB2tR6R7f/8he8XE4MPf36ttYq1ufF2t87S6i4bYzwC472zjWD5F5G2qu9DCibBQ6M5/GtWPCMF4Iw2aRPL68ogPPoM4+/0nX3mZMnkgLZcnUkWohxEsbL2qRwoEKvAFxtj1VTA60BjThILNVO4wtolGy7Yp0YPxe3XeQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=eDDSpb5q; arc=none smtp.client-ip=209.85.218.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="eDDSpb5q" Received: by mail-ej1-f53.google.com with SMTP id a640c23a62f3a-c2055573c8cso518108966b.3 for ; Mon, 24 Aug 2026 05:55:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787576138; x=1788180938; darn=vger.kernel.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:from:to:cc:subject :date:message-id:reply-to:content-type; bh=1qoR/dhTppfDpvNv2/Q5EDuQc2/02Dofvc/NVVx1pJc=; b=eDDSpb5qBv4HRdRpoSiMCdJ41a3k/OAohYQZqDBXR1P9+3Ky+NgZF4KLxd0vrBj3Kr Bhen6vGTZkCw5Jvc07HVhoDuC+Gl4wCwPVu4ypDwbVPSSoJ3XsBDRnTftuxKC+YgX00R HaFJ8msqxmcRuBYYYlzWHKtzuMAh1EOTWa8KQ2J6FDGlNwwR4ter363t+1Dgw0dmorVt 2wznpYItCA8nZWo0O2CgSXCEjt6Z9XXvqsxYieMU2857ViNsapLWV484vIRhgFfl+3HN ApsZpIVCbfzyhVR0ad8QGTVmnYMtUUIB9h6YXy67AxGyIXXcu2ieS4x3bhfrEiItRzbD APUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787576138; x=1788180938; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=1qoR/dhTppfDpvNv2/Q5EDuQc2/02Dofvc/NVVx1pJc=; b=MI09WUreoN0H0tPyThpz5i58v9atlgEhpVc1MLtk738HHcjC3JLQu/lMlzwRYN9EE3 sEazJW9LjCvV3T6nJt7fH32+uqGOxJJK1aHrRDlSAXdaDM1+FOHPGuJd4S85A+hzw09e qaCsOrOLcK7u87O6pDwc7JNXJKVGVZAHUh7EVbVHHvRJNJpVJLniT4cFeD1Q7y6w7L4a uo4GAMt+e0k2Lg/s5meRJS8AkhSy+JzqzMvAE3oNu/19vpRk0fqn8g50qnNYQ5zklHo6 UtN0zzC9LKQqbEwbg/OWaD4fLT30seOIrZMY3UXBOO6tLRRyKMrKKF+cjDSGHHHYQTRx y66w== X-Forwarded-Encrypted: i=1; AHgh+RoOBhTju2HiP8ua5LmnikP5b27tBNciInLV6IN0rKJYI56foGubt5wnxGbQR8FjaCTTQtjsjxDCPtT+M0M=@vger.kernel.org X-Gm-Message-State: AFuF++mBqBPr01kehNWs3J2uqSNUoXbdtzOpDdf2vz4LRRKomRDkZLsN ic7w9Zy2cbKK1tZTdgr4bkrJpGkZmszWNbqyX+JNi98d1TFZStCf2UCC9ppslA== X-Gm-Gg: AR+sD135GjwmqY7GFQJok+rtrH9MYMeDneq91ktKu6+TqgbByDMeGPUtLTXQ8tWunSu ymfNl/iHPqG1DLUuRuE+QRArp8jkgcXX6lY8l2umaJq5wrk5rAWq/xSc5DhOswm6/mQJcBtvY+0 KD6yeGZMWH7oXPr6OQnnYqE92hqCyTU8IkV0xgmKw63fCDzrY3BB3kFA3/JX8fvHVo9nlhrcMoL Dxvi4tzkAH3Iqd5fcGdI2VSjrzh/KDcBosZ969+d24aO6JRKhMkDya0yhTx2t4H++zFlDrPqJHh So7xlKcPATB7mf/4oDKFHW+XUKz9CWamKFkiKyq4bUP+hDEYa1ahOJSGN02GuVJHEhbahB6s0vn bJURJC5UJnr2LBy2oYKIcB2lxKTUp5OhALrq6mUmTGg/RQ8O1o0C8NKYv0Jeir3mG0iJjX1oxS8 w1FwIT0ecjrJn3LOA5pWsFMDxHXxXHZp6sj+wFED6QO0PLjAGMmjDa2stgkKqsWZDpetfQ3qEJ9 VNRNGJTmnbskQ== X-Received: by 2002:a17:906:794b:b0:c20:f871:1041 with SMTP id a640c23a62f3a-c24925a396fmr1654642766b.7.1787576138141; Mon, 24 Aug 2026 05:55:38 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:dea4:599b:49a8:96f5]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c24966f9c9fsm1245403066b.39.2026.08.24.05.55.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 05:55:33 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Biju Das , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org, stable@kernel.org Subject: [PATCH v7 1/9] pwm: rzg2l-gpt: Fix macro used for period/duty cycle conversion Date: Mon, 24 Aug 2026 13:55:07 +0100 Message-ID: <20260824125523.131762-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260824125523.131762-1-biju.das.jz@bp.renesas.com> References: <20260824125523.131762-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Biju Das The driver converts state->period and state->duty_cycle (both in nanoseconds) into timer ticks by multiplying with rate_khz and dividing by USEC_PER_SEC. Since rate_khz is expressed in kHz (cycles per millisecond), the correct divisor is NSEC_PER_MSEC, not USEC_PER_SEC. Both constants evaluate to 1000000, so this is a readability/correctness fix with no functional change, and it keeps the calculation's units self-consistent with the comment describing the overflow bound. Update rzg2l_gpt_calculate_period_or_duty() and rzg2l_gpt_config() accordingly. Cc: stable@kernel.org Fixes: 061f087f5d0b ("pwm: Add support for RZ/G2L GPT") Signed-off-by: Biju Das --- v7: * New patch. --- drivers/pwm/pwm-rzg2l-gpt.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 1569f3ba8c53..108fa99f832d 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -208,13 +208,13 @@ static u64 rzg2l_gpt_calculate_period_or_duty(struct = rzg2l_gpt_chip *rzg2l_gpt, =20 /* * The calculation doesn't overflow an u64 because prescale =E2=89=A4 5 a= nd so - * tmp =3D val << (2 * prescale) * USEC_PER_SEC + * tmp =3D val << (2 * prescale) * NSEC_PER_MSEC * < 2^32 * 2^10 * 10^6 * < 2^32 * 2^10 * 2^20 * =3D 2^62 */ tmp =3D (u64)val << (2 * prescale); - tmp *=3D USEC_PER_SEC; + tmp *=3D NSEC_PER_MSEC; =20 return DIV64_U64_ROUND_UP(tmp, rzg2l_gpt->rate_khz); } @@ -266,7 +266,7 @@ static int rzg2l_gpt_config(struct pwm_chip *chip, stru= ct pwm_device *pwm, u8 prescale; =20 /* Limit period/duty cycle to max value supported by the HW */ - period_ticks =3D mul_u64_u64_div_u64(state->period, rzg2l_gpt->rate_khz, = USEC_PER_SEC); + period_ticks =3D mul_u64_u64_div_u64(state->period, rzg2l_gpt->rate_khz, = NSEC_PER_MSEC); if (period_ticks > RZG2L_MAX_TICKS) period_ticks =3D RZG2L_MAX_TICKS; /* @@ -288,7 +288,7 @@ static int rzg2l_gpt_config(struct pwm_chip *chip, stru= ct pwm_device *pwm, prescale =3D rzg2l_gpt_calculate_prescale(period_ticks); pv =3D rzg2l_gpt_calculate_pv_or_dc(period_ticks, prescale); =20 - duty_ticks =3D mul_u64_u64_div_u64(state->duty_cycle, rzg2l_gpt->rate_khz= , USEC_PER_SEC); + duty_ticks =3D mul_u64_u64_div_u64(state->duty_cycle, rzg2l_gpt->rate_khz= , NSEC_PER_MSEC); if (duty_ticks > period_ticks) duty_ticks =3D period_ticks; dc =3D rzg2l_gpt_calculate_pv_or_dc(duty_ticks, prescale); --=20 2.43.0 From nobody Mon Sep 28 08:47:22 2026 Received: from mail-ej1-f41.google.com (mail-ej1-f41.google.com [209.85.218.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA68A41DEDC for ; Mon, 24 Aug 2026 12:55:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576148; cv=none; b=avXJIq0ZBds2BKRj8XLkCkVrAhApRTE4J1HQQiLfSfMSluSjMwknjnJF+W3MuWszIZhfbWLKR/6XbmjZA+lLDl+s2fuCtCTOAuS/6+Jr0kO3LbI0zFRr8Ump0/d7MDaVyVnFB0gVtCu8T/DQsz3pmA8E5qtHBkMCS4birw+oZyo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576148; c=relaxed/simple; bh=30ZZqhUMeAuyffRRfbVhxV+DdgyX9Ua7fqPyawNZ+7s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=a7OE68kxpfg16FxMR8s7LULJ8PYPvSucf9sKMV0i8JcWd94BN5fpL4NtzqwKV535F3F+wTTt/lW1NJEgjQnTlffm45CPzTcU4s6kqrZ6+fELXxnmpvGfvOAJboYrTAXRndbUDyNxwYv5CylvLMXcQAWk6ZMRgK079jkOHM98zz8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=p9G+UdtL; arc=none smtp.client-ip=209.85.218.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="p9G+UdtL" Received: by mail-ej1-f41.google.com with SMTP id a640c23a62f3a-c207cb16cf5so537078966b.1 for ; Mon, 24 Aug 2026 05:55:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787576145; x=1788180945; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=unn4dgeJwrLigxXrI1YjfTCy5CqWaORoXQIDckl5nvw=; b=p9G+UdtLi2HU58ZBd3+T3C6gbWqirKO74hjGzfuz9gRUWlYFls1aJAgSlpOdvXM9iR Tyr5RC6TmRCP1JOBpHv2pwP1Epdj5ZnXHfSUgNWe/5MXz/ra1I+pG/XZzPZwSsRzWKWN fW417IT5OiK8mD5fErQtnw44R15Yfl/l8ITQb6uZu/Ehvm/VA1rOiHVoyR6mOuOJO3xN 0xXtzBGJ2I2sKpuY25d8MZJQNexUAuhv9K2Bd8NKOZ/L7bMpf1VdgZdRE5Si6n3ovD/H S1ZhVajeQk3D+ok4Y0pSwjVjDW+cPKz2wHrSGeU0H/qT5/RqxreOTzoT6pYrx3ZaaMtE 2Q8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787576145; x=1788180945; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=unn4dgeJwrLigxXrI1YjfTCy5CqWaORoXQIDckl5nvw=; b=duq9nqMsL2b6c8dvZayF2zokJtrkbPSZtU1KiqodGatmG7DZzbdV71n0Gc+mAXZ0UD EtT4ICcPvjoRzK1fNix4AMsAgdREF6d/FQgShkguOzLeE3OFumeglnrEq//RsaJMyUBB 9FTi4nn8mOwyGm8t+gWEgrWR5F9R5PZivK3tmhjFhxqWoVWRkCZ1VgpYGV8i6jRyYjQZ Ngk2bFTl8C6iAd4ImwdmtiXZWwd0PwhvstfaIv3KY/WiIeIOzwJ0Sr6szl5zvt//WSoW ipZDQ60l1G3zDThe29dsf0SorZxYp5UktJoyp4aXhsCC+m0rHfLI2plYs+rJd56Bysm4 Rnpg== X-Forwarded-Encrypted: i=1; AHgh+RoCIGRcoOjjTa70zRkgUxyPNcQkQxrPSPERrFi2Jrf91vgGGs36MHSZzFSRtd0rqZ1zB+y8IBbxqgrQk7o=@vger.kernel.org X-Gm-Message-State: AFuF++l6RQFDjxysSr+urfg5AlYEhKf0WPAfNDXjLlo1300tGYWwgIWu n6ibpdkMR5aDokuWDaRLMzIakgcGv+nV9sIMaCvbp++uywUSjP5rTs7F X-Gm-Gg: AR+sD10fowBkeXNJJVqKHFGynuN4mCAdhEKoj6Xq2fIkTLyNdi9ltfWTnWGvvW4bSMy 00BvRzaHNc5bbvcRSQIrlPBf4U//CBzOLml6wTcvRmCQoyvN+8kglhA9u9pw2QOjfRbLsXqiktY MzhY7trmmU+fawfiG+g4Ba8kau0TtflqAMmwMkVG+6ErlaZT8WZxHm4tFrSZfRV8HdcypY5U1NA hJwQnYiCYGrNw1if/Ln4hb0iWX/9aY8uSVJoLRgzlesd4Qz2cHYuOl75APQ1m5U3ETtZEiLWIDn 7xN1WaPjcWrw+RCwNgxzVbhAwgvpkta7yIY2yc+APbVz/NU+tKSs49t12WSYO6Imav6fuM99vGh 2QoJIYzXOp0IV1+OlNoiC8V56/Ghqqq1YNBo9IP6E2odvXFCedihTjk1GMaYn0hunL8EfXXypLL beWVKazaYFps4yjQ4lsKDqXkMULFS9TaY1250/L6Rii5+EqD1AWydBYfaxpwxh+wqRlBlORJUQW 1k3hDbtaQtlMg== X-Received: by 2002:a17:906:f58b:b0:c1f:8021:deef with SMTP id a640c23a62f3a-c246a390c73mr2711178966b.10.1787576144662; Mon, 24 Aug 2026 05:55:44 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:dea4:599b:49a8:96f5]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c24966f9c9fsm1245403066b.39.2026.08.24.05.55.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 05:55:39 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Biju Das , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v7 2/9] pwm: rzg2l-gpt: Convert to waveform callbacks Date: Mon, 24 Aug 2026 13:55:08 +0100 Message-ID: <20260824125523.131762-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260824125523.131762-1-biju.das.jz@bp.renesas.com> References: <20260824125523.131762-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Migrate the rzg2l-gpt driver from the legacy .get_state/.apply ops to the new waveform callback interface. Introduce struct rzg2l_gpt_waveform to represent a hardware waveform configuration holding the period register value (gtpr), compare/capture register value (gtccr), and prescaler (prescale). Signed-off-by: Biju Das --- v6->v7: * Avoided recalculation of prescale, if is_small_second_period =3D=3D true. * Moved `wfhw->gtccr =3D 0` into the if block in rzg2l_gpt_config(). v5->v6: * Dropped local variables pv and dc from rzg2l_gpt_round_waveform_tohw(). * Dropped blank line in rzg2l_gpt_round_waveform_tohw(). * Moved assignment of rzg2l_gpt->period_ticks[ch] to *_write_waveform(). * Restored clamping of duty_ticks with period_ticks in rzg2l_gpt_round_waveform_tohw(). * Simplified rzg2l_gpt_write_waveform() using else if statement. * Dropped local variable gptr in rzg2l_gpt_write_waveform(). * Moved mutex after early return in rzg2l_gpt_round_waveform_tohw(). v5: * Updated commit description. * Updated rzg2l_gpt_round_waveform_tohw() to initialize gtccr when the period of the second channel is smaller. * Replaced period_ticks with RZG2L_MAX_TICKS for the duty_ticks maximum value check in rzg2l_gpt_round_waveform_tohw(). v4 from [1] [1] https://lore.kernel.org/all/20251208152133.269316-3-biju.das.jz@bp.rene= sas.com/ --- drivers/pwm/pwm-rzg2l-gpt.c | 208 ++++++++++++++++++++++-------------- 1 file changed, 127 insertions(+), 81 deletions(-) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 108fa99f832d..2d40c59106fb 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -86,6 +86,13 @@ struct rzg2l_gpt_chip { u32 channel_enable_count[RZG2L_MAX_HW_CHANNELS]; }; =20 +/* This represents a hardware configuration for one channel */ +struct rzg2l_gpt_waveform { + u32 gtpr; + u32 gtccr; + u8 prescale; +}; + static inline struct rzg2l_gpt_chip *to_rzg2l_gpt_chip(struct pwm_chip *ch= ip) { return pwmchip_get_drvdata(chip); @@ -152,7 +159,8 @@ static void rzg2l_gpt_free(struct pwm_chip *chip, struc= t pwm_device *pwm) rzg2l_gpt->channel_request_count[ch]--; } =20 -static bool rzg2l_gpt_is_ch_enabled(struct rzg2l_gpt_chip *rzg2l_gpt, u8 h= wpwm) +static bool rzg2l_gpt_is_ch_enabled(struct rzg2l_gpt_chip *rzg2l_gpt, u8 h= wpwm, + u32 *gtcr) { u8 ch =3D RZG2L_GET_CH(hwpwm); u32 val; @@ -161,6 +169,9 @@ static bool rzg2l_gpt_is_ch_enabled(struct rzg2l_gpt_ch= ip *rzg2l_gpt, u8 hwpwm) if (!(val & RZG2L_GTCR_CST)) return false; =20 + if (gtcr) + *gtcr =3D val; + val =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTIOR(ch)); =20 return val & RZG2L_GTIOR_OxE(rzg2l_gpt_subchannel(hwpwm)); @@ -219,56 +230,40 @@ static u64 rzg2l_gpt_calculate_period_or_duty(struct = rzg2l_gpt_chip *rzg2l_gpt, return DIV64_U64_ROUND_UP(tmp, rzg2l_gpt->rate_khz); } =20 -static int rzg2l_gpt_get_state(struct pwm_chip *chip, struct pwm_device *p= wm, - struct pwm_state *state) -{ - struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); - - state->enabled =3D rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm); - if (state->enabled) { - u32 sub_ch =3D rzg2l_gpt_subchannel(pwm->hwpwm); - u32 ch =3D RZG2L_GET_CH(pwm->hwpwm); - u8 prescale; - u32 val; - - val =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCR(ch)); - prescale =3D FIELD_GET(RZG2L_GTCR_TPCS, val); - - val =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(ch)); - state->period =3D rzg2l_gpt_calculate_period_or_duty(rzg2l_gpt, val, pre= scale); - - val =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch)); - state->duty_cycle =3D rzg2l_gpt_calculate_period_or_duty(rzg2l_gpt, val,= prescale); - if (state->duty_cycle > state->period) - state->duty_cycle =3D state->period; - } - - state->polarity =3D PWM_POLARITY_NORMAL; - - return 0; -} - static u32 rzg2l_gpt_calculate_pv_or_dc(u64 period_or_duty_cycle, u8 presc= ale) { return min_t(u64, DIV_ROUND_DOWN_ULL(period_or_duty_cycle, 1 << (2 * pres= cale)), U32_MAX); } =20 -/* Caller holds the lock while calling rzg2l_gpt_config() */ -static int rzg2l_gpt_config(struct pwm_chip *chip, struct pwm_device *pwm, - const struct pwm_state *state) +static int rzg2l_gpt_round_waveform_tohw(struct pwm_chip *chip, + struct pwm_device *pwm, + const struct pwm_waveform *wf, + void *_wfhw) { struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); - u8 sub_ch =3D rzg2l_gpt_subchannel(pwm->hwpwm); + struct rzg2l_gpt_waveform *wfhw =3D _wfhw; + bool is_small_second_period =3D false; u8 ch =3D RZG2L_GET_CH(pwm->hwpwm); u64 period_ticks, duty_ticks; - unsigned long pv, dc; - u8 prescale; + + if (wf->period_length_ns =3D=3D 0) { + *wfhw =3D (struct rzg2l_gpt_waveform){ + .gtpr =3D 0, + .gtccr =3D 0, + .prescale =3D 0, + }; + + return 0; + } =20 /* Limit period/duty cycle to max value supported by the HW */ - period_ticks =3D mul_u64_u64_div_u64(state->period, rzg2l_gpt->rate_khz, = NSEC_PER_MSEC); + period_ticks =3D mul_u64_u64_div_u64(wf->period_length_ns, + rzg2l_gpt->rate_khz, NSEC_PER_MSEC); if (period_ticks > RZG2L_MAX_TICKS) period_ticks =3D RZG2L_MAX_TICKS; + + guard(mutex)(&rzg2l_gpt->lock); /* * GPT counter is shared by the two IOs of a single channel, so * prescale and period can NOT be modified when there are multiple IOs @@ -277,29 +272,86 @@ static int rzg2l_gpt_config(struct pwm_chip *chip, st= ruct pwm_device *pwm, if (rzg2l_gpt->channel_request_count[ch] > 1) { u8 sibling_ch =3D rzg2l_gpt_sibling(pwm->hwpwm); =20 - if (rzg2l_gpt_is_ch_enabled(rzg2l_gpt, sibling_ch)) { + if (rzg2l_gpt_is_ch_enabled(rzg2l_gpt, sibling_ch, NULL)) { if (period_ticks < rzg2l_gpt->period_ticks[ch]) - return -EBUSY; + is_small_second_period =3D true; =20 period_ticks =3D rzg2l_gpt->period_ticks[ch]; } + } else { + wfhw->prescale =3D rzg2l_gpt_calculate_prescale(period_ticks); } =20 - prescale =3D rzg2l_gpt_calculate_prescale(period_ticks); - pv =3D rzg2l_gpt_calculate_pv_or_dc(period_ticks, prescale); + wfhw->gtpr =3D rzg2l_gpt_calculate_pv_or_dc(period_ticks, wfhw->prescale); + if (is_small_second_period) { + wfhw->gtccr =3D 0; + return 1; + } =20 - duty_ticks =3D mul_u64_u64_div_u64(state->duty_cycle, rzg2l_gpt->rate_khz= , NSEC_PER_MSEC); + duty_ticks =3D mul_u64_u64_div_u64(wf->duty_length_ns, rzg2l_gpt->rate_kh= z, NSEC_PER_MSEC); if (duty_ticks > period_ticks) duty_ticks =3D period_ticks; - dc =3D rzg2l_gpt_calculate_pv_or_dc(duty_ticks, prescale); + wfhw->gtccr =3D rzg2l_gpt_calculate_pv_or_dc(duty_ticks, wfhw->prescale); =20 - /* - * GPT counter is shared by multiple channels, we cache the period ticks - * from the first enabled channel and use the same value for both - * channels. - */ - rzg2l_gpt->period_ticks[ch] =3D period_ticks; + return 0; +} + +static int rzg2l_gpt_round_waveform_fromhw(struct pwm_chip *chip, + struct pwm_device *pwm, + const void *_wfhw, + struct pwm_waveform *wf) +{ + struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); + const struct rzg2l_gpt_waveform *wfhw =3D _wfhw; + + wf->period_length_ns =3D rzg2l_gpt_calculate_period_or_duty(rzg2l_gpt, wf= hw->gtpr, + wfhw->prescale); + wf->duty_length_ns =3D rzg2l_gpt_calculate_period_or_duty(rzg2l_gpt, wfhw= ->gtccr, + wfhw->prescale); + wf->duty_offset_ns =3D 0; + + return 0; +} + +static int rzg2l_gpt_read_waveform(struct pwm_chip *chip, + struct pwm_device *pwm, + void *_wfhw) +{ + struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); + struct rzg2l_gpt_waveform *wfhw =3D _wfhw; + u32 sub_ch =3D rzg2l_gpt_subchannel(pwm->hwpwm); + u32 ch =3D RZG2L_GET_CH(pwm->hwpwm); + u32 gtcr; + + guard(mutex)(&rzg2l_gpt->lock); + if (rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm, >cr)) { + wfhw->prescale =3D FIELD_GET(RZG2L_GTCR_TPCS, gtcr); + wfhw->gtpr =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(ch)); + wfhw->gtccr =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch)); + if (wfhw->gtccr > wfhw->gtpr) + wfhw->gtccr =3D wfhw->gtpr; + } else { + *wfhw =3D (struct rzg2l_gpt_waveform) { }; + } + + return 0; +} + +static u64 rzg2l_gpt_calculate_cycles(u32 value, u8 prescale) +{ + return (u64)value << (2 * prescale); +} =20 +static int rzg2l_gpt_write_waveform(struct pwm_chip *chip, + struct pwm_device *pwm, + const void *_wfhw) +{ + struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); + const struct rzg2l_gpt_waveform *wfhw =3D _wfhw; + u8 sub_ch =3D rzg2l_gpt_subchannel(pwm->hwpwm); + u8 ch =3D RZG2L_GET_CH(pwm->hwpwm); + + guard(mutex)(&rzg2l_gpt->lock); /* * Counter must be stopped before modifying mode, prescaler, timer * counter and buffer enable registers. These registers are shared @@ -318,14 +370,16 @@ static int rzg2l_gpt_config(struct pwm_chip *chip, st= ruct pwm_device *pwm, =20 /* Select count clock */ rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), RZG2L_GTCR_TPCS, - FIELD_PREP(RZG2L_GTCR_TPCS, prescale)); + FIELD_PREP(RZG2L_GTCR_TPCS, wfhw->prescale)); =20 /* Set period */ - rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTPR(ch), pv); + rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTPR(ch), wfhw->gtpr); + } else if (wfhw->gtpr && (wfhw->gtpr < rzg2l_gpt_read(rzg2l_gpt, RZG2L_GT= PR(ch)))) { + return -EBUSY; } =20 /* Set duty cycle */ - rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch), dc); + rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch), wfhw->gtccr); =20 if (rzg2l_gpt->channel_enable_count[ch] <=3D 1) { /* Set initial value for counter */ @@ -334,44 +388,36 @@ static int rzg2l_gpt_config(struct pwm_chip *chip, st= ruct pwm_device *pwm, /* Set no buffer operation */ rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTBER(ch), 0); =20 - /* Restart the counter after updating the registers */ - rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), - RZG2L_GTCR_CST, RZG2L_GTCR_CST); + if (wfhw->gtpr) + /* Restart the counter after updating the registers */ + rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), + RZG2L_GTCR_CST, RZG2L_GTCR_CST); } =20 - return 0; -} - -static int rzg2l_gpt_apply(struct pwm_chip *chip, struct pwm_device *pwm, - const struct pwm_state *state) -{ - struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); - bool enabled =3D pwm->state.enabled; - int ret; - - if (state->polarity !=3D PWM_POLARITY_NORMAL) - return -EINVAL; - - guard(mutex)(&rzg2l_gpt->lock); - if (!state->enabled) { - if (enabled) - rzg2l_gpt_disable(rzg2l_gpt, pwm); - - return 0; - } - - ret =3D rzg2l_gpt_config(chip, pwm, state); - if (!ret && !enabled) + if (wfhw->gtpr && !rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm, NULL)) { rzg2l_gpt_enable(rzg2l_gpt, pwm); + /* + * GPT counter is shared by multiple channels, we cache the + * period ticks from the first enabled channel and use the same + * value for both channels. + */ + rzg2l_gpt->period_ticks[ch] =3D rzg2l_gpt_calculate_cycles(wfhw->gtpr, + wfhw->prescale); + } else if (!wfhw->gtpr && rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm, = NULL)) { + rzg2l_gpt_disable(rzg2l_gpt, pwm); + } =20 - return ret; + return 0; } =20 static const struct pwm_ops rzg2l_gpt_ops =3D { .request =3D rzg2l_gpt_request, .free =3D rzg2l_gpt_free, - .get_state =3D rzg2l_gpt_get_state, - .apply =3D rzg2l_gpt_apply, + .sizeof_wfhw =3D sizeof(struct rzg2l_gpt_waveform), + .round_waveform_tohw =3D rzg2l_gpt_round_waveform_tohw, + .round_waveform_fromhw =3D rzg2l_gpt_round_waveform_fromhw, + .read_waveform =3D rzg2l_gpt_read_waveform, + .write_waveform =3D rzg2l_gpt_write_waveform, }; =20 static int rzg2l_gpt_probe(struct platform_device *pdev) --=20 2.43.0 From nobody Mon Sep 28 08:47:22 2026 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8FC9141DE03 for ; Mon, 24 Aug 2026 12:55:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576151; cv=none; b=u4hlaXPWuIAEKXDnYbtuTfoBDnM6MFqreV/VU4qt6kGnuPLd2hZ2YVX9GYeXbeWNAojV2viglUu1Lv5mRjkHyAP/2hXnxQin2kdIXfQgeamHEp+XyQTDYqKwbiAwnt6ulALtjw0eI6wIDkojs7EHI0gXkGCAi6ZaBa4B+M/wqZI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576151; c=relaxed/simple; bh=5Kw2fqLXA76dVaAYZYB2XnROiAJp8L2IGAYhDQnqUYY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iihAuRIdOMlKAnFABm3UJEhFAtml++PnGoAnVCRJxYEcSkNc2kfwck1vQVlLK8LR9pevoahXMznQAnB43nYY8hzf7WfxwHrkynIXAQOXS0pk+lwoghOkilpU28TXClKo9cT7mkqGAKUDRrw4xtRQX+oPUbFNPEWG2xw8pQTG1eE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=aoiK/iPd; arc=none smtp.client-ip=209.85.218.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="aoiK/iPd" Received: by mail-ej1-f53.google.com with SMTP id a640c23a62f3a-c207cb16cf5so537087966b.1 for ; Mon, 24 Aug 2026 05:55:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787576148; x=1788180948; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=9TWoXnFxzx1GlYm+udbSxbUhiDJnm5nfEowULKxIdMM=; b=aoiK/iPdyaxPuDbBNPsfqka1Kw3S3mQisMsG62wL5ZL514oleu31UAzueq8aoSQCdY hT6y58+aPLF6RoKuJiYP84sVJ94l4+mtv9mCb8qIezPA336e7b5137HNOtIwCnovN4Zr 2QQtMbyT1fo9e4m3IjbPN2+IxzRw2jYreBmhi/qMSnIiBjcY8XmQa8kyYL59OfYtRd76 a7soNZDwOXRyOblchesbNuPgq+BpwTJkZ3q+kwdCsb/577yMfVxIVbxmiJhMIyAp7DHj rtgIOezBfCxufqeFkDA68mRzdDOlUo9DNoxHZYSQS1GqSuo++lrEX5JGFHzPlK5m40jc oiLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787576148; x=1788180948; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=9TWoXnFxzx1GlYm+udbSxbUhiDJnm5nfEowULKxIdMM=; b=jcSg4RxT1vjqFvoYDiBx8P+AcNsdVEbT4Ri4+IaEbOMQ7LBZJFal1qYRiWjzziGqkR C4DDhWWaHn1NS2LI3z0cJAAYO5gbo3zNz10MwwD3qr7xIWp1+b4iTLq4DKK0BKAeO7xK 6GNYsf9N6+5x5qiaNIwOCW63zloETmmlFOHFWT1uMJPx4+ii6+EjbOm8GrT1mmPkHyJR un6AZXsUbJg7Uwyp4TrbVfO03wXZu++GzxGAR0CXAxLiGSx9yrgG07DRETvI80Wz7NIl fL3cJL6zl5N7n67JIUykt+blVoHdX8/TZg99BiEs1Hp7d1PnWx5FzU6THmzwR0J64VTU Ym3A== X-Forwarded-Encrypted: i=1; AHgh+Ro3APdXF8mtELs5HgMV7gStbVi7xD1S22yo9/Bg99akBL/izLP+OXLGjRGq+CYdet4v22Odo/PzpOY2I1E=@vger.kernel.org X-Gm-Message-State: AFuF++l3cFt+oAcPw1qH/ITrNq/YxFnJ4FWpmaEV/uMVLjI3BXwWuD47 lEDCxOKkRqfbfNWge1A+GfcLCia90IcLCWRaLnnVMEY8ELzRP0QsVPDb X-Gm-Gg: AR+sD10+9JdAHx98garMx3lWeKAKz93KkQPD+gDJbN84YlUJlDl3nvsGfK/HtzxuoLF 2aGWmaTEtn9e5HVI5xfCbQMoFUK6fRscTznI4NXW8tvpGYzZicIAHWgXvAkIthtw9mzsM/qGnVT 4ig6sK3aSymVVRYxcTU8U7e3KtQX4hjpEXf22c8rrOLlFPc4tgx5xIWkl01XJeJGk/pvc9Mzl6w Rd0DwwGSyMrrCFFmd4bLrUSzXdly8tgGwR8EV2ktDp/ywopypCDfrsETYiv3Jtm3zZM4pr8GBFt wuRC0f3HE0LIZBFHuYJcy0DoZPKkk8+1o7tU5SjKoKB7TWVYJILxdbp5uqlLLjFPXlWDK56wKfW MV/JF5eK2o3EVpVvJgPNBNA1RKwKKWP1vMTZGkOkMXzLb5NnrnxkTtBmw3BwaEhgRckS+/AKAsQ +uEiAg6RIusQc/Ktufbe3Ies7sHjnQBEKmXP3YYtislsqY7P0HdTrzNVBZ/mQGhOFJhoajNl6m6 hABdz3cbUYu/w== X-Received: by 2002:a17:907:961d:b0:c24:469d:5653 with SMTP id a640c23a62f3a-c246a653373mr2750262766b.21.1787576147560; Mon, 24 Aug 2026 05:55:47 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:dea4:599b:49a8:96f5]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c24966f9c9fsm1245403066b.39.2026.08.24.05.55.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 05:55:45 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Tommaso Merciai Subject: [PATCH v7 3/9] pwm: rzg2l-gpt: Add info variable to struct rzg2l_gpt_chip Date: Mon, 24 Aug 2026 13:55:09 +0100 Message-ID: <20260824125523.131762-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260824125523.131762-1-biju.das.jz@bp.renesas.com> References: <20260824125523.131762-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Introduce struct rzg2l_gpt_info to capture SoC-specific hardware differences, starting with the gtcr_tpcs field mask for the prescaler bitfield in GTCR. This is needed because the RZ/G3E GPT has a 4-bit prescaler field versus the 3-bit field on RZ/G2L. Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das --- v6->v7: * No change. v5->v6: * No change. v4->v5: * Updated commit description. v3->v4: * Dropped field_{get,prep} as mainline now support it. * Updated commit description. * Retained RZG2L_GTCR_TPCS bit definitons * Replaced gtcr_tpcs_mask->gtcr_tpcs v2->v3: * No change. v1->v2: * Collected tag. --- drivers/pwm/pwm-rzg2l-gpt.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 2d40c59106fb..da2645a42608 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -77,9 +77,14 @@ #define RZG2L_MAX_SCALE_FACTOR 1024 #define RZG2L_MAX_TICKS ((u64)U32_MAX * RZG2L_MAX_SCALE_FACTOR) =20 +struct rzg2l_gpt_info { + u32 gtcr_tpcs; +}; + struct rzg2l_gpt_chip { void __iomem *mmio; struct mutex lock; /* lock to protect shared channel resources */ + const struct rzg2l_gpt_info *info; unsigned long rate_khz; u64 period_ticks[RZG2L_MAX_HW_CHANNELS]; u32 channel_request_count[RZG2L_MAX_HW_CHANNELS]; @@ -325,7 +330,7 @@ static int rzg2l_gpt_read_waveform(struct pwm_chip *chi= p, =20 guard(mutex)(&rzg2l_gpt->lock); if (rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm, >cr)) { - wfhw->prescale =3D FIELD_GET(RZG2L_GTCR_TPCS, gtcr); + wfhw->prescale =3D field_get(rzg2l_gpt->info->gtcr_tpcs, gtcr); wfhw->gtpr =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(ch)); wfhw->gtccr =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch)); if (wfhw->gtccr > wfhw->gtpr) @@ -369,8 +374,8 @@ static int rzg2l_gpt_write_waveform(struct pwm_chip *ch= ip, rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTUDDTYC(ch), RZG2L_GTUDDTYC_UP_COUNTIN= G); =20 /* Select count clock */ - rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), RZG2L_GTCR_TPCS, - FIELD_PREP(RZG2L_GTCR_TPCS, wfhw->prescale)); + rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), rzg2l_gpt->info->gtcr_tpcs, + field_prep(rzg2l_gpt->info->gtcr_tpcs, wfhw->prescale)); =20 /* Set period */ rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTPR(ch), wfhw->gtpr); @@ -439,6 +444,8 @@ static int rzg2l_gpt_probe(struct platform_device *pdev) if (IS_ERR(rzg2l_gpt->mmio)) return PTR_ERR(rzg2l_gpt->mmio); =20 + rzg2l_gpt->info =3D of_device_get_match_data(dev); + rstc =3D devm_reset_control_get_exclusive_deasserted(dev, NULL); if (IS_ERR(rstc)) return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert reset control\= n"); @@ -481,8 +488,12 @@ static int rzg2l_gpt_probe(struct platform_device *pde= v) return 0; } =20 +static const struct rzg2l_gpt_info rzg2l_data =3D { + .gtcr_tpcs =3D RZG2L_GTCR_TPCS, +}; + static const struct of_device_id rzg2l_gpt_of_table[] =3D { - { .compatible =3D "renesas,rzg2l-gpt" }, + { .compatible =3D "renesas,rzg2l-gpt", .data =3D &rzg2l_data }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, rzg2l_gpt_of_table); --=20 2.43.0 From nobody Mon Sep 28 08:47:22 2026 Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 811B1420482 for ; Mon, 24 Aug 2026 12:55:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576156; cv=none; b=Y+XUeCsFbaG+JVD7N1zqlM0tyGtgqUZwaH8QTBadzSfQTsWucZg44WAdZ1kOMe9c7cTGNj57bKAD1JEAfluGYI7llM82iOyRW6VdWX0h275V4NDNJbsn5LlTnKQRqB6VfZUFv1bfnIjstEMCBCY9M5WgrH0taBh+EguBx/9Vfw4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576156; c=relaxed/simple; bh=inSxxGkFCfO+Y6k29RSiQ7EJPmZ0OiQhAM6MDMEWVd0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=l1Yk4HZ46pN3l+ZrlMMiqxREihJfIFaoIiqGlIN6UkI7xJyYDmTQtDTx3fgqzuMR76exqL6nte/n0XGw8pW8+P79/AiY9iJWpxcgSHE1TlmI2Gyg1EWw3xAMJ6EK5hbn3vRma5OJ0pUn5Xel0DbQa2y+ojDal0HTrfNr3xQ5tvU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=KfQsgHUf; arc=none smtp.client-ip=209.85.218.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KfQsgHUf" Received: by mail-ej1-f48.google.com with SMTP id a640c23a62f3a-c160420289bso500798366b.0 for ; Mon, 24 Aug 2026 05:55:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787576151; x=1788180951; darn=vger.kernel.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:from:to:cc:subject :date:message-id:reply-to:content-type; bh=0qaSHwszAWXEDRTaC8hozpR5IBR7Lde/0WoXfRxEwB8=; b=KfQsgHUfITXop2lajZ84edDQE7fOHWkXOps6M3HNtnWfIqPYFFS/6ElIi2Wi1UFa15 2m8TkhufVXvCaHClbU4vXpfFxy8TRbGUcWiloBujW7SCXTXyF7wiFvBTTvSFMEHXZcmy lPm+7qDGibqxRGd8nOqe1INK0/TFsR7VCADLPbdsv88i27oPkmFlbWgPgFzG5d9X35s7 lm/c3jbMBLUUd0z50qNRUwgWSypR6NOqMMMVV1r159kxwXmzXwLA3vxOawvpw70xYvh1 ZtUP86yJGYaWGv+1kx/Nre7r0XiaJXKsG5kLF/kTt28Fi8CsMxwsgKmlJV3UFIlBGhcl kT9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787576151; x=1788180951; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=0qaSHwszAWXEDRTaC8hozpR5IBR7Lde/0WoXfRxEwB8=; b=b4+ZCgmVRgR5bSJ0h9A2s7HPbXbpVQTiRbZQ/TxNqcChlhSn3Kx3RgLBRBy9KKop2H QBh5/NfV5+V74ZBqlR5jBR9v55CPWWmiaKTyrL0NOSOgT8wlHG+dASyf1AP1WMitOWZz TnMiVulrGvCthLz+Z/zkY5pCE8MVz19k4GH3xIlrsRvu5VZdBcgsE/WWw/pg1eH1OPXr RwGw3ZHK0h6QlYxgZA8UN+bOvxuQnuYZ7kmET5j+sALaiweEU13u+O2ocbxq7LClVV59 WKYIrKFsg8FpiURtCKqzcM+/XsKlCwRpB4xrdI80NApDCF4bmNSanrmCDp3FsVrAHqlM 0RLQ== X-Forwarded-Encrypted: i=1; AHgh+RqUGgGAaoWxlE1PFZm43JU/HRz2KkfsSsS1Cby970pcVfh3QIOXpYw/uYrD2rSNOoTeVf8s9y/6DMBlp90=@vger.kernel.org X-Gm-Message-State: AFuF++mqrII5nLE2ffT469m6+X7Bx0yzd83auvhbOaX7Yba3IeYL9YM0 eYm2WPkGlw9IuZpFPySK9iQbF2DDH2Q7dA3JHMLm5yphKh5jaahOljfg X-Gm-Gg: AR+sD13ZlEH3OpNpZk4xc7qoOvnyWkqDm21mupJT+4lL1hSfNMfRnJmA4DYGi74QdQR lRedJQtMESQ935zU4HPZd4hD88bSw5hAhqKfJP0V+MjLlP2OwyiOddmdh/HA2bH7VE7FIzGf4o8 odZ7UyFlJ26YuhDyadNnn1xh7xzH5Nx95jxFNrIz01Q3a3AZJ1A/x46BD1GkqGy436GGDW2QiBA p1tevo+LXSpoxVpvJ3fil1P3ZehiFA/Vm1LObOJTJ+OaeCB5EM5tO+daecaB1Wr0SgECXjBnBeV n6az2WHktOhdqgr6WB5OUnppGB8MFlVCTM1r/8DgGS91q5EVXGDvAv9IhQPoIZMZfWA/yROBNHI TPICt3WkzLs/JJ1IS0MhimQFmhFQty+WlCJcRzGBh8NUXb2d1YJnRJR8pjSaU97BRUbKGj0fjDh x7+6TrgkyNXhEJwNTMqsBQY0pez3rVmNkjX6VR3m0drmsW+02yPjMye2OJb7oP7aok7GKBtn/cn EhaWggrqI+8sQ== X-Received: by 2002:a17:907:1c9e:b0:c16:3187:997e with SMTP id a640c23a62f3a-c246a4ede76mr2752351766b.7.1787576150539; Mon, 24 Aug 2026 05:55:50 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:dea4:599b:49a8:96f5]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c24966f9c9fsm1245403066b.39.2026.08.24.05.55.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 05:55:48 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Biju Das , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org, Tommaso Merciai Subject: [PATCH v7 4/9] pwm: rzg2l-gpt: Add prescale_mult variable to struct rzg2l_gpt_info Date: Mon, 24 Aug 2026 13:55:10 +0100 Message-ID: <20260824125523.131762-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260824125523.131762-1-biju.das.jz@bp.renesas.com> References: <20260824125523.131762-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Biju Das RZ/G3E GPT IP has prescale factor power of 2 where as that of RZ/G2L is 4. Add prescale_mult variable to struct rzg2l_gpt_info for handling this difference. Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das --- v6->v7: * No change. v5->v6: * Dropped extra parameter rzg2l_gpt from rzg2l_gpt_calculate_prescale() in rzg2l_gpt_round_waveform_tohw(). * Updated comment in rzg2l_gpt_calculate_period_or_duty(). v4->v5: * No change. v3->v4: * Updated commit header and description * Renamed prescale_pow_of_two_mult_factor->prescale_mult v2->v3: * No change. v1->v2: * Collected tag. --- drivers/pwm/pwm-rzg2l-gpt.c | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index da2645a42608..fc77c27f0a97 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -79,6 +79,7 @@ =20 struct rzg2l_gpt_info { u32 gtcr_tpcs; + u8 prescale_mult; }; =20 struct rzg2l_gpt_chip { @@ -220,24 +221,29 @@ static void rzg2l_gpt_disable(struct rzg2l_gpt_chip *= rzg2l_gpt, static u64 rzg2l_gpt_calculate_period_or_duty(struct rzg2l_gpt_chip *rzg2l= _gpt, u32 val, u8 prescale) { + const struct rzg2l_gpt_info *info =3D rzg2l_gpt->info; u64 tmp; =20 /* - * The calculation doesn't overflow an u64 because prescale =E2=89=A4 5 a= nd so - * tmp =3D val << (2 * prescale) * NSEC_PER_MSEC + * The calculation doesn't overflow a u64 because, + * prescale =E2=89=A4 5 for info->prescale_mult =3D 2 and so + * tmp =3D val << (info->prescale_mult * prescale) * NSEC_PER_MSEC * < 2^32 * 2^10 * 10^6 * < 2^32 * 2^10 * 2^20 * =3D 2^62 */ - tmp =3D (u64)val << (2 * prescale); + tmp =3D (u64)val << (info->prescale_mult * prescale); tmp *=3D NSEC_PER_MSEC; =20 return DIV64_U64_ROUND_UP(tmp, rzg2l_gpt->rate_khz); } =20 -static u32 rzg2l_gpt_calculate_pv_or_dc(u64 period_or_duty_cycle, u8 presc= ale) +static u32 rzg2l_gpt_calculate_pv_or_dc(const struct rzg2l_gpt_info *info, + u64 period_or_duty_cycle, u8 prescale) { - return min_t(u64, DIV_ROUND_DOWN_ULL(period_or_duty_cycle, 1 << (2 * pres= cale)), + return min_t(u64, + DIV_ROUND_DOWN_ULL(period_or_duty_cycle, + 1 << (info->prescale_mult * prescale)), U32_MAX); } =20 @@ -247,6 +253,7 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chi= p *chip, void *_wfhw) { struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); + const struct rzg2l_gpt_info *info =3D rzg2l_gpt->info; struct rzg2l_gpt_waveform *wfhw =3D _wfhw; bool is_small_second_period =3D false; u8 ch =3D RZG2L_GET_CH(pwm->hwpwm); @@ -287,7 +294,7 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chi= p *chip, wfhw->prescale =3D rzg2l_gpt_calculate_prescale(period_ticks); } =20 - wfhw->gtpr =3D rzg2l_gpt_calculate_pv_or_dc(period_ticks, wfhw->prescale); + wfhw->gtpr =3D rzg2l_gpt_calculate_pv_or_dc(info, period_ticks, wfhw->pre= scale); if (is_small_second_period) { wfhw->gtccr =3D 0; return 1; @@ -296,7 +303,7 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chi= p *chip, duty_ticks =3D mul_u64_u64_div_u64(wf->duty_length_ns, rzg2l_gpt->rate_kh= z, NSEC_PER_MSEC); if (duty_ticks > period_ticks) duty_ticks =3D period_ticks; - wfhw->gtccr =3D rzg2l_gpt_calculate_pv_or_dc(duty_ticks, wfhw->prescale); + wfhw->gtccr =3D rzg2l_gpt_calculate_pv_or_dc(info, duty_ticks, wfhw->pres= cale); =20 return 0; } @@ -342,9 +349,9 @@ static int rzg2l_gpt_read_waveform(struct pwm_chip *chi= p, return 0; } =20 -static u64 rzg2l_gpt_calculate_cycles(u32 value, u8 prescale) +static u64 rzg2l_gpt_calculate_cycles(u32 value, u8 mult, u8 prescale) { - return (u64)value << (2 * prescale); + return (u64)value << (mult * prescale); } =20 static int rzg2l_gpt_write_waveform(struct pwm_chip *chip, @@ -352,6 +359,7 @@ static int rzg2l_gpt_write_waveform(struct pwm_chip *ch= ip, const void *_wfhw) { struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); + const struct rzg2l_gpt_info *info =3D rzg2l_gpt->info; const struct rzg2l_gpt_waveform *wfhw =3D _wfhw; u8 sub_ch =3D rzg2l_gpt_subchannel(pwm->hwpwm); u8 ch =3D RZG2L_GET_CH(pwm->hwpwm); @@ -407,6 +415,7 @@ static int rzg2l_gpt_write_waveform(struct pwm_chip *ch= ip, * value for both channels. */ rzg2l_gpt->period_ticks[ch] =3D rzg2l_gpt_calculate_cycles(wfhw->gtpr, + info->prescale_mult, wfhw->prescale); } else if (!wfhw->gtpr && rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm, = NULL)) { rzg2l_gpt_disable(rzg2l_gpt, pwm); @@ -490,6 +499,7 @@ static int rzg2l_gpt_probe(struct platform_device *pdev) =20 static const struct rzg2l_gpt_info rzg2l_data =3D { .gtcr_tpcs =3D RZG2L_GTCR_TPCS, + .prescale_mult =3D 2, }; =20 static const struct of_device_id rzg2l_gpt_of_table[] =3D { --=20 2.43.0 From nobody Mon Sep 28 08:47:22 2026 Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E653441D237 for ; Mon, 24 Aug 2026 12:55:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576159; cv=none; b=Ee807VQYzaGAYc9Q8+5L+Lr4yNTHEHmz1a/eQRsW1wNiufgnnywXWxm/Dfz0GZ3gP3eqBQiQbO/VX7yIoLvS3JH1CkwzX6SywZcdeQQmAlEpzTYbUucEgiP9HBhoXtLz9M+52P2UBXgrCPBgMPLDpXbAjai6x+X7UkxJrUDVjts= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576159; c=relaxed/simple; bh=WF43uh9DEFG/iSay7LTzpQsb1QG3ediiaYUC29U+SlY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QUC4WOf+EHu3joQ0jQdDVhBsaNEF22CjQG6xoQbq3+t8BAH1EPfYvj5hKN/2+MjAkoya9XO7ymUoYDdbkgDR8AuKwBJ5PP6WbCquj5BdB2ll4uRSiVeBINgBL4j/KkzXnub5+9lfJ6jC0oTqJkR23oqgMFb0LT7ximxf2nJ18o8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=sAB2dEu8; arc=none smtp.client-ip=209.85.208.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="sAB2dEu8" Received: by mail-ed1-f54.google.com with SMTP id 4fb4d7f45d1cf-6a1a546a6bbso6072726a12.1 for ; Mon, 24 Aug 2026 05:55:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787576154; x=1788180954; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=fJRWjVbAapYcETNapM+o3EvgRbyZOp6oMld1UiTr6pE=; b=sAB2dEu8uBu4yUf+7mDfM3aOVwd1snp2dHAacDIZirHzIS4uoCx8N5wwjOemmS1F8s h1k2MrOxjR69v6fuXPM4htaN9copvpPiMMhlk4Yu2F1dFGNWAtXzJTssR+7pZFTVldG8 sXSvS5wUsuo3SCEl9n5n6VzHmtv5GlPNtrEWX6qB/8q1wNpNR2XVEh7SXGH5GvfPetku 5b6QLg8fTUcLZAWDBZ178SArXtmHfU6oaHn6E6AwALEbwHH8xVaMKlNKKSzXE1oMeer1 SzYF3mlWArFIMlzhAIPQdVCis4h/8fCt727XnBHdwTkqMChoURWNPYXGdmyjErmrErO1 ioWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787576154; x=1788180954; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=fJRWjVbAapYcETNapM+o3EvgRbyZOp6oMld1UiTr6pE=; b=qmniAmqjbJJMBkDrg6YCwQ12hoPyt48KOihxOkZbtVNPyn5jqJ7+p965xceR1mz0PI F6viRKl+Ryg9aOPXTB0yX2SFRjd3cRO1XeOm3/BoMqe892rwSt6ktIEiI61zUqHuzkfb JiJBNFoq91Gv2j/YCRKspY5xdkujAL6xJQ+DMrJKy9YsziNMdcYxBXFTdYxxWgoow5QF 3JcgqTI2UVDPPLqtJMM+Z0IH/HCOjXx/6Em2cxKyhIb/CSm0prNUxruqiqcaKo0rmPV6 a+oMM544362D3kaLVRqySc2hgatixeldukxGk4Z6DiypIwrqPvINARu10eUh0FQIcCG6 kHoA== X-Forwarded-Encrypted: i=1; AHgh+RoYTG+ClBenqgjVgNAa0cRKpcd7hw1JWTH44JuvhWI13JnVAnMqMRv9CfrM8NThs6loPp8FDqmDAH2UhAc=@vger.kernel.org X-Gm-Message-State: AFuF++kXCzR2SJK3RtfZ5EP3oZznvOlicwzN2Tle7rBq9ptQiSy6K8k7 fTSRLI1TcUN9FdHGoljH7nv9jyGNqtUviQ9ULZOPMSHvn0F2YU41Oj8TIkd2IQ== X-Gm-Gg: AR+sD10I/QSGgVXOBaFnLju37hAUEDYIP65AIwi7mU2Efy111YuLe4xCyEUMmBC4mMX ZCt8agkAy92lBET6JiN9tXAiBsIgfPSeE29wsJfdxzNM+l85uh72V7RG8VpSKG3hAUQm9I3tx3+ 1FRv2O52IT69gAOcwr5WDW8bEexN9XeZzbXbY44hDS3luplzh/8FqXeEgFBO84dpxd/39IJUual wiDpQ5PHsLD+79FZJ6XvyH1CaYIY60szPu8uWgcVzAPOBR/rpCGrKEn0Gp7miLHruL8e6kt6y6p 9kU1jW78nKPeuFjMb/pBx5rtDc3fRAEOnAQzcV/er/nCGawSNZjqNHZiTP/m7xMzD6N3gLa16z5 yMdWObLO0yoEjLlPCx2O20FB979mUF9gPKMq61rrclLRkugI3Onb5fMwnq1gYJRjUWb1zj/9LJb K1MMHOuAzXtTB6MbfUkMWJrdCtrOJIKWQuYfVFpwNK1MMElbyhTifgQ4Ax9bELT5i5XrdTg/870 yjL1KOhCiqY+DWxZ5D0sd+G X-Received: by 2002:a17:907:3cc6:b0:c17:cf99:6154 with SMTP id a640c23a62f3a-c246a6176b4mr2915739466b.16.1787576154265; Mon, 24 Aug 2026 05:55:54 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:dea4:599b:49a8:96f5]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c24966f9c9fsm1245403066b.39.2026.08.24.05.55.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 05:55:52 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Biju Das , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org, Tommaso Merciai Subject: [PATCH v7 5/9] pwm: rzg2l-gpt: Add calculate_prescale() callback to struct rzg2l_gpt_info Date: Mon, 24 Aug 2026 13:55:11 +0100 Message-ID: <20260824125523.131762-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260824125523.131762-1-biju.das.jz@bp.renesas.com> References: <20260824125523.131762-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The RZ/G2L GPT prescaler steps are continuous powers of 4, while RZ/G3E uses powers of 2 but with a discontinuous sequence. Add a calculate_prescale function pointer to struct rzg2l_gpt_info to allow per-SoC prescaler selection logic. Replace the direct call to rzg2l_gpt_calculate_prescale() in rzg2l_gpt_round_waveform_tohw() with an indirect call through info->calculate_prescale(). Wire the existing rzg2l_gpt_calculate_prescale() into rzg2l_data to preserve current RZ/G2L behaviour. Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das --- v6->v7: * No change. v5->v6: * No change. v4->v5: * Updated commit description. v3->v4: * No change. v2->v3: * No change. v1->v2: * Collected tag. --- drivers/pwm/pwm-rzg2l-gpt.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index fc77c27f0a97..2a1c5a22484b 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -78,6 +78,7 @@ #define RZG2L_MAX_TICKS ((u64)U32_MAX * RZG2L_MAX_SCALE_FACTOR) =20 struct rzg2l_gpt_info { + u8 (*calculate_prescale)(u64 period); u32 gtcr_tpcs; u8 prescale_mult; }; @@ -291,7 +292,7 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chi= p *chip, period_ticks =3D rzg2l_gpt->period_ticks[ch]; } } else { - wfhw->prescale =3D rzg2l_gpt_calculate_prescale(period_ticks); + wfhw->prescale =3D info->calculate_prescale(period_ticks); } =20 wfhw->gtpr =3D rzg2l_gpt_calculate_pv_or_dc(info, period_ticks, wfhw->pre= scale); @@ -498,6 +499,7 @@ static int rzg2l_gpt_probe(struct platform_device *pdev) } =20 static const struct rzg2l_gpt_info rzg2l_data =3D { + .calculate_prescale =3D rzg2l_gpt_calculate_prescale, .gtcr_tpcs =3D RZG2L_GTCR_TPCS, .prescale_mult =3D 2, }; --=20 2.43.0 From nobody Mon Sep 28 08:47:22 2026 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEA5C41D643 for ; Mon, 24 Aug 2026 12:55:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576162; cv=none; b=pfdOe9n45NrEtS3tJ2qvkTyOn3KsBKmlYY8WoCkixeYM0iiW2pY73wJ1B52MRLrgmjv98cFj8NZ8iUAAXDFd/Iwg6A4MKJxkRRCn+bEDEHR6LhXI3VE087oFtapVAfWKGPP26rzdjNpyewlgZbZZX66RMvlg6iNHt2obIYwJJic= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576162; c=relaxed/simple; bh=QFpkWmzU4vBnG1dAZVV86MZS14GWpeR0Dc0amvK+2ro=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Stq0QEJzVKq++hJEIQ7Quarec6xwGG/hHqJCbVkbDNrJ96RxQrzMTZP8If3Tt7CUJkGPp7jUIrUVFd/ilcDQGAZ+Q7+dLWsTDDqXny4iFLaINf+vdlLQLtAxx5IYNjkx3t7D6GtHn/Y9u/GFNPd2Gq6Hh6AOVma0laN870dHRMw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Ft60fVht; arc=none smtp.client-ip=209.85.218.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Ft60fVht" Received: by mail-ej1-f53.google.com with SMTP id a640c23a62f3a-c247f6687dcso388075766b.2 for ; Mon, 24 Aug 2026 05:55:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787576157; x=1788180957; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=PmyKnXKnBsvM8viq8kmX6SvEPZk4puMXMItNZHFn0aM=; b=Ft60fVhtdfU2PrdDEi3Edt1ghJkCDhs/Y1T7tktiI/sWXTvZ8S9D7xDrUiTSq5VJtB 86W5aKT76Iv1kwnyFv3YJ5Djg21m/AKWIfPdKVyt3i2lvsnj/2z8Pv+YpAYenjhONnRX 7xAdkjj9hqcFfzznZTauLe+hETm217ky2qfiqHwOTfGt6g8uKs+FlycZFqdDL52Wof7h YwWiYxAig+08Z11+nrSfbykNzsdU6JYom3ERYMopwt2oWzecshqsFXx7DlW3hW42nCjC 9EVr7TaqgjWZqyJrSVz7s10enl8IeTcW6JMBcxr9bXT18UffFWu9/b1dF8e/Cs+AVK5g dC+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787576157; x=1788180957; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=PmyKnXKnBsvM8viq8kmX6SvEPZk4puMXMItNZHFn0aM=; b=qOM0m4R3IYePyAJ/bXmtoMhI9n8KqrHaqM33LJvv8/8v5LrjPKN/vufc1K5gbWRaxl KXtsxbvMH0Yuql3mCmLsc9sCXWbluz6/UnXn9aN27Kl4p3AGIOfLmX+DYM7duHgE/Hbb fFPGzMyEALBuPxY32neJJLRk7D8E2deop0io1R6Uo9fbMFozNcCxYzrDRcLkQxQV9l25 cuqI8TlH4JflzEfqoQi4xgEvPvG8VWeoYlK4IRc5aP2fTpK4I/g+exCcRI+62O6JapWa ncBtVJEb9MYIY9Wa2zGt5HM+nAH6AkRz+I4IPsrnJoW/2J1ksQhcFT0gfCjqYOnrDmxQ m2PA== X-Forwarded-Encrypted: i=1; AHgh+RoCu/qHlceSnpaVSJ1GaLiXb3WWKKwBwZROol/TBWimdaYVaTkctMlb7UPDREa8qNB5SBtDayACTANiegg=@vger.kernel.org X-Gm-Message-State: AFuF++ksWBUH8uClIRnG2LajfLK0Ydq8ShL1clb9LnmP3/2IYSucehlL V4N5aAi5AOlL3pruE9k6JrYhMHo9l4XNfic/mHMlPR7z2tn6zM4Pbe/RDu2aWg== X-Gm-Gg: AR+sD12hzLQpOCauWQoyH8EKzzpMPVHG0FHgzsw10yOwc5cBScc2JEkJavai0Nzy3sS /KkF8iEqFDjEisJyOX/L3xOrSIPFolIKkcf9uXGshhapDlWX8WuZxl0HovIII+bl8U74mnz4fwF PPxFZjCINthhqtMxXmU0vFV1Upz2i2ZZo8ksEapBGrg7fqgUOqyZ+7NFAMdyYX/Of9Mxuvr7YhC AN8YnY9b1Hr17sQPH0sdCVnAF5VKtQVzmGsAJCbyvAA6OugefvHePFW9nNT4A5uue/awqD5H0qK p98sMf2ivMw0BSNxi3I6vZsPm80kjXkZY9r2iP6DhnKNj+VAWMLAHHcJq6QxTRWQAehlHWpxtuq e12eq+lbKkQP2QC1RhPI2GXz3w6wUi8OXLRfqAbKAoyn2jgXh/mjpjmdRInYeVjNXHr3fnVTiaN 8JgrUV+FPV8Wy2Ezp8W9niNxgX+dLGSQ3tUSHqdNQFYEGpvqTsmRaGYgq9TFxyLVyvuHsb3sBp9 iTUPIuhIjUqcA== X-Received: by 2002:a17:907:6d1d:b0:c1f:983f:d8a with SMTP id a640c23a62f3a-c246a6b2c64mr2966368066b.24.1787576156977; Mon, 24 Aug 2026 05:55:56 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:dea4:599b:49a8:96f5]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c24966f9c9fsm1245403066b.39.2026.08.24.05.55.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 05:55:55 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v7 6/9] dt-bindings: pwm: Document RZ/G3E GPT support Date: Mon, 24 Aug 2026 13:55:12 +0100 Message-ID: <20260824125523.131762-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260824125523.131762-1-biju.das.jz@bp.renesas.com> References: <20260824125523.131762-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Document support for the GPT found on the Renesas RZ/G3E (R9A09G047) SoC. The GPT is a 32-bit timer with 16 hardware channels (GPT0: 8 channel and GPT1: 8channels). The hardware supports simultaneous control of all channels. PWM waveforms can be generated by controlling the up-counter, downcounter, or up- and down-counter. Reviewed-by: Rob Herring (Arm) Signed-off-by: Biju Das --- v6->v7: * No change. v5->v6: * No change. v4->v5: * No change. v3->v4: * No change. v2->v3: * Added Rb tag from Rob. v1->v2: * Created separate document for RZ/G3E GPT. * Updated commit header and description. --- .../bindings/pwm/renesas,rzg3e-gpt.yaml | 323 ++++++++++++++++++ 1 file changed, 323 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt= .yaml diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml b= /Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml new file mode 100644 index 000000000000..cb4ffab5f47f --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml @@ -0,0 +1,323 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/renesas,rzg3e-gpt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G3E General PWM Timer (GPT) + +maintainers: + - Biju Das + +description: | + RZ/G3E General PWM Timer (GPT) composed of 16 channels with 32-bit + timer. It supports the following functions + * 32 bits x 16 channels. + * Up-counting or down-counting (saw waves) or up/down-counting + (triangle waves) for each counter. + * Clock sources independently selectable for each channel. + * Four I/O pins per channel. + * Two output compare/input capture registers per channel. + * For the two output compare/input capture registers of each channel, + four registers are provided as buffer registers and are capable of + operating as comparison registers when buffering is not in use. + * In output compare operation, buffer switching can be at crests or + troughs, enabling the generation of laterally asymmetric PWM waveforms. + * Registers for setting up frame cycles in each channel (with capability + for generating interrupts at overflow or underflow) + * Generation of dead times in PWM operation. + * Synchronous starting, stopping and clearing counters for arbitrary + channels. + * Count start, count stop, count clear, up-count, down-count, or input + capture operation in response to a maximum of 8 ELC events. + * Count start, count stop, count clear, up-count, down-count, or input + capture operation in response to the status of two input pins. + * Starting, clearing, stopping and up/down counters in response to a + maximum of four external triggers. + * Output pin disable function by detected short-circuits between output + pins. + * A/D converter start triggers can be generated. + * Compare match A to F event and overflow/underflow event can be output + to the ELC. + * Enables the noise filter for input capture. + * Logical operation between the channel output. + +properties: + compatible: + items: + - const: renesas,r9a09g047-gpt # RZ/G3E + + reg: + maxItems: 1 + + '#pwm-cells': + const: 3 + + interrupts: + items: + - description: Input capture/compare match of the GTCCRA for channel= GPT{0,1}.0 + - description: Input capture/compare match of the GTCCRB for channel= GPT{0,1}.0 + - description: Compare match with the GTCCRC for channel GPT{0,1}.0 + - description: Compare match with the GTCCRD for channel GPT{0,1}.0 + - description: Compare match with the GTCCRE for channel GPT{0,1}.0 + - description: Compare match with the GTCCRF for channel GPT{0,1}.0 + - description: A and B both high interrupt for channel GPT{0,1}.0 + - description: A and B both low interrupt for channel GPT{0,1}.0 + - description: Input capture/compare match of the GTCCRA for channel= GPT{0,1}.1 + - description: Input capture/compare match of the GTCCRB for channel= GPT{0,1}.1 + - description: Compare match with the GTCCRC for channel GPT{0,1}.1 + - description: Compare match with the GTCCRD for channel GPT{0,1}.1 + - description: Compare match with the GTCCRE for channel GPT{0,1}.1 + - description: Compare match with the GTCCRF for channel GPT{0,1}.1 + - description: A and B both high interrupt for channel GPT{0,1}.1 + - description: A and B both low interrupt for channel GPT{0,1}.1 + - description: Input capture/compare match of the GTCCRA for channel= GPT{0,1}.2 + - description: Input capture/compare match of the GTCCRB for channel= GPT{0,1}.2 + - description: Compare match with the GTCCRC for channel GPT{0,1}.2 + - description: Compare match with the GTCCRD for channel GPT{0,1}.2 + - description: Compare match with the GTCCRE for channel GPT{0,1}.2 + - description: Compare match with the GTCCRF for channel GPT{0,1}.2 + - description: A and B both high interrupt for channel GPT{0,1}.2 + - description: A and B both low interrupt for channel GPT{0,1}.2 + - description: Input capture/compare match of the GTCCRA for channel= GPT{0,1}.3 + - description: Input capture/compare match of the GTCCRB for channel= GPT{0,1}.3 + - description: Compare match with the GTCCRC for channel GPT{0,1}.3 + - description: Compare match with the GTCCRD for channel GPT{0,1}.3 + - description: Compare match with the GTCCRE for channel GPT{0,1}.3 + - description: Compare match with the GTCCRF for channel GPT{0,1}.3 + - description: A and B both high interrupt for channel GPT{0,1}.3 + - description: A and B both low interrupt for channel GPT{0,1}.3 + - description: Input capture/compare match of the GTCCRA for channel= GPT{0,1}.4 + - description: Input capture/compare match of the GTCCRB for channel= GPT{0,1}.4 + - description: Compare match with the GTCCRC for channel GPT{0,1}.4 + - description: Compare match with the GTCCRD for channel GPT{0,1}.4 + - description: Compare match with the GTCCRE for channel GPT{0,1}.4 + - description: Compare match with the GTCCRF for channel GPT{0,1}.4 + - description: A and B both high interrupt for channel GPT{0,1}.4 + - description: A and B both low interrupt for channel GPT{0,1}.4 + - description: Input capture/compare match of the GTCCRA for channel= GPT{0,1}.5 + - description: Input capture/compare match of the GTCCRB for channel= GPT{0,1}.5 + - description: Compare match with the GTCCRC for channel GPT{0,1}.5 + - description: Compare match with the GTCCRD for channel GPT{0,1}.5 + - description: Compare match with the GTCCRE for channel GPT{0,1}.5 + - description: Compare match with the GTCCRF for channel GPT{0,1}.5 + - description: A and B both high interrupt for channel GPT{0,1}.5 + - description: A and B both low interrupt for channel GPT{0,1}.5 + - description: Input capture/compare match of the GTCCRA for channel= GPT{0,1}.6 + - description: Input capture/compare match of the GTCCRB for channel= GPT{0,1}.6 + - description: Compare match with the GTCCRC for channel GPT{0,1}.6 + - description: Compare match with the GTCCRD for channel GPT{0,1}.6 + - description: Compare match with the GTCCRE for channel GPT{0,1}.6 + - description: Compare match with the GTCCRF for channel GPT{0,1}.6 + - description: A and B both high interrupt for channel GPT{0,1}.6 + - description: A and B both low interrupt for channel GPT{0,1}.6 + - description: Input capture/compare match of the GTCCRA for channel= GPT{0,1}.7 + - description: Input capture/compare match of the GTCCRB for channel= GPT{0,1}.7 + - description: Compare match with the GTCCRC for channel GPT{0,1}.7 + - description: Compare match with the GTCCRD for channel GPT{0,1}.7 + - description: Compare match with the GTCCRE for channel GPT{0,1}.7 + - description: Compare match with the GTCCRF for channel GPT{0,1}.7 + - description: A and B both high interrupt for channel GPT{0,1}.7 + - description: A and B both low interrupt for channel GPT{0,1}.7 + + interrupt-names: + items: + - const: gtcia0 + - const: gtcib0 + - const: gtcic0 + - const: gtcid0 + - const: gtcie0 + - const: gtcif0 + - const: gtcih0 + - const: gtcil0 + - const: gtcia1 + - const: gtcib1 + - const: gtcic1 + - const: gtcid1 + - const: gtcie1 + - const: gtcif1 + - const: gtcih1 + - const: gtcil1 + - const: gtcia2 + - const: gtcib2 + - const: gtcic2 + - const: gtcid2 + - const: gtcie2 + - const: gtcif2 + - const: gtcih2 + - const: gtcil2 + - const: gtcia3 + - const: gtcib3 + - const: gtcic3 + - const: gtcid3 + - const: gtcie3 + - const: gtcif3 + - const: gtcih3 + - const: gtcil3 + - const: gtcia4 + - const: gtcib4 + - const: gtcic4 + - const: gtcid4 + - const: gtcie4 + - const: gtcif4 + - const: gtcih4 + - const: gtcil4 + - const: gtcia5 + - const: gtcib5 + - const: gtcic5 + - const: gtcid5 + - const: gtcie5 + - const: gtcif5 + - const: gtcih5 + - const: gtcil5 + - const: gtcia6 + - const: gtcib6 + - const: gtcic6 + - const: gtcid6 + - const: gtcie6 + - const: gtcif6 + - const: gtcih6 + - const: gtcil6 + - const: gtcia7 + - const: gtcib7 + - const: gtcic7 + - const: gtcid7 + - const: gtcie7 + - const: gtcif7 + - const: gtcih7 + - const: gtcil7 + + clocks: + items: + - description: Core clock (PCLKD) + - description: Bus clock (PCLKA) + + clock-names: + items: + - const: core + - const: bus + + power-domains: + maxItems: 1 + + resets: + items: + - description: Reset for bus clock (PCLKA/PCLKD) + - description: Reset for core clock (PCLKD) + + reset-names: + items: + - const: rst_p + - const: rst_s + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - resets + - reset-names + +allOf: + - $ref: pwm.yaml# + +additionalProperties: false + +examples: + - | + #include + #include + + pwm@13010000 { + compatible =3D "renesas,r9a09g047-gpt"; + reg =3D <0x13010000 0x10000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "gtcia0", "gtcib0", "gtcic0", "gtcid0", + "gtcie0", "gtcif0", "gtcih0", "gtcil0", + "gtcia1", "gtcib1", "gtcic1", "gtcid1", + "gtcie1", "gtcif1", "gtcih1", "gtcil1", + "gtcia2", "gtcib2", "gtcic2", "gtcid2", + "gtcie2", "gtcif2", "gtcih2", "gtcil2", + "gtcia3", "gtcib3", "gtcic3", "gtcid3", + "gtcie3", "gtcif3", "gtcih3", "gtcil3", + "gtcia4", "gtcib4", "gtcic4", "gtcid4", + "gtcie4", "gtcif4", "gtcih4", "gtcil4", + "gtcia5", "gtcib5", "gtcic5", "gtcid5", + "gtcie5", "gtcif5", "gtcih5", "gtcil5", + "gtcia6", "gtcib6", "gtcic6", "gtcid6", + "gtcie6", "gtcif6", "gtcih6", "gtcil6", + "gtcia7", "gtcib7", "gtcic7", "gtcid7", + "gtcie7", "gtcif7", "gtcih7", "gtcil7"; + clocks =3D <&cpg CPG_MOD 0x31>, <&cpg CPG_MOD 0x31>; + clock-names =3D "core", "bus"; + power-domains =3D <&cpg>; + resets =3D <&cpg 0x59>, <&cpg 0x5a>; + reset-names =3D "rst_p", "rst_s"; + #pwm-cells =3D <3>; + }; --=20 2.43.0 From nobody Mon Sep 28 08:47:22 2026 Received: from mail-ed1-f46.google.com (mail-ed1-f46.google.com [209.85.208.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0B3841D624 for ; Mon, 24 Aug 2026 12:56:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576163; cv=none; b=FRrzyngRRBTuITe8AoCrA7RLA7qScW8aX2JpDEIZmJ9h9oq2TxZMCHRCJfZBYLNTAyDUto1iAdu1bst2Z9/us9EDVJd7kkRgwD8On4inG+tx38YDBGq1UqbegWjC6K42zfEqqj7p0II5qk6Ay1ZCI/gUZBP4S3LwcHij7btKm8U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576163; c=relaxed/simple; bh=sffgno/gC67sZdNEFUdmg5sB/+7lWuFA41I2RUKvMOk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XUPYXeNi2NZuQtOF4uuZEfxk4fw4nKh/J2EPklttqQblGZIgxagxYet7sd7f/1LFT84VSmugNjK/F1N7ZQie8Lw18sGoklz0yYxqI8gZK00YOdt6OdnO3cDixURPxxMhJeKNv7XUlWvK2pqSY7z8gsDBg+0OUhrB86iMiGJgYAM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=KbWcOsSp; arc=none smtp.client-ip=209.85.208.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KbWcOsSp" Received: by mail-ed1-f46.google.com with SMTP id 4fb4d7f45d1cf-6983d3dae7aso7184859a12.0 for ; Mon, 24 Aug 2026 05:56:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787576158; x=1788180958; darn=vger.kernel.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:from:to:cc:subject :date:message-id:reply-to:content-type; bh=lfMn5bcQJYdZF8OAr9fNY6Kn2fwXmO0B8zGw+NRHLnY=; b=KbWcOsSpeYpYxIstU0AneD/VuHiRpVbmF+Sit6SE0UqQO8LKC55QXKN5UQYWyKeJ6f 8Ie9SmcF3e8wzLs3PWwU+JglaYCkTyJ2tASZhw94PX4zd5cm/rlDUjcqj+yVaX+xvJNe UamsuU607hE4NKN0OdDQBSm2FLbYGyogUEiWMseR0KS9/Mc9hyy8rPxHngGAIc4tvF/4 bu8r128vSlXmTlgFZsDDffWrjxj/JQ3tzAeDrsspKpThgo/Ff2qjA28/yspvf2vuuQ+B XvbgSQ+p/ChYat7pT/Lhq0lwaNz1FWYKeCUu3YJDKMR0WoYCYjHi4y2k+RsmWCoN+YU6 bllg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787576158; x=1788180958; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=lfMn5bcQJYdZF8OAr9fNY6Kn2fwXmO0B8zGw+NRHLnY=; b=U03/r5WsOYFuP3GS2/3Vd7Eyqq48AKxaJHrd9PDq3jHBe0r5DIxJcnIf9mSW8is8Vt IVdWT7YbCRZ/dFlJnFPSdNoAfF6BUMjFhKif5DTxud9fUm5nn8l5h6kInu8zsEYRoHZO G/c27FthNzq6nxh7ZPN4FofcboVrjdXmLhCAkc0T5AqyzHFQy5d8EZRg+H9zQVgMHJ4X h84Hon8CAOgr7eh8++2fyyutDeMptQnbwlNSZZ9Jyqz3M2KDAM18PUOtOMcQLd0tcGgc /MVDaZixqtpUQ7pud6Rzpe0B2/w8DnhtpfxHn3oTJ3S8TsK+L6sJfVYGXTzApRAYDo7N GDhA== X-Forwarded-Encrypted: i=1; AHgh+RrYufk1Vh/S95GuOm8obyW/m1qXzXBLMZA8qRlzh6IKaAd4eWULyTBUw0HOqKsJtpLZ2z1VVVbWcGgYEGg=@vger.kernel.org X-Gm-Message-State: AFuF++mChvho4HxHPSJMoz/SZReA3K1J1uHd2JHUWVNLTInJTrVk59fh VPztVj0mPUPU+euV2trrfG6CDiv29hVXCMHIaTDL+UdKAQ3EHTMTUWnT X-Gm-Gg: AR+sD13s6R6I6qwDi8IbH+mdM1i9SUdNS4OHYAp6dab5rsyMA6INu68qYhOcteehS4v 6ePcBCN68mfaxpUf1yFTvk603YCb4ft8TQvdWvBYilJaJnD+2cLyIu9HbRPwem5/ICK+PKSRs9Y rYEdv+evCMk1CvuFGSSzE+/HkhsKUGMrbZrBKoAcLB0ybWnuMwPhMAbYqhQJX/Ie5qdBtywZFJb PXiAd9GsRUvATU9rv1dQhZxHclCd6h9jRhMZREoHKiCCykVju+jtZQKkOElJI/h0ZT2GwvPmDTW iyZC/mz04F/wX3Hb/Jnf66UeeADvFvySKObiz/RAZQF6yq4hsFID2xvkdwxqZ6tL3WDajh76j3P Bcwql8ZU26CuBIvUU5xZSTjqxR4e9wR77BT0qu0hj3oK0kOl+mxI/rnFnf4yuvsM27q1MFIfGra h9ahR7t/x8mgK2Hh+vEgPHDVWrp4cLhmJCvHNkZnQWn/N+kAhGoVRDtrAogHRJLXgW04ccZTUs7 n+0aR2evefJKQ== X-Received: by 2002:a17:907:1c19:b0:c16:785:cfb6 with SMTP id a640c23a62f3a-c246d5b7ebemr2557044366b.3.1787576158306; Mon, 24 Aug 2026 05:55:58 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:dea4:599b:49a8:96f5]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c24966f9c9fsm1245403066b.39.2026.08.24.05.55.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 05:55:57 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Tommaso Merciai Subject: [PATCH v7 7/9] pwm: rzg2l-gpt: Add RZ/G3E support Date: Mon, 24 Aug 2026 13:55:13 +0100 Message-ID: <20260824125523.131762-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260824125523.131762-1-biju.das.jz@bp.renesas.com> References: <20260824125523.131762-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Biju Das Add RZ/G3E GPT support. It has multiple clocks and resets compared to RZ/G2L. Also prescale field width and factor for calculating prescale are different. Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das --- v6->v7: * No change. v5->v6: * Updated rzg3e_gpt_calculate_prescale(). * Updated comment in rzg2l_gpt_calculate_period_or_duty(). v4->v5: * No change. v3->v4: * Added RZG3E_GTCR_TPCS bit definition for RZ/G3E and added to rzg3e_data. v2->v3: * No change. v1->v2: * Added link to hardware manual * Updated limitation section * Collected tag=20 --- drivers/pwm/pwm-rzg2l-gpt.c | 45 ++++++++++++++++++++++++++++++++++--- 1 file changed, 42 insertions(+), 3 deletions(-) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 2a1c5a22484b..c61c648f71a8 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -6,15 +6,21 @@ * * Hardware manual for this IP can be found here * https://www.renesas.com/eu/en/document/mah/rzg2l-group-rzg2lc-group-use= rs-manual-hardware-0?language=3Den + * https://www.renesas.com/en/document/mah/rzg3e-group-users-manual-hardwa= re * * Limitations: * - Counter must be stopped before modifying Mode and Prescaler. * - When PWM is disabled, the output is driven to inactive. * - While the hardware supports both polarities, the driver (for now) * only handles normal polarity. - * - General PWM Timer (GPT) has 8 HW channels for PWM operations and - * each HW channel have 2 IOs. + * - For RZ/G2L, the General PWM Timer (GPT) has 8 HW channels for PWM + operations and each HW channel have 2 IOs (GTIOCn{A, B}). * - Each IO is modelled as an independent PWM channel. + * - For RZ/G3E, the General PWM Timer (GPT) has 16 HW channels for PWM + operations (GPT0: 8 channels, GPT1: 8 Channels) and each HW channel + have 4 IOs (GTIOCn{A,AN,B,BN}). The 2 extra IOs GTIOCnAN and GTIOCnBN + in RZ/G3E are anti-phase signals of GTIOCnA and GTIOCnB. The + anti-phase signals of RZ/G3E are not modelled as PWM channel. * - When both channels are used, disabling the channel on one stops the * other. * - When both channels are used, the period of both IOs in the HW channel @@ -47,6 +53,7 @@ #define RZG2L_GTCR_CST BIT(0) #define RZG2L_GTCR_MD GENMASK(18, 16) #define RZG2L_GTCR_TPCS GENMASK(26, 24) +#define RZG3E_GTCR_TPCS GENMASK(26, 23) =20 #define RZG2L_GTCR_MD_SAW_WAVE_PWM_MODE FIELD_PREP(RZG2L_GTCR_MD, 0) =20 @@ -146,6 +153,22 @@ static u8 rzg2l_gpt_calculate_prescale(u64 period_tick= s) return prescale; } =20 +static u8 rzg3e_gpt_calculate_prescale(u64 period_ticks) +{ + u32 prescaled_period_ticks; + u8 prescale; + + prescaled_period_ticks =3D period_ticks >> 32; + if (prescaled_period_ticks > 64 && prescaled_period_ticks < 256) + prescale =3D 8; + else if (prescaled_period_ticks >=3D 256) + prescale =3D 10; + else + prescale =3D fls(prescaled_period_ticks); + + return prescale; +} + static int rzg2l_gpt_request(struct pwm_chip *chip, struct pwm_device *pwm) { struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); @@ -227,7 +250,8 @@ static u64 rzg2l_gpt_calculate_period_or_duty(struct rz= g2l_gpt_chip *rzg2l_gpt, =20 /* * The calculation doesn't overflow a u64 because, - * prescale =E2=89=A4 5 for info->prescale_mult =3D 2 and so + * prescale =E2=89=A4 5 for info->prescale_mult =3D 2, + * prescale =E2=89=A4 10 for info->prescale_mult =3D 1, and so * tmp =3D val << (info->prescale_mult * prescale) * NSEC_PER_MSEC * < 2^32 * 2^10 * 10^6 * < 2^32 * 2^10 * 2^20 @@ -460,6 +484,14 @@ static int rzg2l_gpt_probe(struct platform_device *pde= v) if (IS_ERR(rstc)) return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert reset control\= n"); =20 + rstc =3D devm_reset_control_get_optional_exclusive_deasserted(dev, "rst_s= "); + if (IS_ERR(rstc)) + return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert rst_s reset\n"= ); + + clk =3D devm_clk_get_optional_enabled(dev, "bus"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "Cannot get bus clock\n"); + clk =3D devm_clk_get_enabled(dev, NULL); if (IS_ERR(clk)) return dev_err_probe(dev, PTR_ERR(clk), "Cannot get clock\n"); @@ -498,6 +530,12 @@ static int rzg2l_gpt_probe(struct platform_device *pde= v) return 0; } =20 +static const struct rzg2l_gpt_info rzg3e_data =3D { + .calculate_prescale =3D rzg3e_gpt_calculate_prescale, + .gtcr_tpcs =3D RZG3E_GTCR_TPCS, + .prescale_mult =3D 1, +}; + static const struct rzg2l_gpt_info rzg2l_data =3D { .calculate_prescale =3D rzg2l_gpt_calculate_prescale, .gtcr_tpcs =3D RZG2L_GTCR_TPCS, @@ -505,6 +543,7 @@ static const struct rzg2l_gpt_info rzg2l_data =3D { }; =20 static const struct of_device_id rzg2l_gpt_of_table[] =3D { + { .compatible =3D "renesas,r9a09g047-gpt", .data =3D &rzg3e_data }, { .compatible =3D "renesas,rzg2l-gpt", .data =3D &rzg2l_data }, { /* Sentinel */ } }; --=20 2.43.0 From nobody Mon Sep 28 08:47:22 2026 Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C24EC41E6D6 for ; Mon, 24 Aug 2026 12:56:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576164; cv=none; b=SepbqjFtUtrVlyIF0EBfSfNixePhonxqCOhF/98B4nDCArGI3bHxRK3hph66A61wTDWlR6HK5e2mp57MwLVWDbVka6Yu8hrNf2Z6N2l8ZhHTKt/sZxI0NKF7ZehEnLjsmFoJBExmBoBMVa+Nd7SNSGT49jxJHRM1h8zmmVrOU+o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576164; c=relaxed/simple; bh=2S9ge3Gkux6zzeM+n6dPsFXQ7STMFa+l1y8WPqoTfCk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tKFEa0COrArTD2PTCOuIe+6NZpUaTA1Cofr/06Kk1GhgRWGBjxQazPVac4T1ZQQ5QPPUlHS249C5TwwSZPot4blEL4sk/TGV2Fd1s2BSL+To7ISQvSaD7mlxyEuwFnQho2/40YpliueA7KSjuUS+Qh/v7OCs1V7ezra/vi9ZchQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ZTBDucYY; arc=none smtp.client-ip=209.85.218.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ZTBDucYY" Received: by mail-ej1-f43.google.com with SMTP id a640c23a62f3a-c16794450aeso494049166b.2 for ; Mon, 24 Aug 2026 05:56:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787576160; x=1788180960; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=lEYpVaTK2qGZEqiKTNTTUd76osnkufYUG4ARHqvujuo=; b=ZTBDucYYPfcxo8Pw00+LOBPvusYW5BjXQXm8VVnM0MTIByWFp29ebAfW/cBnpALbza Cp1XkLDSUvmfQVez21fDXVRnEUzzPBH3W9nU0lbbldAUEgeGqJy4eALBVWP8hrqh3uY4 kreA/zDNHFX8IlCezOo4ag0iluy4qZQT6hnfri3Gb51GRKluVIctfTnZg5EL8VgC9PNq 9F4QZi04d/Ue9mDa9wD//PT2+hnR6C5Ez9lyuOkKtN5t+b78tRwB4VbnT+/XFxSN3tA8 ssas1vswN9vp3I8gNlIsjZ8KfWD08mU/olNKlucf5MVtlik9Uwe+WuV3JIUMroTN2Kqk Aq3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787576160; x=1788180960; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=lEYpVaTK2qGZEqiKTNTTUd76osnkufYUG4ARHqvujuo=; b=h2BBb6urdQbBcTw26rIefwSLtnrcN4s4v+AadjjeqsHy3PvlIZMrPtDVECLQEEhZOs apLX5yktoFUJDp24ufG3AdlXEweii5Hu3F2/4saLPO3VKBVV+liJ5m3WKkufZEIDOd8R 9V6mRoPAmOx/s+Yz50HFfmv8g3xiD7Mj1ZtOa1rkCc5y2i/xmv4/gQqq92Lo4ERPVeNB mr7ycyy1M6PQfRQLTmxCNUi6sI2LQZFxZLS4b93giQUYex3MD7Rt5Hu6rEQ11io7xkOe hHmKHdU7AxfTPy/9o0R3nTRnybRplz9iB7h8WQh8Ig8osxjlRClwmLCOKCSRQNw7wmVf lTXg== X-Forwarded-Encrypted: i=1; AHgh+RoFzo7iwrNcF3tUhrfl3F3Pd47JEMKbevuUiD6qBiOnuExBmdtzhdX7HWpHUrcqJ+9vok2kV0VH9HWj3Fw=@vger.kernel.org X-Gm-Message-State: AFuF++lu6l2wq8IcVb9GR9KzaYm7o5CmrQvTnCyfYurAwCMzKoRUQOCq 1XkeqPv2xHwbBpbMWYo4VdCWBrnpLSsPUdfBul67dj9JuS5aSwg5hrwF X-Gm-Gg: AR+sD13Y2rBhU5x/oj0zkUPtV6G4r7yY8xp6e/kDlpJPCpMNqngfufRDGhSCdVhyuUC aQKSvKpSnMtA7Yu9zskB4tlZ2yYrEqISEBn0DmVAnjPWmBkXJbBI8ybQUUuNJ5AxSYiaQaXYDx0 xRbaLXtrZPoloQDBLJxiFKbhVSPMMEZtnpvFBzEKlxvowoQ9O4fBGHJqOKoBjm7Jm8N6mU7aTqM EQzOTjFO/oWfrnp91GxnlUAfHNhWs+M9/wUfXphCbOeWGX1OVisRQe8w2CoaN+ToSYf/PGSSJhu W/fSLDGXOtjcPxIqEjimMcGxNPH9/LKcu+Vbqwpgj0dZ8d3qz4u56kRNZlq8MQXRoc2OomE4hd6 4fwptY2qCrsNXYgDnC1Ui+AoDFS0rnyq5wknlFClXGSSQuvzZtATrhJMGh26QQ8i2Zh5LYVqigR G7uLVrVd0pfhiN5FDMtgSJaLjH0hXOMDhipwDVxhBTWdVcGBwOvGnbH4fBf/Qt9qJM5QIUapRhi pF8VMzIErz8yw== X-Received: by 2002:a17:907:9346:b0:c1a:5d49:f99d with SMTP id a640c23a62f3a-c246a3ab4c2mr3218865366b.7.1787576159544; Mon, 24 Aug 2026 05:55:59 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:dea4:599b:49a8:96f5]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c24966f9c9fsm1245403066b.39.2026.08.24.05.55.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 05:55:59 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v7 8/9] dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property Date: Mon, 24 Aug 2026 13:55:14 +0100 Message-ID: <20260824125523.131762-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260824125523.131762-1-biju.das.jz@bp.renesas.com> References: <20260824125523.131762-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das RZ/G2L GPT IP supports output pin disable function by dead time error and detecting short-circuits between output pins. Add documentation for the optional property renesas,poegs to link a pair of GPT IOs with POEG. Reviewed-by: Rob Herring Signed-off-by: Biju Das --- v6->v7: * No change v5->v6: * No change v5: * No change v24 from [1]: [1] https://lore.kernel.org/all/20250226144531.176819-1-biju.das.jz@bp.rene= sas.com/ --- .../bindings/pwm/renesas,rzg2l-gpt.yaml | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml b= /Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml index 13b807765a30..98bcde755fb9 100644 --- a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml @@ -245,6 +245,28 @@ properties: resets: maxItems: 1 =20 + renesas,poegs: + minItems: 1 + maxItems: 8 + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle to POEG instance that serves the output dis= able + - enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ] + description: | + An index identifying pair of GPT channels. + <0> : GPT channels 0 and 1 + <1> : GPT channels 2 and 3 + <2> : GPT channels 4 and 5 + <3> : GPT channels 6 and 7 + <4> : GPT channels 8 and 9 + <5> : GPT channels 10 and 11 + <6> : GPT channels 12 and 13 + <7> : GPT channels 14 and 15 + description: + A list of phandle and channel index pair tuples to the POEGs that ha= ndle the + output disable for the GPT channels. + required: - compatible - reg @@ -375,4 +397,5 @@ examples: power-domains =3D <&cpg>; resets =3D <&cpg R9A07G044_GPT_RST_C>; #pwm-cells =3D <3>; + renesas,poegs =3D <&poeggd 4>; }; --=20 2.43.0 From nobody Mon Sep 28 08:47:22 2026 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5195423780 for ; Mon, 24 Aug 2026 12:56:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576165; cv=none; b=gwb/dioL7TXCpIJGXrdOavStI0Q4JiVQoZhR7DQjn3zfmXOQTfmD38KGQKsQh1cqwsQb54BQvbkzss0rHn/4OLLI8yqbUD55gzPrK6MfwCmjCbu7lHtb8nHn+gTTT9jZp7myEAPO7ahzEiF2qD8qo+OlEMkMjAt6uQIN9vaoAOo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787576165; c=relaxed/simple; bh=YG+IiEVQQovs2Oyy6pGJHFjkdJTDdsD9yEfGJakM0mg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=twbeeL+1xbtQo7BlXibGdbWC2x7qeHEwl/bmixSAhSFruuRZMPtz+a0e3vpXAX3OFpGWfPLaQ9J+e/TbJZb/XAx4ide46DA5SEYlg7/QmIla53NnlAHafwXt7SlQEMjyJDkiMC84Mocn5tekwqHiOecErPBhdTfCR2+DrFgMwbs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=jPZ2gA1p; arc=none smtp.client-ip=209.85.218.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jPZ2gA1p" Received: by mail-ej1-f45.google.com with SMTP id a640c23a62f3a-c20fb91ed0fso522555866b.3 for ; Mon, 24 Aug 2026 05:56:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787576161; x=1788180961; darn=vger.kernel.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:from:to:cc:subject :date:message-id:reply-to:content-type; bh=9T6PUvsAbU79P22b+F31n1QypVkr8AsU12//9zas9pI=; b=jPZ2gA1ptmVlTpeNlETlAKNvF/PnANob5eiwHNXzRm7jicEM7+Am1x/x3/0fQAr9x9 JBMU1GEbg9yXQ2c+QB6YOStCKiz/xdeiKvtMFiE3Q9zcXLIhrOdDyKdxqU+t1iBQIvjs izcxF+noreF37AOFsTNMeJYh2+a4cm7NnfrNiGCzOR6BgiEAjYxHJ/C5F1+4xtwRJ6Ik JzQ8ZdO6QmeVLe44fMTqOsdYHP9iP0UGGTMtf/E3Nr4ztj5tMC0qLdGVSTMts4c6uoHi WGyofM/3jgXeIHorhW5IMkmQZtYmg8Utxr2J0vDI4OSN3wGekr0jrtnAaG+axrhLrhm2 0FBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787576161; x=1788180961; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=9T6PUvsAbU79P22b+F31n1QypVkr8AsU12//9zas9pI=; b=laNvI2WtHD1vWL9r8uLS8DnkpHdvZz2B5RrdaM+bbV+knX8e1/GPcxBozXikDx7eH2 HrOJEM84qjc/Bksr144/gUNjqov8uH7gzOZJH+nUVIgfqxqS+cNqFjFnaEn6osPgAQlu XdEA6iFO1uEUnNyYZlBNrY9uW2iIpL0zbLQcaxvWmRISW44qpr71y/wHd3AkmKL/4Prf RvaucpjRxJ+AFEK+Cb0weT+ZppiQUI9o2SR5Ro0NXs24X+75j3VXILP0NSDI67XD0UEw LwbzBCWuP3W32wS9Dc19mEYDS8Lc+XCPnU/NKq9uxaOdtsnX9mLXjCgW753hjY4FLrSk GpKQ== X-Forwarded-Encrypted: i=1; AHgh+RordCtwwZOzVe1aSdSzQcMpva3jRgRhFyN7A29VXycVd9aj0duYdOuo+ihJMxgQFO78olgrtcLW9XAhU18=@vger.kernel.org X-Gm-Message-State: AFuF++kM2NtHp4UhObtDlvrLwqXAXFFNHipaRqF3IvrHis7qfz1/ADJb UkJ5iCtTXBu8WxpjaOZkhkAHHjNUuew6um7QCJSlYBlULjk5ZaTFpqeQ X-Gm-Gg: AR+sD11jpbE/AUTuVATAS7aydVzCWG0QP0GBzE/2HHw6hzYzhx3S2KHlVNvDEQtmc6a rj9EO82PdkmHHGNhYpoEK0xWnHo6m+UI6q2K8cNGufw37gmtFZfhlSIIwako7fKzvaKMhBSkWbM 0eYb+Jojoz6tAsiWoYCVszMlmvsedzzUpxWAj6OWPFq/473gZpip1nYY4lJK6vjdy4NVH04AJCz eT4xwuEM+XMqkC7Idf7k0KmPchl7EMyuAdSCeeC8kDMHLp9VXyeL3ilsSClFsePfAunhxfH3763 pYYPmK1NDqG/5Br5C8cq6Nvx4XXC/9U+kMnnmh2Ng8j0ZnzlTc+zVYqVo4ugxAuYAJexvTQ6h0M MI7YfltnakC52oilERKTkE2VZj/B+fS1pIfcvLoiBPAHpW2EThPc0UzrLm6ei2zLqg5q8sZNnH6 hQBapdz/pElxJSalwpBgge5U6/3Lg2kbDvmQXoJ6SSjfwOremJIjTvQwzqT57BocADwurJAooW5 1xbK8a8JHnx1g== X-Received: by 2002:a17:907:934c:b0:c15:f65a:43a8 with SMTP id a640c23a62f3a-c246a604950mr3000521566b.12.1787576160732; Mon, 24 Aug 2026 05:56:00 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:dea4:599b:49a8:96f5]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c24966f9c9fsm1245403066b.39.2026.08.24.05.55.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 05:56:00 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v7 9/9] pwm: rzg2l-gpt: Add support for gpt linking with poeg Date: Mon, 24 Aug 2026 13:55:15 +0100 Message-ID: <20260824125523.131762-10-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260824125523.131762-1-biju.das.jz@bp.renesas.com> References: <20260824125523.131762-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Biju Das The General PWM Timer (GPT) is capable of detecting "dead time error and short-circuits between output pins" and send Output disable request to poeg(Port Output Enable for GPT). Add support for linking poeg group with gpt, so that gpt can control the output disable function by adding rzg2l_gpt_poeg_init() to parse the renesas,poegs device tree property and establish links between POEG groups (A=E2=80=93D) and GPT hardware channels (0=E2=80=937). For each vali= d, enabled POEG phandle entry, the driver: - Reads the renesas,poeg-id from the POEG node and validates it against the supported range - Records the GPT=E2=80=93POEG association in a per-chip bitmap (poeg_gpt_= link) - Configures GTINTAD to route the output disable request to the correct POEG group - Configures GTIOR (OADF/OBDF fields) to set both output pins to high-impedance on an output disable event Non-enabled POEG nodes are silently skipped. Signed-off-by: Biju Das --- v6->v7: * Added rzg2l_gpt_poeg_link_channels() and used __free for deallocating device node pointer. * Replaced dev_err()->dev_err_probe() in rzg2l_gpt_poeg_link_channels(). * Replaced local variable cells with num_poeg_pairs in rzg2l_gpt_poeg_init(). v5->v6: * Dropped extra space in poegs variable assignment in rzg2l_gpt_poeg_init(). * Updated the comment sections of rzg2l_gpt_poeg_init() with POEG and GPT in upper-case and replaced configure->configures. * Format specifiers in dev_err() changed from %d to %u in rzg2l_gpt_poeg_init(). v5: * Updated commit description. * Replaced return type of rzg2l_gpt_poeg_init() from void->int and probe() checks this return value. * Added more error checks in rzg2l_gpt_poeg_init()=20 V24 from [1]: [1] https://lore.kernel.org/all/20250226144531.176819-1-biju.das.jz@bp.rene= sas.com/ --- drivers/pwm/pwm-rzg2l-gpt.c | 92 +++++++++++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index c61c648f71a8..4e1591d81b51 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -45,6 +45,7 @@ #define RZG2L_GTCR(ch) (0x2c + RZG2L_GET_CH_OFFS(ch)) #define RZG2L_GTUDDTYC(ch) (0x30 + RZG2L_GET_CH_OFFS(ch)) #define RZG2L_GTIOR(ch) (0x34 + RZG2L_GET_CH_OFFS(ch)) +#define RZG2L_GTINTAD(ch) (0x38 + RZG2L_GET_CH_OFFS(ch)) #define RZG2L_GTBER(ch) (0x40 + RZG2L_GET_CH_OFFS(ch)) #define RZG2L_GTCNT(ch) (0x48 + RZG2L_GET_CH_OFFS(ch)) #define RZG2L_GTCCR(ch, sub_ch) (0x4c + RZG2L_GET_CH_OFFS(ch) + 4 * (sub_c= h)) @@ -62,12 +63,19 @@ #define RZG2L_GTUDDTYC_UP_COUNTING (RZG2L_GTUDDTYC_UP | RZG2L_GTUDDTYC_UDF) =20 #define RZG2L_GTIOR_GTIOA GENMASK(4, 0) +#define RZG2L_GTIOR_OADF GENMASK(10, 9) #define RZG2L_GTIOR_GTIOB GENMASK(20, 16) +#define RZG2L_GTIOR_OBDF GENMASK(26, 25) #define RZG2L_GTIOR_GTIOx(sub_ch) ((sub_ch) ? RZG2L_GTIOR_GTIOB : RZG2L_GT= IOR_GTIOA) #define RZG2L_GTIOR_OAE BIT(8) #define RZG2L_GTIOR_OBE BIT(24) #define RZG2L_GTIOR_OxE(sub_ch) ((sub_ch) ? RZG2L_GTIOR_OBE : RZG2L_GTIOR= _OAE) =20 +#define RZG2L_GTIOR_OADF_HIGH_IMP_ON_OUT_DISABLE BIT(9) +#define RZG2L_GTIOR_OBDF_HIGH_IMP_ON_OUT_DISABLE BIT(25) +#define RZG2L_GTIOR_PIN_DISABLE_SETTING \ + (RZG2L_GTIOR_OADF_HIGH_IMP_ON_OUT_DISABLE | RZG2L_GTIOR_OBDF_HIGH_IMP_ON_= OUT_DISABLE) + #define RZG2L_INIT_OUT_HI_OUT_HI_END_TOGGLE 0x1b #define RZG2L_GTIOR_GTIOA_OUT_HI_END_TOGGLE_CMP_MATCH \ (RZG2L_INIT_OUT_HI_OUT_HI_END_TOGGLE | RZG2L_GTIOR_OAE) @@ -78,12 +86,17 @@ ((sub_ch) ? RZG2L_GTIOR_GTIOB_OUT_HI_END_TOGGLE_CMP_MATCH : \ RZG2L_GTIOR_GTIOA_OUT_HI_END_TOGGLE_CMP_MATCH) =20 +#define RZG2L_GTINTAD_GRP_MASK GENMASK(25, 24) + #define RZG2L_MAX_HW_CHANNELS 8 #define RZG2L_CHANNELS_PER_IO 2 #define RZG2L_MAX_PWM_CHANNELS (RZG2L_MAX_HW_CHANNELS * RZG2L_CHANNELS_PER= _IO) #define RZG2L_MAX_SCALE_FACTOR 1024 #define RZG2L_MAX_TICKS ((u64)U32_MAX * RZG2L_MAX_SCALE_FACTOR) =20 +#define RZG2L_MAX_POEG_GROUPS 4 +#define RZG2L_LAST_POEG_GROUP 3 + struct rzg2l_gpt_info { u8 (*calculate_prescale)(u64 period); u32 gtcr_tpcs; @@ -98,6 +111,7 @@ struct rzg2l_gpt_chip { u64 period_ticks[RZG2L_MAX_HW_CHANNELS]; u32 channel_request_count[RZG2L_MAX_HW_CHANNELS]; u32 channel_enable_count[RZG2L_MAX_HW_CHANNELS]; + DECLARE_BITMAP(poeg_gpt_link, RZG2L_MAX_POEG_GROUPS * RZG2L_MAX_HW_CHANNE= LS); }; =20 /* This represents a hardware configuration for one channel */ @@ -459,6 +473,80 @@ static const struct pwm_ops rzg2l_gpt_ops =3D { .write_waveform =3D rzg2l_gpt_write_waveform, }; =20 +static int rzg2l_gpt_poeg_link_channels(struct device *dev, + struct rzg2l_gpt_chip *rzg2l_gpt, + struct of_phandle_args *of_args) +{ + struct device_node *np __free(device_node) =3D of_args->np; + u32 poeg_grp, bitpos; + + if (of_args->args[0] >=3D RZG2L_MAX_HW_CHANNELS) + return dev_err_probe(dev, -EINVAL, "Invalid channel %u >=3D %u\n", + of_args->args[0], RZG2L_MAX_HW_CHANNELS); + + if (!of_device_is_available(of_args->np)) + /* It's fine to have a phandle to a non-enabled poeg. */ + return 0; + + if (!of_property_read_u32(of_args->np, "renesas,poeg-id", &poeg_grp)) { + if (poeg_grp > RZG2L_LAST_POEG_GROUP) + return dev_err_probe(dev, -EINVAL, "Invalid poeg group %u > %u\n", + poeg_grp, RZG2L_LAST_POEG_GROUP); + + bitpos =3D of_args->args[0] + poeg_grp * RZG2L_MAX_HW_CHANNELS; + set_bit(bitpos, rzg2l_gpt->poeg_gpt_link); + + rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTINTAD(of_args->args[0]), + RZG2L_GTINTAD_GRP_MASK, poeg_grp << 24); + + rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTIOR(of_args->args[0]), + RZG2L_GTIOR_OBDF | RZG2L_GTIOR_OADF, + RZG2L_GTIOR_PIN_DISABLE_SETTING); + } + + return 0; +} + +/* + * This function links a POEG group{A,B,C,D} with a GPT channel{0..7} and + * configures the pin for output disable. + */ +static int rzg2l_gpt_poeg_init(struct platform_device *pdev, + struct rzg2l_gpt_chip *rzg2l_gpt) +{ + const char *poeg_name =3D "renesas,poegs"; + struct of_phandle_args of_args; + struct property *poegs; + int num_poeg_pairs; + int ret; + + poegs =3D of_find_property(pdev->dev.of_node, poeg_name, NULL); + if (!poegs) + return 0; + + num_poeg_pairs =3D of_property_count_u32_elems(pdev->dev.of_node, poeg_na= me); + if (num_poeg_pairs < 0) + return num_poeg_pairs; + + if (num_poeg_pairs & 1) + return -EINVAL; + + num_poeg_pairs >>=3D 1; + for (unsigned int i =3D 0; i < num_poeg_pairs; i++) { + ret =3D of_parse_phandle_with_fixed_args(pdev->dev.of_node, + poeg_name, 1, i, + &of_args); + if (ret) + return ret; + + ret =3D rzg2l_gpt_poeg_link_channels(&pdev->dev, rzg2l_gpt, &of_args); + if (ret) + return ret; + } + + return 0; +} + static int rzg2l_gpt_probe(struct platform_device *pdev) { struct rzg2l_gpt_chip *rzg2l_gpt; @@ -520,6 +608,10 @@ static int rzg2l_gpt_probe(struct platform_device *pde= v) if (rzg2l_gpt->rate_khz * KILO !=3D rate) return dev_err_probe(dev, -EINVAL, "Rate is not multiple of 1000\n"); =20 + ret =3D rzg2l_gpt_poeg_init(pdev, rzg2l_gpt); + if (ret) + return dev_err_probe(dev, ret, "Failed to link gpt with poeg\n"); + mutex_init(&rzg2l_gpt->lock); =20 chip->ops =3D &rzg2l_gpt_ops; --=20 2.43.0