From nobody Mon Sep 28 08:57:48 2026 Received: from out28-169.mail.aliyun.com (out28-169.mail.aliyun.com [115.124.28.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 304FD4189DD; Mon, 24 Aug 2026 12:40:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787575233; cv=none; b=rqX0TNTrNtfkBpViuNU7BLc8HdJpHlSRl5PKnK37JfKZvm/UVlAZ5+gz+SJHCqtho4SAAToQpch2MDrjpsO2ahqYg86k9M2mnp0FgKkOWp4/ip2VszcHGuAuXw/ybQC+HvWVqNTJ1Nw7UxT8yLeykXXxLuaufzUo2WYvi/iaWfE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787575233; c=relaxed/simple; bh=VvMNeTl43EAnzwqFM3KAQGlPL31aXcFp7ZMK+ulU33k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=A+mdTQiu+gVx4Ox99Vnh2knw+MloDqOZif+ZwhQtsLwhQqbSPHEa2aBS20PpBJWINP/pTiXlB92qIuOgr8X12NVqehCs6F/PyyORB5hrk1qghJWyEPsl8qOFU2mwyvLwC0p2+eqqyeKI16p2i5ngdgu6ET5tP3xNGufk4wl3bm8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=115.124.28.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam: AC=CONTINUE;BC=0.07653359|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_system_inform|0.0567326-0.000132363-0.943135;FP=16598417234024275939|0|0|0|0|-1|-1|-1;HT=maildocker-contentspam033032062159;MF=zhang_wei@open-hieco.net;NM=1;PH=DS;RN=9;RT=9;SR=0;TI=SMTPD_---.iw1ggoq_1787575224; Received: from localhost.localdomain(mailfrom:zhang_wei@open-hieco.net fp:SMTPD_---.iw1ggoq_1787575224 cluster:ay29) by smtp.aliyun-inc.com; Mon, 24 Aug 2026 20:40:25 +0800 From: Tina Zhang To: Sean Christopherson , Jim Mattson , kvm@vger.kernel.org Cc: Paolo Bonzini , Shuah Khan , zhouyanjing@hygon.cn, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Tina Zhang Subject: [PATCH v5 1/8] KVM: x86: Add helper to provide intercept linear addresses Date: Mon, 24 Aug 2026 20:39:47 +0800 Message-ID: <20260824123954.315112-2-zhang_wei@open-hieco.net> X-Mailer: git-send-email 2.43.7 In-Reply-To: <20260824123954.315112-1-zhang_wei@open-hieco.net> References: <20260824123954.315112-1-zhang_wei@open-hieco.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add get_intercept_linear_addr() to compute the linear address for intercepts that report one, and pass the result through x86_instruction_info. Handle INVLPG as the initial user. INVLPG's memory operand is decoded with NoAccess, and thus src_val does not contain the operand address. Compute the address from the decoded segment base and effective address in the emulator, where the operand state is available. This allows intercept handlers to use the linear address directly without duplicating the emulator's address calculation. Signed-off-by: Tina Zhang --- arch/x86/kvm/emulate.c | 29 +++++++++++++++++++++-------- arch/x86/kvm/kvm_emulate.h | 1 + 2 files changed, 22 insertions(+), 8 deletions(-) diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index 8071b372d233..a0e57b64cadd 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -410,6 +410,26 @@ static int em_salc(struct x86_emulate_ctxt *ctxt) _fault ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; \ }) =20 +static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) +{ + if (ctxt->mode =3D=3D X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) + return 0; + + return ctxt->ops->get_cached_segment_base(ctxt, seg); +} + +static u64 get_intercept_linear_addr(struct x86_emulate_ctxt *ctxt, + enum x86_intercept intercept) +{ + u64 la; + + if (intercept !=3D x86_intercept_invlpg) + return 0; + + la =3D seg_base(ctxt, ctxt->src.addr.mem.seg) + ctxt->src.addr.mem.ea; + return ctxt->mode =3D=3D X86EMUL_MODE_PROT64 ? la : (u32)la; +} + static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt, enum x86_intercept intercept, enum x86_intercept_stage stage) @@ -427,6 +447,7 @@ static int emulator_check_intercept(struct x86_emulate_= ctxt *ctxt, .src_type =3D ctxt->src.type, .dst_type =3D ctxt->dst.type, .ad_bytes =3D ctxt->ad_bytes, + .intercept_linear_addr =3D get_intercept_linear_addr(ctxt, intercept), .rip =3D ctxt->eip, .next_rip =3D ctxt->_eip, }; @@ -520,14 +541,6 @@ static u32 desc_limit_scaled(struct desc_struct *desc) return desc->g ? (limit << 12) | 0xfff : limit; } =20 -static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) -{ - if (ctxt->mode =3D=3D X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) - return 0; - - return ctxt->ops->get_cached_segment_base(ctxt, seg); -} - static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, u32 error, bool valid) { diff --git a/arch/x86/kvm/kvm_emulate.h b/arch/x86/kvm/kvm_emulate.h index 3e375af15c03..9eda648a1314 100644 --- a/arch/x86/kvm/kvm_emulate.h +++ b/arch/x86/kvm/kvm_emulate.h @@ -51,6 +51,7 @@ struct x86_instruction_info { u8 src_type; /* type of source operand */ u8 dst_type; /* type of destination operand */ u8 ad_bytes; /* size of src/dst address */ + u64 intercept_linear_addr; /* arch-reported linear address, if any */ u64 rip; /* rip of the instruction */ u64 next_rip; /* rip following the instruction */ }; base-commit: 1b731e5ded480bd1e5546aed35584238661ce72e --=20 2.43.7 From nobody Mon Sep 28 08:57:48 2026 Received: from out28-217.mail.aliyun.com (out28-217.mail.aliyun.com [115.124.28.217]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F48141B37D; Mon, 24 Aug 2026 12:40:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.217 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787575243; cv=none; b=Fgd8byv9EcVw6Qe+1neyiPo++nb+2nk1ZEPU+YNqe8dxrwZZvf6sjaGri61O1mLeiIMYbeYOU7CeNoGEDZhi0snL8cxqSkxK+q0PkBunhClBtrmWUII2hOGXqA3168UDp7JcdBURl3ccrN0qFAkOOzrVhc64Jn6C6xpDsWKSIec= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787575243; c=relaxed/simple; bh=oQKj2gG7VT+v/fK2Y1FTo/AHvqiW7BLnSvF+geSP600=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LVELuUEUaERMD5QLcMc3KkCCYrulvnK30jMUQYQvY44lpy+gYupZvgCxxp59h1IVyqhdZqAVM/RJ17x7Y56axuVHl1UOR6Ej2/BSZL81/khTkBtpnwqUb8ytclf+bNpZh7qbcQVmRwF+nnBiUMpX5pMqBti0yoc5XubTczYxNw8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=115.124.28.217 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam: AC=CONTINUE;BC=0.09897623|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_system_inform|0.0982147-9.01477e-05-0.901695;FP=4965848656623764659|1|1|1|0|-1|-1|-1;HT=maildocker-contentspam033032053168;MF=zhang_wei@open-hieco.net;NM=1;PH=DS;RN=9;RT=9;SR=0;TI=SMTPD_---.iw1ggtS_1787575225; Received: from localhost.localdomain(mailfrom:zhang_wei@open-hieco.net fp:SMTPD_---.iw1ggtS_1787575225 cluster:ay29) by smtp.aliyun-inc.com; Mon, 24 Aug 2026 20:40:27 +0800 From: Tina Zhang To: Sean Christopherson , Jim Mattson , kvm@vger.kernel.org Cc: Paolo Bonzini , Shuah Khan , zhouyanjing@hygon.cn, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Tina Zhang Subject: [PATCH v5 2/8] KVM: nSVM: Synthesize DecodeAssists EXITINFO for emulated intercepts Date: Mon, 24 Aug 2026 20:39:48 +0800 Message-ID: <20260824123954.315112-3-zhang_wei@open-hieco.net> X-Mailer: git-send-email 2.43.7 In-Reply-To: <20260824123954.315112-1-zhang_wei@open-hieco.net> References: <20260824123954.315112-1-zhang_wei@open-hieco.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When the x86 emulator encounters an instruction intercepted by L1, svm_check_intercept() synthesizes a nested VM-Exit without fresh hardware DecodeAssist state. Populate the architectural EXITINFO fields when DecodeAssists is exposed to L1. Generate EXITINFO1 with the GPR number for MOV CR/DR, the interrupt vector for INTn, and the linear address for INVLPG. Set EXITINFO1 to zero for CLTS, LMSW, SMSW, and INVLPGA; the INVLPGA address remains in guest rAX. Clear EXITINFO2 for all covered intercepts and leave unrelated intercepts unchanged. Signed-off-by: Tina Zhang --- arch/x86/kvm/svm/svm.c | 48 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 9d607b98bd06..c7c1f1527c3c 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4810,6 +4810,52 @@ static const struct __x86_intercept { #undef POST_EX #undef POST_MEM =20 +static void svm_prepare_decode_assist_exit_info(struct kvm_vcpu *vcpu, + const struct x86_instruction_info *info) +{ + struct vmcb *vmcb =3D to_svm(vcpu)->vmcb; + u64 exit_info_1; + + if (!guest_cpu_cap_has(vcpu, X86_FEATURE_DECODEASSISTS)) + return; + + switch (info->intercept) { + case x86_intercept_cr_read: + case x86_intercept_cr_write: + /* MOV CRx: bit 63 set, GPR number in bits 3:0. */ + exit_info_1 =3D BIT_ULL(63) | (info->modrm_rm & 0xf); + break; + case x86_intercept_clts: + case x86_intercept_lmsw: + case x86_intercept_smsw: + /* CLTS/LMSW/SMSW: no decode information, bit 63 clear. */ + exit_info_1 =3D 0; + break; + case x86_intercept_dr_read: + case x86_intercept_dr_write: + /* MOV DRx: GPR number in bits 3:0. */ + exit_info_1 =3D info->modrm_rm & 0xf; + break; + case x86_intercept_intn: + /* INTn: software interrupt number in bits 7:0. */ + exit_info_1 =3D info->src_val & 0xff; + break; + case x86_intercept_invlpg: + /* INVLPG: linear address of the target page. */ + exit_info_1 =3D info->intercept_linear_addr; + break; + case x86_intercept_invlpga: + /* INVLPGA: the address remains available in guest rAX. */ + exit_info_1 =3D 0; + break; + default: + return; + } + + vmcb->control.exit_info_1 =3D exit_info_1; + vmcb->control.exit_info_2 =3D 0; +} + static int svm_check_intercept(struct kvm_vcpu *vcpu, struct x86_instruction_info *info, enum x86_intercept_stage stage, @@ -4931,6 +4977,8 @@ static int svm_check_intercept(struct kvm_vcpu *vcpu, break; } =20 + svm_prepare_decode_assist_exit_info(vcpu, info); + /* TODO: Advertise NRIPS to guest hypervisor unconditionally */ if (static_cpu_has(X86_FEATURE_NRIPS)) vmcb->control.next_rip =3D info->next_rip; --=20 2.43.7 From nobody Mon Sep 28 08:57:48 2026 Received: from out198-22.us.a.mail.aliyun.com (out198-22.us.a.mail.aliyun.com [47.90.198.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B57F941D638; Mon, 24 Aug 2026 12:40:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=47.90.198.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787575261; cv=none; b=aX4jMNj6QxxubdJOT2xKeLx4S0666N9i1cuYz6dU5jorowV9yKiR1gLITwP/xXns8kzeQQ+We0OkjTYjcpFSiuVSfMTPqCywFI+23N/9RBTA2di9qzoODdiuc6DbNPSGkvgNesjzreNm1uqGLR6nqOxPk1RD3CtbzN6OwWbjVWk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787575261; c=relaxed/simple; bh=Kw08plDE7St066BGYrJ3qnKS73qdi7HExWNjOvM/iSc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=khPVCu3Z+lKPzUAYA1xax6OQx7+sd8r3XwlariEjYK29CYzDMjhQ6FEeGDC83fnwMZQermF45HbtqtbM6dquiOW46zS+B4juiOH/JlSk+jDhcPz1CypX4iWih851Ue7jA0H6+wfLMpknJ/CIQVfGjvkbbrvwLiOdtVirLiVVDHE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=47.90.198.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam: AC=CONTINUE;BC=0.07436264|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_system_inform|0.0120011-0.00288252-0.985116;FP=17179378910432399098|1|1|1|0|-1|-1|-1;HT=maildocker-contentspam033022149254;MF=zhang_wei@open-hieco.net;NM=1;PH=DS;RN=9;RT=9;SR=0;TI=SMTPD_---.iw1ggzc_1787575228; Received: from localhost.localdomain(mailfrom:zhang_wei@open-hieco.net fp:SMTPD_---.iw1ggzc_1787575228 cluster:ay29) by smtp.aliyun-inc.com; Mon, 24 Aug 2026 20:40:29 +0800 From: Tina Zhang To: Sean Christopherson , Jim Mattson , kvm@vger.kernel.org Cc: Paolo Bonzini , Shuah Khan , zhouyanjing@hygon.cn, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Tina Zhang Subject: [PATCH v5 3/8] KVM: nSVM: Track fresh hardware DecodeAssist bytes Date: Mon, 24 Aug 2026 20:39:49 +0800 Message-ID: <20260824123954.315112-4-zhang_wei@open-hieco.net> X-Mailer: git-send-email 2.43.7 In-Reply-To: <20260824123954.315112-1-zhang_wei@open-hieco.net> References: <20260824123954.315112-1-zhang_wei@open-hieco.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" VMCB02 instruction bytes are valid only for the hardware VM-Exit that populated them. Track whether VMCB02 contains instruction bytes for the data #PF or #NPF currently being reflected to L1 so that stale bytes are not copied to VMCB12. Clear the VMCB02 instruction-byte fields and freshness state before each nested run. Mark the bytes as fresh only when a data #PF or #NPF came from hardware; KVM-synthesized exits and instruction-fetch faults leave the state clear. A subsequent change will use this state when propagating hardware DecodeAssist instruction bytes to VMCB12. Signed-off-by: Tina Zhang --- arch/x86/kvm/svm/nested.c | 41 +++++++++++++++++++++++++++++++++++++-- arch/x86/kvm/svm/svm.c | 6 +++--- arch/x86/kvm/svm/svm.h | 5 ++++- 3 files changed, 46 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86/kvm/svm/nested.c index 73f37b050d0a..6770721d4e4c 100644 --- a/arch/x86/kvm/svm/nested.c +++ b/arch/x86/kvm/svm/nested.c @@ -35,6 +35,38 @@ =20 #define CC KVM_NESTED_VMENTER_CONSISTENCY_CHECK =20 +static void nested_svm_clear_insn_bytes(struct vmcb *vmcb) +{ + vmcb->control.insn_len =3D 0; + memset(vmcb->control.insn_bytes, 0, + sizeof(vmcb->control.insn_bytes)); +} + +static bool nested_svm_vmexit_has_insn_bytes(const struct vmcb *vmcb) +{ + u64 exit_code =3D vmcb->control.exit_code; + + if (exit_code !=3D SVM_EXIT_NPF && + exit_code !=3D SVM_EXIT_EXCP_BASE + PF_VECTOR) + return false; + + return !(vmcb->control.exit_info_1 & PFERR_FETCH_MASK); +} + +static void nested_svm_set_vmcb02_insn_bytes_fresh(struct vcpu_svm *svm, + bool from_hardware) +{ + svm->nested.vmcb02_insn_bytes_fresh =3D + from_hardware && static_cpu_has(X86_FEATURE_DECODEASSISTS) && + nested_svm_vmexit_has_insn_bytes(svm->vmcb); +} + +static void nested_svm_clear_vmcb02_insn_bytes(struct vcpu_svm *svm) +{ + nested_svm_clear_insn_bytes(svm->nested.vmcb02.ptr); + svm->nested.vmcb02_insn_bytes_fresh =3D false; +} + static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, struct x86_exception *fault, bool from_hardware) @@ -68,6 +100,7 @@ static void nested_svm_inject_npf_exit(struct kvm_vcpu *= vcpu, (fault->error_code & ~PFERR_GUEST_FAULT_STAGE_MASK); vmcb->control.exit_info_2 =3D fault->address; =20 + nested_svm_set_vmcb02_insn_bytes_fresh(svm, from_hardware); nested_svm_vmexit(svm); } =20 @@ -868,7 +901,9 @@ static void nested_vmcb02_prepare_control(struct vcpu_s= vm *svm) /* * Filled at exit: exit_code, exit_info_1, exit_info_2, exit_int_info, * exit_int_info_err, next_rip, insn_len, insn_bytes. + * Clear stale DecodeAssist data before L2 runs. */ + nested_svm_clear_vmcb02_insn_bytes(svm); =20 if (guest_cpu_cap_has(vcpu, X86_FEATURE_VGIF) && (vmcb12_ctrl->int_ctl & V_GIF_ENABLE_MASK)) @@ -1643,14 +1678,16 @@ static int nested_svm_intercept(struct vcpu_svm *sv= m) return vmexit; } =20 -int nested_svm_exit_handled(struct vcpu_svm *svm) +int nested_svm_exit_handled(struct vcpu_svm *svm, bool from_hardware) { int vmexit; =20 vmexit =3D nested_svm_intercept(svm); =20 - if (vmexit =3D=3D NESTED_EXIT_DONE) + if (vmexit =3D=3D NESTED_EXIT_DONE) { + nested_svm_set_vmcb02_insn_bytes_fresh(svm, from_hardware); nested_svm_vmexit(svm); + } =20 return vmexit; } diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index c7c1f1527c3c..5426a9669053 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -2571,7 +2571,7 @@ static bool check_selective_cr0_intercepted(struct kv= m_vcpu *vcpu, =20 if (cr0 ^ val) { svm->vmcb->control.exit_code =3D SVM_EXIT_CR0_SEL_WRITE; - ret =3D (nested_svm_exit_handled(svm) =3D=3D NESTED_EXIT_DONE); + ret =3D (nested_svm_exit_handled(svm, false) =3D=3D NESTED_EXIT_DONE); } =20 return ret; @@ -3723,7 +3723,7 @@ static int svm_handle_exit(struct kvm_vcpu *vcpu, fas= tpath_t exit_fastpath) vmexit =3D nested_svm_exit_special(svm); =20 if (vmexit =3D=3D NESTED_EXIT_CONTINUE) - vmexit =3D nested_svm_exit_handled(svm); + vmexit =3D nested_svm_exit_handled(svm, true); =20 if (vmexit =3D=3D NESTED_EXIT_DONE) return 1; @@ -4983,7 +4983,7 @@ static int svm_check_intercept(struct kvm_vcpu *vcpu, if (static_cpu_has(X86_FEATURE_NRIPS)) vmcb->control.next_rip =3D info->next_rip; vmcb->control.exit_code =3D icpt_info.exit_code; - vmexit =3D nested_svm_exit_handled(svm); + vmexit =3D nested_svm_exit_handled(svm, false); =20 ret =3D (vmexit =3D=3D NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED : X86EMUL_CONTINUE; diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 66b44b54608e..610def16f700 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -242,6 +242,9 @@ struct svm_nested_state { * on its side. */ bool force_msr_bitmap_recalc; + + /* True if VMCB02 has instruction bytes from the current hardware exit. */ + bool vmcb02_insn_bytes_fresh; }; =20 struct vcpu_sev_es_state { @@ -887,7 +890,7 @@ static inline void nested_svm_simple_vmexit(struct vcpu= _svm *svm, u32 exit_code) nested_svm_vmexit(svm); } =20 -int nested_svm_exit_handled(struct vcpu_svm *svm); +int nested_svm_exit_handled(struct vcpu_svm *svm, bool from_hardware); int nested_svm_check_permissions(struct kvm_vcpu *vcpu); int nested_svm_check_cached_vmcb12(struct kvm_vcpu *vcpu); int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, --=20 2.43.7 From nobody Mon Sep 28 08:57:48 2026 Received: from out28-98.mail.aliyun.com (out28-98.mail.aliyun.com [115.124.28.98]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9526F41D106; Mon, 24 Aug 2026 12:40:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.98 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787575237; cv=none; b=gNX/VMSHo+U/lrMzZV4/hD09pYIqhZYf7Ntm00vBqSoXFOwQ2Y/3HQKxfWgygfW6NskoaQylXQVr4CMaigyCkAlO+lZspvQgN9ikfJDTlRZmjTSJi9TZZrHnpST5pzvrPpli88vWJwHabCVMp0MzOi3w5Nu3FFMDifBeVVp1L/Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787575237; c=relaxed/simple; bh=wDy/Py089/L7PFM09ZV1p73EN303ObxO58eeY3f9z3k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ROiY7OcCg5D/RHd3lhqw3UxRHZyt31UTbc9L48MwGiApeWHNE5zFE/VsZ5yRmz5WMtGijkTkulnyUM+BDn/SUDC5jqQ1ND3M92nfuFFqmGMOfMkjT13NKbReQnY8Rv1B76Kg5jABNx3TOCxwDeR6KqAWewgvzGxDOsUlpSzIMGY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=115.124.28.98 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam: AC=CONTINUE;BC=0.07436831|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_regular_dialog|0.00510203-0.00091654-0.993981;FP=13826171909849165819|1|1|1|0|-1|-1|-1;HT=maildocker-contentspam033037026024;MF=zhang_wei@open-hieco.net;NM=1;PH=DS;RN=9;RT=9;SR=0;TI=SMTPD_---.iw1gh3c_1787575230; Received: from localhost.localdomain(mailfrom:zhang_wei@open-hieco.net fp:SMTPD_---.iw1gh3c_1787575230 cluster:ay29) by smtp.aliyun-inc.com; Mon, 24 Aug 2026 20:40:31 +0800 From: Tina Zhang To: Sean Christopherson , Jim Mattson , kvm@vger.kernel.org Cc: Paolo Bonzini , Shuah Khan , zhouyanjing@hygon.cn, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Tina Zhang Subject: [PATCH v5 4/8] KVM: nSVM: Propagate hardware DecodeAssist bytes to VMCB12 Date: Mon, 24 Aug 2026 20:39:50 +0800 Message-ID: <20260824123954.315112-5-zhang_wei@open-hieco.net> X-Mailer: git-send-email 2.43.7 In-Reply-To: <20260824123954.315112-1-zhang_wei@open-hieco.net> References: <20260824123954.315112-1-zhang_wei@open-hieco.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" DecodeAssists provides instruction bytes for nested page faults and intercepted page faults caused by data accesses. When the feature is exposed to L1, copy fresh hardware-provided instruction bytes from VMCB02 to VMCB12 for these exits. Clear the VMCB12 instruction-byte state before rebuilding it, and leave the length zero for instruction-fetch page faults, unrelated exits, and exits without fresh hardware bytes. Signed-off-by: Tina Zhang --- arch/x86/kvm/svm/nested.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86/kvm/svm/nested.c index 6770721d4e4c..2db0ec66e8dc 100644 --- a/arch/x86/kvm/svm/nested.c +++ b/arch/x86/kvm/svm/nested.c @@ -42,6 +42,20 @@ static void nested_svm_clear_insn_bytes(struct vmcb *vmc= b) sizeof(vmcb->control.insn_bytes)); } =20 +static void nested_svm_copy_insn_bytes(struct vmcb *to, + const struct vmcb *from) +{ + u8 insn_len =3D from->control.insn_len; + + nested_svm_clear_insn_bytes(to); + + if (WARN_ON_ONCE(insn_len > sizeof(from->control.insn_bytes))) + return; + + to->control.insn_len =3D insn_len; + memcpy(to->control.insn_bytes, from->control.insn_bytes, insn_len); +} + static bool nested_svm_vmexit_has_insn_bytes(const struct vmcb *vmcb) { u64 exit_code =3D vmcb->control.exit_code; @@ -67,6 +81,25 @@ static void nested_svm_clear_vmcb02_insn_bytes(struct vc= pu_svm *svm) svm->nested.vmcb02_insn_bytes_fresh =3D false; } =20 +static void nested_svm_update_vmcb12_insn_bytes(struct kvm_vcpu *vcpu, + struct vmcb *vmcb12, + const struct vmcb *vmcb02) +{ + struct vcpu_svm *svm =3D to_svm(vcpu); + + nested_svm_clear_insn_bytes(vmcb12); + + if (!guest_cpu_cap_has(vcpu, X86_FEATURE_DECODEASSISTS) || + !nested_svm_vmexit_has_insn_bytes(vmcb02)) + goto out; + + if (svm->nested.vmcb02_insn_bytes_fresh) + nested_svm_copy_insn_bytes(vmcb12, vmcb02); + +out: + svm->nested.vmcb02_insn_bytes_fresh =3D false; +} + static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, struct x86_exception *fault, bool from_hardware) @@ -1332,6 +1365,8 @@ static int nested_svm_vmexit_update_vmcb12(struct kvm= _vcpu *vcpu) if (guest_cpu_cap_has(vcpu, X86_FEATURE_NRIPS)) vmcb12->control.next_rip =3D vmcb02->control.next_rip; =20 + nested_svm_update_vmcb12_insn_bytes(vcpu, vmcb12, vmcb02); + if (nested_vmcb12_has_lbrv(vcpu)) svm_copy_lbrs(&vmcb12->save, &vmcb02->save); =20 --=20 2.43.7 From nobody Mon Sep 28 08:57:48 2026 Received: from out198-14.us.a.mail.aliyun.com (out198-14.us.a.mail.aliyun.com [47.90.198.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E27DC4119ED; Mon, 24 Aug 2026 12:46:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=47.90.198.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787575570; cv=none; b=Rz75SH9BNTC2xsg597KukibDaniroSNxHjxUYb/JEzac2kSMVHYC6RBABAS96BXlzQzcOBAHLCY9LOJGws0zS1DW+5aRNJQbGgM98yeUuArr44FD1Bb0y2luT9A7o4EY95GoyGCB5uz3g3jgPVfLP/tRZfQENz3fXuaEpKkqLrM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787575570; c=relaxed/simple; bh=NbUXxaSExkfSwtv9zczV8ia4rzqoGBgHWA5soURC0fo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=defVBMhesDdpx1wtj+nF8azdZDXNV3WrsydcByjEuFjhL+ZuYdR0NH2avnrNpCl3LVNcUkU7mcQEgmQ4wc1AoMdxjFvT+VhFdpW9dX8YhU9hJDvfN5bXrYoP2IRwuyAF/OCe3SJwX7eMdBe0OEOzn1COyeT1TRweGYjZuoD4IBA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=47.90.198.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam: AC=CONTINUE;BC=0.0743627|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_alarm|0.00334544-0.000799676-0.995855;FP=18368052134460067323|1|1|1|0|-1|-1|-1;HT=maildocker-contentspam033068016216;MF=zhang_wei@open-hieco.net;NM=1;PH=DS;RN=9;RT=9;SR=0;TI=SMTPD_---.iw1gh6p_1787575231; Received: from localhost.localdomain(mailfrom:zhang_wei@open-hieco.net fp:SMTPD_---.iw1gh6p_1787575231 cluster:ay29) by smtp.aliyun-inc.com; Mon, 24 Aug 2026 20:40:32 +0800 From: Tina Zhang To: Sean Christopherson , Jim Mattson , kvm@vger.kernel.org Cc: Paolo Bonzini , Shuah Khan , zhouyanjing@hygon.cn, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Tina Zhang Subject: [PATCH v5 5/8] KVM: nSVM: Use emulator bytes for synthesized nested #NPF Date: Mon, 24 Aug 2026 20:39:51 +0800 Message-ID: <20260824123954.315112-6-zhang_wei@open-hieco.net> X-Mailer: git-send-email 2.43.7 In-Reply-To: <20260824123954.315112-1-zhang_wei@open-hieco.net> References: <20260824123954.315112-1-zhang_wei@open-hieco.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SVM DecodeAssists provides instruction bytes for data-access #NPF exits. Hardware-reflected VM-Exits can use fresh VMCB02 bytes, but a KVM-synthesized #NPF has no hardware byte state to propagate. Use the emulator fetch cache when the nested #NPF is the current emulator exception. Store the bytes in a one-shot buffer that is consumed while constructing VMCB12 and cleared before the next nested run, preventing an unrelated nested VM-Exit from reusing stale emulator bytes. Signed-off-by: Tina Zhang --- arch/x86/kvm/svm/nested.c | 50 ++++++++++++++++++++++++++++++++++++++- arch/x86/kvm/svm/svm.h | 12 ++++++++++ 2 files changed, 61 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86/kvm/svm/nested.c index 2db0ec66e8dc..635ff20cc431 100644 --- a/arch/x86/kvm/svm/nested.c +++ b/arch/x86/kvm/svm/nested.c @@ -81,11 +81,45 @@ static void nested_svm_clear_vmcb02_insn_bytes(struct v= cpu_svm *svm) svm->nested.vmcb02_insn_bytes_fresh =3D false; } =20 +static void nested_svm_clear_synthesized_insn_bytes(struct vcpu_svm *svm) +{ + svm->nested.synthesized_insn_bytes.prepared =3D false; + svm->nested.synthesized_insn_bytes.insn_len =3D 0; +} + +static void nested_svm_prepare_synthesized_insn_bytes(struct kvm_vcpu *vcp= u) +{ + struct vcpu_svm *svm =3D to_svm(vcpu); + struct nested_svm_insn_bytes *synthesized =3D + &svm->nested.synthesized_insn_bytes; + struct x86_emulate_ctxt *ctxt =3D vcpu->arch.emulate_ctxt; + + static_assert(sizeof(synthesized->insn_bytes) >=3D + sizeof(ctxt->fetch.data)); + + nested_svm_clear_synthesized_insn_bytes(svm); + + if (!guest_cpu_cap_has(vcpu, X86_FEATURE_DECODEASSISTS)) + return; + + if (!ctxt || ctxt->eip !=3D kvm_rip_read(vcpu) || + ctxt->fetch.end < ctxt->fetch.data || + ctxt->fetch.end > ctxt->fetch.data + sizeof(ctxt->fetch.data)) + return; + + synthesized->insn_len =3D ctxt->fetch.end - ctxt->fetch.data; + memcpy(synthesized->insn_bytes, ctxt->fetch.data, + synthesized->insn_len); + synthesized->prepared =3D true; +} + static void nested_svm_update_vmcb12_insn_bytes(struct kvm_vcpu *vcpu, struct vmcb *vmcb12, const struct vmcb *vmcb02) { struct vcpu_svm *svm =3D to_svm(vcpu); + struct nested_svm_insn_bytes *synthesized =3D + &svm->nested.synthesized_insn_bytes; =20 nested_svm_clear_insn_bytes(vmcb12); =20 @@ -93,11 +127,20 @@ static void nested_svm_update_vmcb12_insn_bytes(struct= kvm_vcpu *vcpu, !nested_svm_vmexit_has_insn_bytes(vmcb02)) goto out; =20 - if (svm->nested.vmcb02_insn_bytes_fresh) + if (svm->nested.vmcb02_insn_bytes_fresh) { nested_svm_copy_insn_bytes(vmcb12, vmcb02); + goto out; + } + + if (synthesized->prepared) { + vmcb12->control.insn_len =3D synthesized->insn_len; + memcpy(vmcb12->control.insn_bytes, synthesized->insn_bytes, + vmcb12->control.insn_len); + } =20 out: svm->nested.vmcb02_insn_bytes_fresh =3D false; + nested_svm_clear_synthesized_insn_bytes(svm); } =20 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, @@ -106,6 +149,8 @@ static void nested_svm_inject_npf_exit(struct kvm_vcpu = *vcpu, { struct vcpu_svm *svm =3D to_svm(vcpu); struct vmcb *vmcb =3D svm->vmcb; + struct x86_emulate_ctxt *ctxt =3D vcpu->arch.emulate_ctxt; + bool from_emulation =3D ctxt && fault =3D=3D &ctxt->exception; u64 fault_stage; =20 /* @@ -134,6 +179,8 @@ static void nested_svm_inject_npf_exit(struct kvm_vcpu = *vcpu, vmcb->control.exit_info_2 =3D fault->address; =20 nested_svm_set_vmcb02_insn_bytes_fresh(svm, from_hardware); + if (from_emulation && !(fault->error_code & PFERR_FETCH_MASK)) + nested_svm_prepare_synthesized_insn_bytes(vcpu); nested_svm_vmexit(svm); } =20 @@ -937,6 +984,7 @@ static void nested_vmcb02_prepare_control(struct vcpu_s= vm *svm) * Clear stale DecodeAssist data before L2 runs. */ nested_svm_clear_vmcb02_insn_bytes(svm); + nested_svm_clear_synthesized_insn_bytes(svm); =20 if (guest_cpu_cap_has(vcpu, X86_FEATURE_VGIF) && (vmcb12_ctrl->int_ctl & V_GIF_ENABLE_MASK)) diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 610def16f700..9344707e9ffd 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -209,6 +209,12 @@ struct vmcb_ctrl_area_cached { }; }; =20 +struct nested_svm_insn_bytes { + bool prepared; + u8 insn_len; + u8 insn_bytes[X86_MAX_INSTRUCTION_LENGTH]; +}; + struct svm_nested_state { struct kvm_vmcb_info vmcb02; u64 hsave_msr; @@ -245,6 +251,12 @@ struct svm_nested_state { =20 /* True if VMCB02 has instruction bytes from the current hardware exit. */ bool vmcb02_insn_bytes_fresh; + + /* + * Cached instruction bytes for the current synthesized nested #NPF. + * Valid until the corresponding nested VM-Exit is constructed. + */ + struct nested_svm_insn_bytes synthesized_insn_bytes; }; =20 struct vcpu_sev_es_state { --=20 2.43.7 From nobody Mon Sep 28 08:57:48 2026 Received: from out28-171.mail.aliyun.com (out28-171.mail.aliyun.com [115.124.28.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B9A7408614; Mon, 24 Aug 2026 12:46:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787575564; cv=none; b=dvMy6Xuc+4ChqKK92NmQK33dy0i8+uk5nZnDPLvLsP0CNWPaz1UHvwiguVjuG+pIgyuCbyaQwhWQbFSWJE8sUDt1ZCFtQzM75mTRZCS+jiBwA8oHqBBtCs9qPI1D9qK3dzbDZjrHOg84ZIXNhKI2Bgpnu7ZOPLGSi2GQR1UElmY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787575564; c=relaxed/simple; bh=HTsTrf3GS8focgENfcnW4GUKxWGfWXBsY/M9EnYLQ54=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Z2E2Z3HYjAKVqbTll1e/FjkErygdpBF/gjx57mKDC3T15BJuQ1CPAlezgquD3PZv3Fy77YcTJRnIwIkz/a+v8HsGheK9CwhbASfgIFZNqYWC39oy6znDQ3iVonjDjqxeJwZIdITH8vPAgAxy04zgKHbaaYd5mVjd35l0XOx6lDA= ARC-Authentication-Results: i=1; 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charset="utf-8" For a synthesized #NPF, the emulator fetch cache is not guaranteed to contain the full architected 15-byte DecodeAssist window, e.g. it may contain only the bytes needed to decode the instruction. Keep preparation of synthesized state limited to capturing a matching emulator fetch cache for #NPF. When constructing VMCB12, copy those bytes and fetch any missing tail through L2 guest page tables. If no emulator bytes are available, fetch the full window from L2 RIP, including for a queued or synthesized #PF VM-Exit. Stop at a translation fault, read failure, non-canonical address, or CS limit overrun. For a non-64-bit L2, truncate each incremented linear address to 32 bits so that a fetch whose CS.base makes it cross the 4GB boundary wraps as required. Do not perform tail or fallback reads for SEV guests. KVM cannot read plaintext instruction bytes from encrypted guest memory, and the existing SEV emulation path treats missing hardware DecodeAssist bytes as unavailable instead of decoding guest memory. For nested SEV, report only matching emulator bytes already captured for a synthesized #NPF, potentially a zero instruction-byte count. Signed-off-by: Tina Zhang --- arch/x86/kvm/svm/nested.c | 58 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 57 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86/kvm/svm/nested.c index 635ff20cc431..c677ad5df8d6 100644 --- a/arch/x86/kvm/svm/nested.c +++ b/arch/x86/kvm/svm/nested.c @@ -87,6 +87,54 @@ static void nested_svm_clear_synthesized_insn_bytes(stru= ct vcpu_svm *svm) svm->nested.synthesized_insn_bytes.insn_len =3D 0; } =20 +static u8 nested_svm_fetch_insn_bytes(struct kvm_vcpu *vcpu, u8 *bytes, + u8 count, u8 max_bytes) +{ + struct kvm_pagewalk *gva_walk =3D &vcpu->arch.gva_walk; + u64 access =3D PFERR_FETCH_MASK; + gva_t rip =3D kvm_get_linear_rip(vcpu); + struct x86_exception e; + + if (kvm_x86_call(get_cpl)(vcpu) =3D=3D 3) + access |=3D PFERR_USER_MASK; + + if (!is_64_bit_mode(vcpu)) { + u32 eip =3D kvm_rip_read(vcpu); + u32 limit =3D to_svm(vcpu)->vmcb->save.cs.limit; + + if (eip > limit) + return 0; + max_bytes =3D min_t(u64, max_bytes, (u64)limit - eip + 1); + } + + count =3D min(count, max_bytes); + + while (count < max_bytes) { + gva_t addr =3D rip + count; + unsigned int chunk; + gpa_t gpa; + + if (!is_64_bit_mode(vcpu)) + addr =3D (u32)addr; + else if (is_noncanonical_address(addr, vcpu, 0)) + break; + + chunk =3D min_t(unsigned int, max_bytes - count, + PAGE_SIZE - offset_in_page(addr)); + gpa =3D gva_walk->gva_to_gpa(vcpu, gva_walk, addr, access, &e); + + if (gpa =3D=3D INVALID_GPA || + kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(gpa), + bytes + count, + offset_in_page(gpa), chunk)) + break; + + count +=3D chunk; + } + + return count; +} + static void nested_svm_prepare_synthesized_insn_bytes(struct kvm_vcpu *vcp= u) { struct vcpu_svm *svm =3D to_svm(vcpu); @@ -120,6 +168,7 @@ static void nested_svm_update_vmcb12_insn_bytes(struct = kvm_vcpu *vcpu, struct vcpu_svm *svm =3D to_svm(vcpu); struct nested_svm_insn_bytes *synthesized =3D &svm->nested.synthesized_insn_bytes; + const u8 max_bytes =3D sizeof(vmcb12->control.insn_bytes); =20 nested_svm_clear_insn_bytes(vmcb12); =20 @@ -135,9 +184,16 @@ static void nested_svm_update_vmcb12_insn_bytes(struct= kvm_vcpu *vcpu, if (synthesized->prepared) { vmcb12->control.insn_len =3D synthesized->insn_len; memcpy(vmcb12->control.insn_bytes, synthesized->insn_bytes, - vmcb12->control.insn_len); + synthesized->insn_len); } =20 + if (!is_sev_guest(vcpu)) + vmcb12->control.insn_len =3D + nested_svm_fetch_insn_bytes(vcpu, + vmcb12->control.insn_bytes, + vmcb12->control.insn_len, + max_bytes); + out: svm->nested.vmcb02_insn_bytes_fresh =3D false; nested_svm_clear_synthesized_insn_bytes(svm); --=20 2.43.7 From nobody Mon Sep 28 08:57:48 2026 Received: from out28-193.mail.aliyun.com (out28-193.mail.aliyun.com [115.124.28.193]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8022241A76F; Mon, 24 Aug 2026 12:40:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.193 ARC-Seal: i=1; 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charset="utf-8" Advertise DecodeAssists to L1 now that KVM virtualizes the guest-visible DecodeAssist state in VMCB12: EXITINFO1 decode data for MOV CR/DR, INTn, and INVLPG exits, plus instruction bytes for nested page faults and intercepted #PF exits. INVLPGA's linear address remains available directly from the saved guest rAX, as required by the APM. Expose the feature only when supported by hardware, as KVM still relies on hardware DecodeAssists for VM-Exits that are reflected directly from L2. With DecodeAssists exposed, QEMU configurations that require the feature (e.g. "-cpu ...,+decodeassists,...,enforce") are no longer rejected. Signed-off-by: Tina Zhang Reviewed-by: Jim Mattson --- arch/x86/kvm/cpuid.c | 1 + arch/x86/kvm/svm/svm.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index ddb022cb203a..b644e45eac71 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -1208,6 +1208,7 @@ void kvm_initialize_cpu_caps(void) VENDOR_F(NPT), VENDOR_F(VMCBCLEAN), VENDOR_F(FLUSHBYASID), + VENDOR_F(DECODEASSISTS), VENDOR_F(NRIPS), VENDOR_F(TSCRATEMSR), VENDOR_F(V_VMSAVE_VMLOAD), diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 5426a9669053..a99a1dc3426f 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -5560,6 +5560,8 @@ static __init void svm_set_cpu_caps(void) */ kvm_cpu_cap_set(X86_FEATURE_FLUSHBYASID); =20 + kvm_cpu_cap_check_and_set(X86_FEATURE_DECODEASSISTS); + if (nrips) kvm_cpu_cap_set(X86_FEATURE_NRIPS); =20 --=20 2.43.7 From nobody Mon Sep 28 08:57:48 2026 Received: from out28-145.mail.aliyun.com (out28-145.mail.aliyun.com [115.124.28.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8D4741D21E; Mon, 24 Aug 2026 12:40:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.145 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787575251; cv=none; b=eAfHPfoKDrzxOKAqxH/zd/k4UCWmCa7iQMyOBEi8BPnvwkDxPB/awRpdzWaL5tfoa3D+jrgpx+JD1sAZsIN4Qcn+sMJ2mW8ScvjzKO72X0JWU1V6Tn3KqbgBGPYnRSKYoJKaQX1kyvFJHiDm9Gh1AQkfP2EPHFOQqnDrw22wVvA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787575251; c=relaxed/simple; bh=wpLTFODlPNu22vOKWXcsbNw7KZWKN51JGFohTV4ndBU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fPS3qcRHmy/BDxRQu0uw6k1LUgsOwgtzSfloHaFkjGxY7VcbXJKQDtzKP41MyOxsVOPZJ39rNGF/MRn6olu00VrUZ/X+/NHmzsYHtzd85uXEycX8So+eSXuWxygsFjEQntyCuijPf4qmpmDkIdbQWGtcOUXkIXUlkJ+ydzrLCU8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=115.124.28.145 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam: AC=CONTINUE;BC=0.07436259|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_alarm|0.00146918-9.3346e-06-0.998522;FP=12665045987995750281|1|1|1|0|-1|-1|-1;HT=maildocker-contentspam033037022039;MF=zhang_wei@open-hieco.net;NM=1;PH=DS;RN=9;RT=9;SR=0;TI=SMTPD_---.iw1ghKh_1787575236; Received: from localhost.localdomain(mailfrom:zhang_wei@open-hieco.net fp:SMTPD_---.iw1ghKh_1787575236 cluster:ay29) by smtp.aliyun-inc.com; Mon, 24 Aug 2026 20:40:37 +0800 From: Tina Zhang To: Sean Christopherson , Jim Mattson , kvm@vger.kernel.org Cc: Paolo Bonzini , Shuah Khan , zhouyanjing@hygon.cn, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Tina Zhang Subject: [PATCH v5 8/8] KVM: selftests: Add nested SVM DecodeAssists test Date: Mon, 24 Aug 2026 20:39:54 +0800 Message-ID: <20260824123954.315112-9-zhang_wei@open-hieco.net> X-Mailer: git-send-email 2.43.7 In-Reply-To: <20260824123954.315112-1-zhang_wei@open-hieco.net> References: <20260824123954.315112-1-zhang_wei@open-hieco.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a focused nested SVM selftest for DecodeAssists. Verify that KVM exposes the feature to L1 and synthesizes EXITINFO for representative MOV CR/DR, CLTS, INTn, INVLPG, and INVLPGA intercepts. Exercise instruction bytes for hardware and synthesized #NPF/#PF exits. Cover a synthesized #NPF that follows a hardware #NPF in the same emulated instruction, truncated on-demand fetching at an unreadable page, and the absence of instruction bytes for an instruction-fetch #PF. The synthesized OUTSB #NPF runs by default. The synthesized #PF and instruction-intercept cases run when kvm.force_emulation_prefix=3D1 is enabled. Signed-off-by: Tina Zhang --- tools/testing/selftests/kvm/Makefile.kvm | 1 + .../selftests/kvm/include/x86/processor.h | 1 + .../kvm/x86/svm_nested_decode_assists_test.c | 482 ++++++++++++++++++ 3 files changed, 484 insertions(+) create mode 100644 tools/testing/selftests/kvm/x86/svm_nested_decode_assis= ts_test.c diff --git a/tools/testing/selftests/kvm/Makefile.kvm b/tools/testing/selft= ests/kvm/Makefile.kvm index 00123169a190..41a3db9a386b 100644 --- a/tools/testing/selftests/kvm/Makefile.kvm +++ b/tools/testing/selftests/kvm/Makefile.kvm @@ -118,6 +118,7 @@ TEST_GEN_PROGS_x86 +=3D x86/vmx_preemption_timer_test TEST_GEN_PROGS_x86 +=3D x86/svm_vmcall_test TEST_GEN_PROGS_x86 +=3D x86/svm_int_ctl_test TEST_GEN_PROGS_x86 +=3D x86/svm_nested_clear_efer_svme +TEST_GEN_PROGS_x86 +=3D x86/svm_nested_decode_assists_test TEST_GEN_PROGS_x86 +=3D x86/svm_nested_shutdown_test TEST_GEN_PROGS_x86 +=3D x86/svm_nested_soft_inject_test TEST_GEN_PROGS_x86 +=3D x86/svm_nested_vmcb12_gpa diff --git a/tools/testing/selftests/kvm/include/x86/processor.h b/tools/te= sting/selftests/kvm/include/x86/processor.h index 6e6f70035508..e9d745a2c131 100644 --- a/tools/testing/selftests/kvm/include/x86/processor.h +++ b/tools/testing/selftests/kvm/include/x86/processor.h @@ -220,6 +220,7 @@ struct kvm_x86_cpu_feature { #define X86_FEATURE_LBRV KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 1) #define X86_FEATURE_NRIPS KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 3) #define X86_FEATURE_TSCRATEMSR KVM_X86_CPU_FEATURE(0x8000000A, 0,= EDX, 4) +#define X86_FEATURE_DECODEASSISTS KVM_X86_CPU_FEATURE(0x8000000A, 0,= EDX, 7) #define X86_FEATURE_PAUSEFILTER KVM_X86_CPU_FEATURE(0x8000000A, 0,= EDX, 10) #define X86_FEATURE_PFTHRESHOLD KVM_X86_CPU_FEATURE(0x8000000A, 0,= EDX, 12) #define X86_FEATURE_V_VMSAVE_VMLOAD KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX= , 15) diff --git a/tools/testing/selftests/kvm/x86/svm_nested_decode_assists_test= .c b/tools/testing/selftests/kvm/x86/svm_nested_decode_assists_test.c new file mode 100644 index 000000000000..7db8042a27c0 --- /dev/null +++ b/tools/testing/selftests/kvm/x86/svm_nested_decode_assists_test.c @@ -0,0 +1,482 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Test KVM's virtualization of SVM DecodeAssists for nested guests. + */ + +#include "test_util.h" +#include "kvm_util.h" +#include "processor.h" +#include "svm_util.h" + +#define TEST_INT_VECTOR 0x81 + +/* Any canonical virtual address that is never mapped by the selftest VM. = */ +#define PF_TEST_GVA BIT_ULL(40) +#define PF_FETCH_TEST_GVA BIT_ULL(41) + +#define OUTSB_OPCODE 0x6e +#define BOUNDARY_OUTSB_CODE_SIZE 15 +#define TEST_IOPM_SIZE (3 * PAGE_SIZE) + +static u8 npf_target[PAGE_SIZE] __aligned(PAGE_SIZE); +static u8 mmio_source __aligned(PAGE_SIZE); +static u8 boundary_outsb_code[2 * PAGE_SIZE] __aligned(PAGE_SIZE); + +static void l2_read_code(void) +{ + asm volatile("mov (%0), %%rax" : : "r"(&npf_target) : "rax", "memory"); + GUEST_FAIL("L2 read did not cause a nested page fault"); +} + +static void l2_outsb_code(void) +{ + asm volatile("mov %0, %%rsi\n\t" + "mov $0x80, %%dx\n\t" + "outsb" + : : "r"(&npf_target) : "rsi", "rdx", "memory"); + GUEST_FAIL("L2 OUTSB did not cause a nested page fault"); +} + +static void l2_movsb_code(void) +{ + asm volatile("mov %0, %%rsi\n\t" + "mov %1, %%rdi\n\t" + "movsb" + : : "r"(&mmio_source), "r"(&npf_target) + : "rsi", "rdi", "memory"); + GUEST_FAIL("L2 MOVSB did not cause a nested page fault"); +} + +static void l2_pf_code(void) +{ + asm volatile("mov (%0), %%rax" + : : "r"(PF_TEST_GVA) : "rax", "memory"); + GUEST_FAIL("L2 access to an unmapped VA did not #PF"); +} + +static void l2_fep_pf_code(void) +{ + asm volatile(KVM_FEP "mov (%0), %%rax" + : : "r"(PF_TEST_GVA) : "rax", "memory"); + GUEST_FAIL("L2 forced-emulated access to an unmapped VA did not #PF"); +} + +static void l2_fep_mov_from_cr4_code(void) +{ + asm volatile(KVM_FEP "mov %%cr4, %%r10" : : : "r10"); + GUEST_FAIL("L2 forced-emulated MOV-from-CR4 was not intercepted"); +} + +static void l2_fep_mov_to_dr7_code(void) +{ + asm volatile("mov %%dr7, %%rax\n\t" + "mov %%rax, %%rbx\n\t" + KVM_FEP "mov %%rbx, %%dr7" : : : "rax", "rbx"); + GUEST_FAIL("L2 forced-emulated MOV-to-DR7 was not intercepted"); +} + +static void l2_fep_clts_code(void) +{ + asm volatile(KVM_FEP "clts" : : : "memory"); + GUEST_FAIL("L2 forced-emulated CLTS was not intercepted"); +} + +static void l2_fep_int_code(void) +{ + asm volatile(KVM_FEP "int %0" : : "i"(TEST_INT_VECTOR)); + GUEST_FAIL("L2 forced-emulated INTn was not intercepted"); +} + +static void l2_fep_invlpg_code(void) +{ + asm volatile(KVM_FEP "invlpg (%0)" : : "r"(&npf_target) : "memory"); + GUEST_FAIL("L2 forced-emulated INVLPG was not intercepted"); +} + +static void l2_fep_invlpga_code(void) +{ + asm volatile(KVM_FEP "invlpga" + : : "a"(&npf_target), "c"(0) : "memory"); + GUEST_FAIL("L2 forced-emulated INVLPGA was not intercepted"); +} + +struct instruction_intercept_test { + const char *name; + void (*code)(void); + u64 intercept; + u32 intercept_cr; + u32 intercept_dr; + u64 exit_code; + u64 exit_info_1; + u64 exit_info_1_mask; + bool check_rax; + u64 rax; +}; + +static const struct instruction_intercept_test instruction_intercept_tests= [] =3D { + { + .name =3D "MOV-from-CR4", + .code =3D l2_fep_mov_from_cr4_code, + .intercept_cr =3D BIT(INTERCEPT_CR4_READ), + .exit_code =3D SVM_EXIT_READ_CR4, + .exit_info_1 =3D BIT_ULL(63) | 10, + .exit_info_1_mask =3D ~0ULL, + }, { + .name =3D "MOV-to-DR7", + .code =3D l2_fep_mov_to_dr7_code, + .intercept_dr =3D BIT(INTERCEPT_DR7_WRITE), + .exit_code =3D SVM_EXIT_WRITE_DR7, + .exit_info_1 =3D 3, + .exit_info_1_mask =3D ~0ULL, + }, { + .name =3D "CLTS", + .code =3D l2_fep_clts_code, + .intercept_cr =3D BIT(INTERCEPT_CR0_WRITE), + .exit_code =3D SVM_EXIT_WRITE_CR0, + .exit_info_1_mask =3D BIT_ULL(63), + }, { + .name =3D "INTn", + .code =3D l2_fep_int_code, + .intercept =3D BIT_ULL(INTERCEPT_INTn), + .exit_code =3D SVM_EXIT_SWINT, + .exit_info_1 =3D TEST_INT_VECTOR, + .exit_info_1_mask =3D ~0ULL, + }, { + .name =3D "INVLPG", + .code =3D l2_fep_invlpg_code, + .intercept =3D BIT_ULL(INTERCEPT_INVLPG), + .exit_code =3D SVM_EXIT_INVLPG, + .exit_info_1 =3D (u64)&npf_target, + .exit_info_1_mask =3D ~0ULL, + }, { + .name =3D "INVLPGA", + .code =3D l2_fep_invlpga_code, + .intercept =3D BIT_ULL(INTERCEPT_INVLPGA), + .exit_code =3D SVM_EXIT_INVLPGA, + .exit_info_1_mask =3D ~0ULL, + .check_rax =3D true, + .rax =3D (u64)&npf_target, + }, +}; + +static void assert_decode_assist_insn_bytes(struct vmcb *vmcb) +{ + GUEST_ASSERT(vmcb->control.insn_len); + GUEST_ASSERT(vmcb->control.insn_len <=3D + sizeof(vmcb->control.insn_bytes)); + GUEST_ASSERT(!memcmp(vmcb->control.insn_bytes, + (void *)vmcb->save.rip, + vmcb->control.insn_len)); +} + +static void assert_full_decode_assist_insn_bytes(struct vmcb *vmcb) +{ + GUEST_ASSERT_EQ(vmcb->control.insn_len, + sizeof(vmcb->control.insn_bytes)); + assert_decode_assist_insn_bytes(vmcb); +} + +static void prepare_l2_for_vmrun(struct svm_test_data *svm, gva_t rip) +{ + struct vmcb *vmcb =3D svm->vmcb; + + vmcb->save.rip =3D rip; + vmcb->save.rsp =3D (u64)svm->stack; +} + +static void run_intercept_test(struct svm_test_data *svm, + const struct instruction_intercept_test *test) +{ + struct vmcb *vmcb =3D svm->vmcb; + struct vmcb_control_area *control =3D &vmcb->control; + u64 expected_exit_info_1 =3D test->exit_info_1 & test->exit_info_1_mask; + + control->intercept |=3D test->intercept; + control->intercept_cr |=3D test->intercept_cr; + control->intercept_dr |=3D test->intercept_dr; + + control->exit_info_1 =3D ~0ULL; + control->exit_info_2 =3D ~0ULL; + prepare_l2_for_vmrun(svm, (u64)test->code); + + run_guest(vmcb, svm->vmcb_gpa); + + __GUEST_ASSERT(control->exit_code =3D=3D test->exit_code, + "%s: expected exit code %#lx, got %#lx", + test->name, (unsigned long)test->exit_code, + (unsigned long)control->exit_code); + __GUEST_ASSERT((control->exit_info_1 & test->exit_info_1_mask) =3D=3D + expected_exit_info_1, + "%s: expected EXITINFO1 %#lx with mask %#lx, got %#lx", + test->name, (unsigned long)expected_exit_info_1, + (unsigned long)test->exit_info_1_mask, + (unsigned long)control->exit_info_1); + __GUEST_ASSERT(!control->insn_len, + "%s: expected no instruction bytes, got %u", + test->name, control->insn_len); + + if (test->check_rax) + __GUEST_ASSERT(vmcb->save.rax =3D=3D test->rax, + "%s: expected rAX %#lx, got %#lx", + test->name, (unsigned long)test->rax, + (unsigned long)vmcb->save.rax); + + __GUEST_ASSERT(!control->exit_info_2, + "%s: expected EXITINFO2 to be clear, got %#lx", + test->name, (unsigned long)control->exit_info_2); + + control->intercept &=3D ~test->intercept; + control->intercept_cr &=3D ~test->intercept_cr; + control->intercept_dr &=3D ~test->intercept_dr; +} + +static void test_instruction_intercepts(struct svm_test_data *svm) +{ + int i; + + if (!is_forced_emulation_enabled) + return; + + for (i =3D 0; i < ARRAY_SIZE(instruction_intercept_tests); i++) + run_intercept_test(svm, &instruction_intercept_tests[i]); +} + +static void test_hardware_npf(struct svm_test_data *svm, gpa_t npf_gpa) +{ + struct vmcb *vmcb =3D svm->vmcb; + + prepare_l2_for_vmrun(svm, (u64)l2_read_code); + run_guest(vmcb, svm->vmcb_gpa); + GUEST_ASSERT_EQ(vmcb->control.exit_code, SVM_EXIT_NPF); + GUEST_ASSERT_EQ(vmcb->control.exit_info_2, npf_gpa); + assert_decode_assist_insn_bytes(vmcb); +} + +/* + * The IOIO intercept causes L0 to emulate OUTSB before accessing its sour= ce + * operand. The emulated read then faults on L1's NPT, resulting in a + * KVM-synthesized #NPF. + */ +static void test_synthesized_npf(struct svm_test_data *svm, gpa_t npf_gpa) +{ + struct vmcb *vmcb =3D svm->vmcb; + + prepare_l2_for_vmrun(svm, (u64)l2_outsb_code); + run_guest(vmcb, svm->vmcb_gpa); + GUEST_ASSERT_EQ(vmcb->control.exit_code, SVM_EXIT_NPF); + GUEST_ASSERT_EQ(vmcb->control.exit_info_2, npf_gpa); + assert_full_decode_assist_insn_bytes(vmcb); +} + +/* + * MOVSB first reads from MMIO, causing a hardware #NPF that L0 emulates. + * After userspace completes the read, the emulated destination write faul= ts + * on L1's NPT. The new #NPF must not reuse the original hardware exit's = GPA. + */ +static void test_synthesized_npf_after_hardware_npf(struct svm_test_data *= svm, + gpa_t npf_gpa) +{ + struct vmcb *vmcb =3D svm->vmcb; + + prepare_l2_for_vmrun(svm, (u64)l2_movsb_code); + run_guest(vmcb, svm->vmcb_gpa); + GUEST_ASSERT_EQ(vmcb->control.exit_code, SVM_EXIT_NPF); + GUEST_ASSERT_EQ(vmcb->control.exit_info_2, npf_gpa); + assert_full_decode_assist_insn_bytes(vmcb); +} + +/* + * OUTSB is the final byte of a mapped code page, and the following page is + * not present in L2's page tables. DecodeAssist byte fetching must stop = at + * the page boundary and report only the OUTSB opcode. + */ +static void test_synthesized_npf_truncated(struct svm_test_data *svm, + gpa_t npf_gpa) +{ + struct vmcb *vmcb =3D svm->vmcb; + + prepare_l2_for_vmrun(svm, + (u64)&boundary_outsb_code[PAGE_SIZE - + BOUNDARY_OUTSB_CODE_SIZE]); + run_guest(vmcb, svm->vmcb_gpa); + GUEST_ASSERT_EQ(vmcb->control.exit_code, SVM_EXIT_NPF); + GUEST_ASSERT_EQ(vmcb->control.exit_info_2, npf_gpa); + GUEST_ASSERT_EQ(vmcb->save.rip, + (u64)&boundary_outsb_code[PAGE_SIZE - 1]); + GUEST_ASSERT_EQ(vmcb->control.insn_len, 1); + GUEST_ASSERT_EQ(vmcb->control.insn_bytes[0], OUTSB_OPCODE); +} + +static void test_hardware_intercepted_pf(struct svm_test_data *svm) +{ + struct vmcb *vmcb =3D svm->vmcb; + + prepare_l2_for_vmrun(svm, (u64)l2_pf_code); + run_guest(vmcb, svm->vmcb_gpa); + GUEST_ASSERT_EQ(vmcb->control.exit_code, SVM_EXIT_EXCP_BASE + PF_VECTOR); + GUEST_ASSERT_EQ(vmcb->control.exit_info_2, PF_TEST_GVA); + GUEST_ASSERT(!(vmcb->control.exit_info_1 & PFERR_PRESENT_MASK)); + GUEST_ASSERT(!(vmcb->control.exit_info_1 & PFERR_FETCH_MASK)); + assert_decode_assist_insn_bytes(vmcb); +} + +static void test_hardware_intercepted_fetch_pf(struct svm_test_data *svm) +{ + struct vmcb *vmcb =3D svm->vmcb; + + prepare_l2_for_vmrun(svm, PF_FETCH_TEST_GVA); + run_guest(vmcb, svm->vmcb_gpa); + GUEST_ASSERT_EQ(vmcb->control.exit_code, SVM_EXIT_EXCP_BASE + PF_VECTOR); + GUEST_ASSERT_EQ(vmcb->control.exit_info_2, PF_FETCH_TEST_GVA); + GUEST_ASSERT(!(vmcb->control.exit_info_1 & PFERR_PRESENT_MASK)); + GUEST_ASSERT(vmcb->control.exit_info_1 & PFERR_FETCH_MASK); + GUEST_ASSERT_EQ(vmcb->control.insn_len, 0); +} + +static void test_synthesized_pf(struct svm_test_data *svm) +{ + struct vmcb *vmcb =3D svm->vmcb; + + if (!is_forced_emulation_enabled) + return; + + prepare_l2_for_vmrun(svm, (u64)l2_fep_pf_code); + run_guest(vmcb, svm->vmcb_gpa); + GUEST_ASSERT_EQ(vmcb->control.exit_code, SVM_EXIT_EXCP_BASE + PF_VECTOR); + GUEST_ASSERT_EQ(vmcb->control.exit_info_2, PF_TEST_GVA); + GUEST_ASSERT(!(vmcb->control.exit_info_1 & PFERR_PRESENT_MASK)); + GUEST_ASSERT(!(vmcb->control.exit_info_1 & PFERR_FETCH_MASK)); + assert_full_decode_assist_insn_bytes(vmcb); +} + +static void l1_guest_code(struct svm_test_data *svm, gpa_t npf_gpa, + gpa_t iopm_gpa) +{ + struct vmcb *vmcb =3D svm->vmcb; + + GUEST_ASSERT(this_cpu_has(X86_FEATURE_DECODEASSISTS)); + + generic_svm_setup(svm, l2_read_code); + vmcb->control.iopm_base_pa =3D iopm_gpa; + + vmcb->control.intercept |=3D BIT_ULL(INTERCEPT_IOIO_PROT); + vmcb->control.intercept_exceptions |=3D 1U << PF_VECTOR; + + test_hardware_npf(svm, npf_gpa); + test_synthesized_npf(svm, npf_gpa); + test_synthesized_npf_after_hardware_npf(svm, npf_gpa); + test_synthesized_npf_truncated(svm, npf_gpa); + test_hardware_intercepted_pf(svm); + test_hardware_intercepted_fetch_pf(svm); + test_synthesized_pf(svm); + test_instruction_intercepts(svm); + + GUEST_DONE(); +} + +static void build_boundary_outsb_code(u8 *code) +{ + u64 source =3D (u64)&npf_target; + + /* movabs $npf_target, %rsi */ + code[0] =3D 0x48; + code[1] =3D 0xbe; + memcpy(&code[2], &source, sizeof(source)); + + /* mov $0x80, %dx; outsb */ + code[10] =3D 0x66; + code[11] =3D 0xba; + code[12] =3D 0x80; + code[13] =3D 0x00; + code[14] =3D OUTSB_OPCODE; +} + +static void prepare_boundary_outsb_code(struct kvm_vm *vm) +{ + gva_t code_gva =3D (gva_t)&boundary_outsb_code[PAGE_SIZE - + BOUNDARY_OUTSB_CODE_SIZE]; + + build_boundary_outsb_code(addr_gva2hva(vm, code_gva)); +} + +static void complete_mmio_read(struct kvm_vcpu *vcpu, gpa_t expected_gpa, + u8 value) +{ + if (vcpu->run->exit_reason =3D=3D KVM_EXIT_IO) { + struct ucall uc; + + if (get_ucall(vcpu, &uc) =3D=3D UCALL_ABORT) + REPORT_GUEST_ASSERT(uc); + } + + TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_MMIO); + TEST_ASSERT(!vcpu->run->mmio.is_write, + "Expected an MMIO read, got a write"); + TEST_ASSERT_EQ(vcpu->run->mmio.phys_addr, expected_gpa); + TEST_ASSERT_EQ(vcpu->run->mmio.len, 1); + vcpu->run->mmio.data[0] =3D value; +} + +static void assert_ucall_done(struct kvm_vcpu *vcpu) +{ + struct ucall uc; + u64 actual; + + TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_IO); + actual =3D get_ucall(vcpu, &uc); + if (actual =3D=3D UCALL_ABORT) + REPORT_GUEST_ASSERT(uc); + + TEST_ASSERT_EQ(actual, UCALL_DONE); +} + +int main(int argc, char *argv[]) +{ + gva_t svm_gva, npf_gva, boundary_page_gva, iopm_gva; + gpa_t npf_gpa, mmio_source_gpa, mmio_gpa, iopm_gpa; + struct userspace_mem_region *region; + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + u64 *pte; + + TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_SVM)); + TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_NPT)); + TEST_REQUIRE(this_cpu_has(X86_FEATURE_DECODEASSISTS)); + TEST_ASSERT(kvm_cpu_has(X86_FEATURE_DECODEASSISTS), + "KVM failed to expose DecodeAssists"); + + vm =3D vm_create_with_one_vcpu(&vcpu, l1_guest_code); + prepare_boundary_outsb_code(vm); + vm_enable_npt(vm); + vcpu_alloc_svm(vm, &svm_gva); + iopm_gva =3D vm_alloc_pages(vm, TEST_IOPM_SIZE / PAGE_SIZE); + iopm_gpa =3D addr_gva2gpa(vm, iopm_gva); + memset(addr_gva2hva(vm, iopm_gva), 0, TEST_IOPM_SIZE); + npf_gva =3D (gva_t)&npf_target; + npf_gpa =3D addr_gva2gpa(vm, npf_gva); + + tdp_identity_map_default_memslots(vm); + pte =3D tdp_get_pte(vm, npf_gpa); + *pte &=3D ~PTE_PRESENT_MASK(&vm->stage2_mmu); + region =3D memslot2region(vm, 0); + mmio_gpa =3D region->region.guest_phys_addr + + region->region.memory_size + PAGE_SIZE; + mmio_source_gpa =3D addr_gva2gpa(vm, (gva_t)&mmio_source); + pte =3D tdp_get_pte(vm, mmio_source_gpa); + *pte =3D (*pte & ~PHYSICAL_PAGE_MASK) | mmio_gpa; + + boundary_page_gva =3D (gva_t)&boundary_outsb_code[PAGE_SIZE]; + pte =3D vm_get_pte(vm, boundary_page_gva); + *pte &=3D ~PTE_PRESENT_MASK(&vm->mmu); + + vcpu_args_set(vcpu, 3, svm_gva, npf_gpa, iopm_gpa); + + /* Complete the MOVSB source read. */ + vcpu_run(vcpu); + complete_mmio_read(vcpu, mmio_gpa, 0xa5); + vcpu_run(vcpu); + assert_ucall_done(vcpu); + + kvm_vm_free(vm); + return 0; +} --=20 2.43.7