From nobody Mon Sep 28 08:46:16 2026 Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com [209.85.210.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C711415B6C for ; Mon, 24 Aug 2026 12:24:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787574242; cv=none; b=XERtcSMrB+tC6PigLgFP6Zg9ojcOcowp4lH4uaq8cESIArr7f2jdkc11w1MzQqdblQU+uBD8lZJJt958Rb+RtRcxZ1/KFxStMwIrCOwBQuEQgfyyusIpO5SuRCkKvB8uhQ5jnZ5PDsZl2sCmI4HcSwdJawV6vAOmhNUG1cMb5Is= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787574242; c=relaxed/simple; bh=0FrHW9VyarVTWexh+cRfUDfEcUegknMlo0+I6quTFkM=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=cxs0/xbRNgA0PiUtW/+wBfpv0rAXs086GZDOrbx5J/CkS8tTBQFLWaz/0cnGJBRXVOwm6l1K9QIxHgtGpHQCressmDqlsffcxst8j6+IcspIU85JLWTdYxzWsqWqWDPBeH1BvddR0ZeqJ/ivpeEVOwqDQrG+rUQMCjJEzRUSB6s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--praan.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=mlX00zJK; arc=none smtp.client-ip=209.85.210.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--praan.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="mlX00zJK" Received: by mail-pf1-f198.google.com with SMTP id d2e1a72fcca58-84e048a801dso4844073b3a.3 for ; Mon, 24 Aug 2026 05:24:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20251104; t=1787574240; x=1788179040; darn=vger.kernel.org; h=content-type:cc:to:from:subject:message-id:references:mime-version :in-reply-to:date:from:to:cc:subject:date:message-id:reply-to :content-type; bh=yfYNwAoiWTPLSXTU/nHcpeXRO8BpM/FKM+cbWnkCGPk=; b=mlX00zJKvdtoLZc1UVTFWjrvh45OFfn0Kv3OkuxZrkJx0DqCs8JO90dg+Al/AaUCyd quO9cFvttzDpu+E4SdPK7/dFUxY90TMVmMITU9TJ+aKtZtV6AduV2s6VNJZJmonVziBT M0Bs8huU04MMTnXuuS8DNj7bSK+SCQRR58aAuB8U384FOH2pO9ErLABUju6oTH1npqF0 dAAY5ieJCagjxhQj8XoklBY1p4TJkksST+rUmTIH+YaOBohyYsO/TbNCxUaRNEXCSU40 mUBjolFlai+kVFEy8bpvkhzOUqdN10FY2L6OXCHEW3lsM6gRV5QFPbnAUfh1U3NXCn+v jiuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787574240; x=1788179040; h=content-type:cc:to:from:subject:message-id:references:mime-version :in-reply-to:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to:content-type; bh=yfYNwAoiWTPLSXTU/nHcpeXRO8BpM/FKM+cbWnkCGPk=; b=KUmSwJ8OQFKDF55MnqOh8ZTAAGNNA5bYrWrQBWTG3dKcSMXVMe3GRaFihF/abCoFdC x+MxISpYl/yIYAC8cJtb0PkZaZzYIejFGrLA/Rv07sPgBYv+H8q6lNFbeMK+wv7zYs96 NNo0IrXx5vKmW7BB3CNCqXBZUIjZ3asNr1qYakDzX9v6kRGdgTBKGBIuPHT3Gir8jOka a1zdshkToXQ0WLT6UF++EPJ2Hn/DH6wDZ3ckzaqCdXoHeg4BMBKDa/Y90oileC0ImgLb Fy6FLI87P22WcNsIoeCpfLrJUOtN5wArY98aXq5E9P0TgZ2IyBOcnHqAog/2Zlit4EMZ GLag== X-Forwarded-Encrypted: i=1; AHgh+RrA3ElI39W9YP0JZALI4bBFteesdXhyxAPN2ePN4mPfXhNkkYvyPetcv6E1GRipf7uUbKxVgoApdGk0doo=@vger.kernel.org X-Gm-Message-State: AFuF++m3JWukqlleMXpSkgpU3/fi46FL+6whGjIk3ZB0o2AHjewdHL/g DxXZPwaoSDpierymB880c8ilj3XXvrxtcnT2SjK4E8+eAqzidFczaEBvaqc05QRzABFdmzb42Da stw== X-Received: from pfdc3.prod.google.com ([2002:aa7:8c03:0:b0:84c:2e88:693d]) (user=praan job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:300c:b0:848:4859:a45 with SMTP id d2e1a72fcca58-8520b96630dmr33366040b3a.2.1787574237585; Mon, 24 Aug 2026 05:23:57 -0700 (PDT) Date: Mon, 24 Aug 2026 12:23:43 +0000 In-Reply-To: <20260824122347.1588592-1-praan@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260824122347.1588592-1-praan@google.com> X-Mailer: git-send-email 2.55.0.766.g2966f0265a-goog Message-ID: <20260824122347.1588592-2-praan@google.com> Subject: [PATCH v3 1/5] iommu/amd: Refactor device probe and capability initialization From: Pranjal Shrivastava To: iommu@lists.linux.dev, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Joerg Roedel , Suravee Suthikulpanit , Vasant Hegde , Ankit Soni , Jason Gunthorpe , Bjorn Helgaas , Samiullah Khawaja , Pranjal Shrivastava Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Restructure the device probe path to improve readability and prepare for cleaner error handling. Refactor check_device() into iommu_lookup_device to explicitly validate and return the amd_iommu ptr & devid. Refactor iommu_init_device() to return the allocated dev_data. Consolidate all PCI cap inits (MSI domains, PASID, ATS) into a new helper: iommu_init_device_caps(). Suggested-by: Vasant Hegde Signed-off-by: Pranjal Shrivastava Reviewed-by: Jason Gunthorpe Reviewed-by: Vasant Hegde --- drivers/iommu/amd/iommu.c | 117 +++++++++++++++++++------------------- 1 file changed, 60 insertions(+), 57 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 4c31294fabc5..e1f9fbb63837 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -675,7 +675,8 @@ static void pdev_disable_caps(struct pci_dev *pdev) * This function checks if the driver got a valid device from the caller to * avoid dereferencing invalid pointers. */ -static bool check_device(struct device *dev) +static bool iommu_lookup_device(struct device *dev, + struct amd_iommu **iommu_out, u16 *devid_out) { struct amd_iommu_pci_seg *pci_seg; struct amd_iommu *iommu; @@ -690,7 +691,7 @@ static bool check_device(struct device *dev) devid =3D PCI_SBDF_TO_DEVID(sbdf); =20 iommu =3D rlookup_amd_iommu(dev); - if (!iommu) + if (!iommu || !iommu->iommu.ops) return false; =20 /* Out of our scope? */ @@ -698,47 +699,33 @@ static bool check_device(struct device *dev) if (devid > pci_seg->last_bdf) return false; =20 + *iommu_out =3D iommu; + *devid_out =3D devid; return true; } =20 -static int iommu_init_device(struct amd_iommu *iommu, struct device *dev) +static struct iommu_dev_data *iommu_init_device(struct amd_iommu *iommu, + struct device *dev, u16 devid) { struct iommu_dev_data *dev_data; - int devid, sbdf; - - if (dev_iommu_priv_get(dev)) - return 0; =20 - sbdf =3D get_device_sbdf_id(dev); - if (sbdf < 0) - return sbdf; - - devid =3D PCI_SBDF_TO_DEVID(sbdf); dev_data =3D find_dev_data(iommu, devid); if (!dev_data) - return -ENOMEM; + return ERR_PTR(-ENOMEM); =20 dev_data->dev =3D dev; =20 /* - * The dev_iommu_priv_set() needes to be called before setup_aliases. + * The dev_iommu_priv_set() needs to be called before setup_aliases. * Otherwise, subsequent call to dev_iommu_priv_get() will fail. */ dev_iommu_priv_set(dev, dev_data); setup_aliases(iommu, dev); =20 - /* - * By default we use passthrough mode for IOMMUv2 capable device. - * But if amd_iommu=3Dforce_isolation is set (e.g. to debug DMA to - * invalid address), we ignore the capability for the device so - * it'll be forced to go into translation mode. - */ - if ((iommu_default_passthrough() || !amd_iommu_force_isolation) && - dev_is_pci(dev) && amd_iommu_gt_ppr_supported()) { - dev_data->flags =3D pdev_get_caps(to_pci_dev(dev)); - } + /* Wait for DTE updates to go through */ + iommu_completion_wait(iommu); =20 - return 0; + return dev_data; } =20 static void iommu_ignore_device(struct amd_iommu *iommu, struct device *de= v) @@ -2477,49 +2464,75 @@ static void detach_device(struct device *dev) mutex_unlock(&dev_data->mutex); } =20 +static void iommu_init_device_caps(struct iommu_dev_data *dev_data, + struct device *dev, + struct amd_iommu *iommu) +{ + if (FEATURE_NUM_INT_REMAP_SUP_2K(amd_iommu_efr2)) + dev_data->max_irqs =3D MAX_IRQS_PER_TABLE_2K; + else + dev_data->max_irqs =3D MAX_IRQS_PER_TABLE_512; + + amd_iommu_set_pci_msi_domain(dev, iommu); + + if (!dev_is_pci(dev)) + return; + + /* + * By default we use passthrough mode for IOMMUv2 capable device. + * But if amd_iommu=3Dforce_isolation is set (e.g. to debug DMA to + * invalid address), we ignore the capability for the device so + * it'll be forced to go into translation mode. + */ + if ((iommu_default_passthrough() || !amd_iommu_force_isolation) && + amd_iommu_gt_ppr_supported()) { + dev_data->flags =3D pdev_get_caps(to_pci_dev(dev)); + } + + /* + * If IOMMU and device supports PASID then it will contain max + * supported PASIDs, else it will be zero. + */ + if (amd_iommu_pasid_supported() && + pdev_pasid_supported(dev_data)) { + dev_data->max_pasids =3D min_t(u32, iommu->iommu.max_pasids, + pci_max_pasids(to_pci_dev(dev))); + } + + pci_prepare_ats(to_pci_dev(dev), PAGE_SHIFT); +} + static struct iommu_device *amd_iommu_probe_device(struct device *dev) { struct iommu_device *iommu_dev; struct amd_iommu *iommu; struct iommu_dev_data *dev_data; int ret; + u16 devid; =20 - if (!check_device(dev)) - return ERR_PTR(-ENODEV); - - iommu =3D rlookup_amd_iommu(dev); - if (!iommu) - return ERR_PTR(-ENODEV); - - /* Not registered yet? */ - if (!iommu->iommu.ops) + if (!iommu_lookup_device(dev, &iommu, &devid)) return ERR_PTR(-ENODEV); =20 if (dev_iommu_priv_get(dev)) return &iommu->iommu; =20 - ret =3D iommu_init_device(iommu, dev); - if (ret) { + dev_data =3D iommu_init_device(iommu, dev, devid); + if (IS_ERR(dev_data)) { + ret =3D PTR_ERR(dev_data); dev_err(dev, "Failed to initialize - trying to proceed anyway\n"); iommu_dev =3D ERR_PTR(ret); iommu_ignore_device(iommu, dev); goto out_err; } =20 - amd_iommu_set_pci_msi_domain(dev, iommu); + iommu_init_device_caps(dev_data, dev, iommu); iommu_dev =3D &iommu->iommu; - + /* - * If IOMMU and device supports PASID then it will contain max - * supported PASIDs, else it will be zero. + * When DMA translation is unavailable return error so the iommu core + * won't attempt domain attach for this device. But interrupt-remap + * is still supported. Hence do not ignore the device. */ - dev_data =3D dev_iommu_priv_get(dev); - if (amd_iommu_pasid_supported() && dev_is_pci(dev) && - pdev_pasid_supported(dev_data)) { - dev_data->max_pasids =3D min_t(u32, iommu->iommu.max_pasids, - pci_max_pasids(to_pci_dev(dev))); - } - if (amd_iommu_pgtable =3D=3D PD_MODE_NONE) { pr_warn_once("%s: DMA translation not supported by iommu.\n", __func__); @@ -2527,16 +2540,6 @@ static struct iommu_device *amd_iommu_probe_device(s= truct device *dev) goto out_err; } =20 - iommu_completion_wait(iommu); - - if (FEATURE_NUM_INT_REMAP_SUP_2K(amd_iommu_efr2)) - dev_data->max_irqs =3D MAX_IRQS_PER_TABLE_2K; - else - dev_data->max_irqs =3D MAX_IRQS_PER_TABLE_512; - - if (dev_is_pci(dev)) - pci_prepare_ats(to_pci_dev(dev), PAGE_SHIFT); - out_err: return iommu_dev; } --=20 2.55.0.766.g2966f0265a-goog From nobody Mon Sep 28 08:46:16 2026 Received: from mail-pf1-f200.google.com (mail-pf1-f200.google.com [209.85.210.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4AE7416855 for ; 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Mon, 24 Aug 2026 05:23:59 -0700 (PDT) Date: Mon, 24 Aug 2026 12:23:44 +0000 In-Reply-To: <20260824122347.1588592-1-praan@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260824122347.1588592-1-praan@google.com> X-Mailer: git-send-email 2.55.0.766.g2966f0265a-goog Message-ID: <20260824122347.1588592-3-praan@google.com> Subject: [PATCH v3 2/5] iommu/amd: Fix DTE clearing and rename iommu_ignore_device() From: Pranjal Shrivastava To: iommu@lists.linux.dev, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Joerg Roedel , Suravee Suthikulpanit , Vasant Hegde , Ankit Soni , Jason Gunthorpe , Bjorn Helgaas , Samiullah Khawaja , Pranjal Shrivastava , sashiko-bot@kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The iommu_ignore_device() function currently uses memset() to manually clear the primary Device Table Entry (DTE), which risks torn writes as the hardware reads DTEs as atomic 256-bit qwords. Furthermore, clearing the primary devid in the lookup table before calling setup_aliases() causes rlookup_amd_iommu() to fail for aliases. This prevents clearing the DTEs for DMA aliases. Fix this by replacing the manual memset with a dedicated helper that invalidates the DTE by clearing the lower 128 bits (having the Valid bit) first, followed by the upper 128 bits. The cleared state is then explicitly cloned to all aliases before the lookup tables are nullified. Rename the function to iommu_disable_device() more accurately reflects its intent, as we still support IRQ remapping for these devices) Fixes: 99fc4ac3d297 ("iommu/amd: Introduce per PCI segment alias_table") Reported-by: sashiko-bot@kernel.org Closes: https://lore.kernel.org/all/20260529153216.2AD1E1F00899@smtp.kernel= .org/ Suggested-by: Jason Gunthorpe Signed-off-by: Pranjal Shrivastava Reviewed-by: Samiullah Khawaja Reviewed-by: Vasant Hegde --- drivers/iommu/amd/iommu.c | 53 ++++++++++++++++++++++++++------------- 1 file changed, 36 insertions(+), 17 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index e1f9fbb63837..8e382317709d 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -728,22 +728,6 @@ static struct iommu_dev_data *iommu_init_device(struct= amd_iommu *iommu, return dev_data; } =20 -static void iommu_ignore_device(struct amd_iommu *iommu, struct device *de= v) -{ - struct amd_iommu_pci_seg *pci_seg =3D iommu->pci_seg; - struct dev_table_entry *dev_table =3D get_dev_table(iommu); - int devid, sbdf; - - sbdf =3D get_device_sbdf_id(dev); - if (sbdf < 0) - return; - - devid =3D PCI_SBDF_TO_DEVID(sbdf); - pci_seg->rlookup_table[devid] =3D NULL; - memset(&dev_table[devid], 0, sizeof(struct dev_table_entry)); - - setup_aliases(iommu, dev); -} =20 =20 /*************************************************************************= *** @@ -2233,6 +2217,41 @@ static void dev_update_dte(struct iommu_dev_data *de= v_data, bool set) clear_dte_entry(iommu, dev_data); } =20 +/* + * Invalidate a DTE by clearing the Valid bit first. + * Note: Lockless; Not to be used on a fully probed + * device with live dev_data. + */ +static void amd_iommu_disable_dte(struct dev_table_entry *ptr) +{ + struct dev_table_entry new =3D {}; + + write_dte_lower128(ptr, &new); + write_dte_upper128(ptr, &new); +} + +static void iommu_disable_device(struct amd_iommu *iommu, struct device *d= ev) +{ + struct amd_iommu_pci_seg *pci_seg =3D iommu->pci_seg; + struct dev_table_entry *dev_table =3D get_dev_table(iommu); + int devid, sbdf; + + sbdf =3D get_device_sbdf_id(dev); + if (sbdf < 0) + return; + + devid =3D PCI_SBDF_TO_DEVID(sbdf); + + /* Clear the primary DTE */ + amd_iommu_disable_dte(&dev_table[devid]); + + /* Clone the cleared DTE to all aliases before wiping the rlookup */ + if (dev_iommu_priv_get(dev)) + clone_aliases(iommu, dev); + + pci_seg->rlookup_table[devid] =3D NULL; +} + /* * If domain is SVA capable then initialize GCR3 table. Also if domain is * in v2 page table mode then update GCR3[0]. @@ -2521,7 +2540,7 @@ static struct iommu_device *amd_iommu_probe_device(st= ruct device *dev) ret =3D PTR_ERR(dev_data); dev_err(dev, "Failed to initialize - trying to proceed anyway\n"); iommu_dev =3D ERR_PTR(ret); - iommu_ignore_device(iommu, dev); + iommu_disable_device(iommu, dev); goto out_err; } =20 --=20 2.55.0.766.g2966f0265a-goog From nobody Mon Sep 28 08:46:16 2026 Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E952E416873 for ; Mon, 24 Aug 2026 12:24:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787574244; cv=none; b=m48E+mD1ynomHpBokdQNEYcEgjl30HWK8OlyYmhKl1YDRkcBnX4P7wzpugOTcYfgs/SKPMRcC/EDwnmgAjx8lmcEl8HbafqmGwRB4tB3ygKJrtpv+fPWGHYEs0tNIgG5JT3Khbn0RQr8l0KWCFZ2sx1Qr4WGaCh//XF42gVDUyg= ARC-Message-Signature: i=1; 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charset="utf-8" Split the amd_iommu_probe_device() error paths into err_deinit and out_err. Proper init failures continue to call iommu_disable_device_dma() while configuration failures (like PD_MODE_NONE or ATS mismatches) skip it to preserve the rlookup_table entry required for IRQ remapping. Reviewed-by: Vasant Hegde Reported-by: sashiko-bot@kernel.org Closes: https://lore.kernel.org/all/20260529153216.2AD1E1F00899@smtp.kernel= .org/ Suggested-by: Ankit Soni Signed-off-by: Pranjal Shrivastava --- drivers/iommu/amd/iommu.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 8e382317709d..ed336bca1a2e 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2540,8 +2540,7 @@ static struct iommu_device *amd_iommu_probe_device(st= ruct device *dev) ret =3D PTR_ERR(dev_data); dev_err(dev, "Failed to initialize - trying to proceed anyway\n"); iommu_dev =3D ERR_PTR(ret); - iommu_disable_device(iommu, dev); - goto out_err; + goto err_deinit; } =20 iommu_init_device_caps(dev_data, dev, iommu); @@ -2559,6 +2558,10 @@ static struct iommu_device *amd_iommu_probe_device(s= truct device *dev) goto out_err; } =20 + return iommu_dev; + +err_deinit: + iommu_disable_device(iommu, dev); out_err: return iommu_dev; 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charset="utf-8" Update the driver to call pci_prepare_ats() after checking if pci_ats_supported() and fail the probe_device if pci_prepare_ats() returns an error. Additionally, update pdev_enable_cap_ats() to WARN_ON() a failure in pci_enable_ats(). Reviewed-by: Vasant Hegde Signed-off-by: Pranjal Shrivastava Reviewed-by: Jason Gunthorpe Reviewed-by: Samiullah Khawaja --- drivers/iommu/amd/iommu.c | 40 +++++++++++++++++++++++++++++---------- 1 file changed, 30 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index ed336bca1a2e..ecee4d097e4e 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -573,10 +573,17 @@ static inline int pdev_enable_cap_ats(struct pci_dev = *pdev) if (amd_iommu_iotlb_sup && (dev_data->flags & AMD_IOMMU_DEVICE_FLAG_ATS_SUP)) { ret =3D pci_enable_ats(pdev, PAGE_SHIFT); - if (!ret) { - dev_data->ats_enabled =3D 1; - dev_data->ats_qdep =3D pci_ats_queue_depth(pdev); - } + + /* + * pci_enable_ats() should not fail here because earlier + * checks have already verified support & config. + */ + if (WARN_ON(ret)) + return ret; + + dev_data->ats_enabled =3D 1; + dev_data->ats_qdep =3D pci_ats_queue_depth(pdev); + ret =3D 0; } =20 return ret; @@ -2483,10 +2490,12 @@ static void detach_device(struct device *dev) mutex_unlock(&dev_data->mutex); } =20 -static void iommu_init_device_caps(struct iommu_dev_data *dev_data, - struct device *dev, - struct amd_iommu *iommu) +static int iommu_init_device_caps(struct iommu_dev_data *dev_data, + struct device *dev, + struct amd_iommu *iommu) { + int ret; + if (FEATURE_NUM_INT_REMAP_SUP_2K(amd_iommu_efr2)) dev_data->max_irqs =3D MAX_IRQS_PER_TABLE_2K; else @@ -2495,7 +2504,7 @@ static void iommu_init_device_caps(struct iommu_dev_d= ata *dev_data, amd_iommu_set_pci_msi_domain(dev, iommu); =20 if (!dev_is_pci(dev)) - return; + return 0; =20 /* * By default we use passthrough mode for IOMMUv2 capable device. @@ -2518,7 +2527,13 @@ static void iommu_init_device_caps(struct iommu_dev_= data *dev_data, pci_max_pasids(to_pci_dev(dev))); } =20 - pci_prepare_ats(to_pci_dev(dev), PAGE_SHIFT); + if (pci_ats_supported(to_pci_dev(dev))) { + ret =3D pci_prepare_ats(to_pci_dev(dev), PAGE_SHIFT); + if (ret) + return ret; + } + + return 0; } =20 static struct iommu_device *amd_iommu_probe_device(struct device *dev) @@ -2543,7 +2558,12 @@ static struct iommu_device *amd_iommu_probe_device(s= truct device *dev) goto err_deinit; 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charset="utf-8" Currently, pci_prepare_ats() internally calls pci_ats_supported() and returns -EINVAL if the device does not support ATS. While this provides a silent safety check, it conflates support detection with configuration. Update pci_prepare_ats() to wrap the internal pci_ats_supported check in a WARN_ON(). This mandates all callers to call pci_prepare_ats() only if the function supports ATS. Update the function documentation to mention that callers must verify ATS support (via pci_ats_supported()) before calling pci_prepare_ats(). Reviewed-by: Vasant Hegde Suggested-by: Baolu Lu Reviewed-by: Nicolin Chen Signed-off-by: Pranjal Shrivastava Reviewed-by: Jason Gunthorpe --- drivers/pci/ats.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c index 96efa00d9743..f18c06b73eb2 100644 --- a/drivers/pci/ats.c +++ b/drivers/pci/ats.c @@ -53,7 +53,9 @@ EXPORT_SYMBOL_GPL(pci_ats_supported); * @ps: the IOMMU page shift * * This must be done by the IOMMU driver on the PF before any VFs are crea= ted to - * ensure that the VF can have ATS enabled. + * ensure that the VF can have ATS enabled. Callers must verify that ATS is + * supported by the device (e.g. via pci_ats_supported()) before calling t= his + * function. * * Returns 0 on success, or negative on failure. */ @@ -61,7 +63,7 @@ int pci_prepare_ats(struct pci_dev *dev, int ps) { u16 ctrl; =20 - if (!pci_ats_supported(dev)) + if (WARN_ON(!pci_ats_supported(dev))) return -EINVAL; =20 if (WARN_ON(dev->ats_enabled)) --=20 2.55.0.766.g2966f0265a-goog