From nobody Mon Sep 28 10:01:08 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE724342C80; Mon, 24 Aug 2026 06:15:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787552111; cv=none; b=hBfaTIDis1I2p6hxAUR5J/Gl+sUTdEhz0hFdlZJZInq0A7crWbjnKrtN6VvSy8rgtr7hLtr0oHImrqC9kPzUn1t6GXwgBAFBVU/0/F9Me2b6gC81q+tJ/jDK9Q5Y3dkVZOyLm/ujmhx3GwpLWlMBEuoJshZvp7k9R7GQvQqVwgU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787552111; c=relaxed/simple; bh=xoVFtZfwFUn8ctUKrgx5JLL2pQj2N3ofLqH+aau927U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=b0D/F1Xrp23gdgK6KE14lL5JZbRhF4aEjsjkYskmuTAfhkhu7aR2YZ88MSSxZBhZ7eZf2jxM8OAe10GsC5N5Soh8b9+73f4MnFgwnShg8Z5Rgp4JL/mEDOO1BJA1/p/M5GmaIXbHBiTXUjvNaBfe2bigc0d7bZAQIJSHjG3EH9I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=USbvkkCB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="USbvkkCB" Received: by smtp.kernel.org (Postfix) with ESMTPS id 825D3C19425; Mon, 24 Aug 2026 06:15:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787552110; bh=xoVFtZfwFUn8ctUKrgx5JLL2pQj2N3ofLqH+aau927U=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=USbvkkCBJQiP6h9hCXLE24Hm0lzbj/M90JFx4RYxJ+oRhBsAinbYtALBuLtytfCqR 6pDIVJd3ETdyND+bOdgNsLfWPEd4nMErxBFTrFKZpRqSCIsOUUxbyJ4ONiKk/Go5qw 9bRlADfd+Mi9eGTyng7aHvRUwJaT1rcYXXYv2I0iUzbQzcI75X76+yP+yrfX0kuFNp ElFvZNIxksDjxWsUERNR5AjRMggUNIQFZ5BFFXmJdDfDhddUzFvMVZcyptxMgz0eut wUxITfLuE2SsaQbezaRWwSofYaHihEWmmmPuw+hBba++UKzCbB8HKVO/OPpDIi3686 2QPkX/KR1vMig== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FDF2C5DF8C; Mon, 24 Aug 2026 06:15:10 +0000 (UTC) From: Jia Wang via B4 Relay Date: Mon, 24 Aug 2026 13:54:14 +0800 Subject: [PATCH 01/12] dt-bindings: riscv: cpus: Fix yamllint style issues Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260824-ultrarisc-dts-v1-1-61ab7aebe9e5@ultrarisc.com> References: <20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com> In-Reply-To: <20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Mark Brown , Andi Shyti , Mika Westerberg , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Eugeniy Paltsev , Vinod Koul , Frank Li Cc: Paul Walmsley , Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org, netdev@vger.kernel.org, dmaengine@vger.kernel.org, Jia Wang X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787552108; l=1425; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=Q697DFC7ysJh9zCppPk9O+0gvj0yAIUmzUczo/IHMyc=; b=or1xxNfTcnovPzCMzApsOwWbacOhxI/q+gccq7qhyvzRWq2X2lx0MS3b8g6Wxi5KIU0117ZLQ IUn00ulNlwjCPLJm5EosC9d3iWABnhGYcGZ3B6wMnXld66Os6azzRvh X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Wrap an overlong description line and normalize the inline dependency lists to satisfy yamllint. Signed-off-by: Jia Wang Acked-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/cpus.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index 5feeb2203050..0da219ae6769 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -117,8 +117,8 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: VLEN/8, the vector register length in bytes. This property is requir= ed on - thead systems where the vector register length is not identical on a= ll harts, or - the vlenb CSR is not available. + thead systems where the vector register length is not identical on a= ll + harts, or the vlenb CSR is not available. =20 # RISC-V has multiple properties for cache op block sizes as the sizes # differ between individual CBO extensions @@ -151,8 +151,8 @@ anyOf: - riscv,isa-base =20 dependencies: - riscv,isa-base: [ "riscv,isa-extensions" ] - riscv,isa-extensions: [ "riscv,isa-base" ] + riscv,isa-base: ["riscv,isa-extensions"] + riscv,isa-extensions: ["riscv,isa-base"] =20 required: - interrupt-controller --=20 2.34.1 From nobody Mon Sep 28 10:01:08 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0BE035B63F; Mon, 24 Aug 2026 06:15:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787552111; cv=none; b=W62j4VeTunPny1DMEcvHm8h/OoXMPngasnQOeJ2k53hDCHvZEIHH0SDKYwkUMh7fuVZD5qDhyNOziMdn6OVYFu6uL7pntmvdd0XciacdYUHv2k/y8iC4HcO3QxVS7GowKFk+0qMgW66MjAnOHxJSbk9TUjOVxxLm3JycQP3LMqg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787552111; c=relaxed/simple; bh=IAB+qgR/3nvdk58Ob6r3FrRddQ0G9TiV3W0KIKIcK0M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=m5htgp+Pb96yZd+nb0ENjTjgUwkWivwLiq7NMLG/QOeokODROMq3fk5gxPArs9w76aCUxwAA9Z2EMzlhc8m4+n11SZUwb81ngKlLnAxQjYhXn4y4M4+7oSFNOeaKI6/uoaaPrEd5GcwMijUqZm/kx6C6GW+swrjp6I2TTkNwItg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kvNOzaWa; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kvNOzaWa" Received: by smtp.kernel.org (Postfix) with ESMTPS id 94F76C2BCF7; Mon, 24 Aug 2026 06:15:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787552110; bh=IAB+qgR/3nvdk58Ob6r3FrRddQ0G9TiV3W0KIKIcK0M=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=kvNOzaWaHz/jcqz2+cI8BkHG5bMu7vy/Kc3XSdYnNsW66PMNumu3HR9t+mEZC46a1 j109HCX4xsJDxXoY/SE1t0B1/44nhEoBzLzUoOuwErM7rfxDlSR+42qoTpkpZL8/fm 1rXiQ2itWBy+QZ30KWT2Kh40TYI/CMO6kUdVoVnMX0j0q89Onucjc73m9lzUxuMTqB q6dFyRM//cHZ0wvRMfPqxhQ0D6mtKv7d6qzHr0f8fMs5I1gzmb17DEN9/w4m9kefmw dKipjW8ne8y4mnRRATNnzrnEy38FMAz9J9bd4N5xGbFWdu8cJWTWTiOos99Hpb9FNx J6DwJ8zb+EEow== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71FBDC5DF94; Mon, 24 Aug 2026 06:15:10 +0000 (UTC) From: Jia Wang via B4 Relay Date: Mon, 24 Aug 2026 13:54:15 +0800 Subject: [PATCH 02/12] dt-bindings: vendor-prefixes: Add shenrongda Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260824-ultrarisc-dts-v1-2-61ab7aebe9e5@ultrarisc.com> References: <20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com> In-Reply-To: <20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Mark Brown , Andi Shyti , Mika Westerberg , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Eugeniy Paltsev , Vinod Koul , Frank Li Cc: Paul Walmsley , Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org, netdev@vger.kernel.org, dmaengine@vger.kernel.org, Jia Wang X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787552108; l=834; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=srZhMWhIRRAzwGwjdYH2TAvocE2gftBCjE4OIfGUdvU=; b=yRRRYkak7O2YkqfP2DQXp3U8p6gybdlntCgpJlpicK/56orMNBs7mNrmemPaOXLPCAcnIhVjp UNZn8Ji8hSjCCwR3u/OEljzLw0WqpXmVLjP+vivIkpOHW7ngnDH0A0x X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Add Shenzhen Rongda Computer Co., Ltd. to the vendor prefixes. Link: http://www.shenrongda.com/ Signed-off-by: Jia Wang Acked-by: Conor Dooley --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 6780b651acf8..61cd5e625a23 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1505,6 +1505,8 @@ patternProperties: description: SGX Sensortech "^sharp,.*": description: Sharp Corporation + "^shenrongda,.*": + description: Shenzhen Rongda Computer Co., Ltd. "^shift,.*": description: SHIFT GmbH "^shimafuji,.*": --=20 2.34.1 From nobody Mon Sep 28 10:01:08 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2ACE33E2ADD; Mon, 24 Aug 2026 06:15:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787552111; cv=none; b=JNBLLIHmWs4yhpLZ+SHOpP66hyTk8N5r1Y0bk4JOZqu7C4zSK8m0KBg7lIiWAuHg36i7efZsQOvIjlH+iaPM1vra3c47uscGQ/5DsXucnB4AAzpn4epjVvmaKaUxaA3t0Urn0RMy/mC0yjC2ZxXqwqVl904CNlXEb1NhYqJANFk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787552111; c=relaxed/simple; bh=FLy/qTiAhZfI9GhBeq9b7ybYoYqfoqJ7jxv71DLMssA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fXqzx68fuwhargp8vBjriHrls4ZXnBsDNEsTesRlAC6vU4nIlPXhRAQSNDIQCbZ53PyGkDnYKl9SrpAoTxJNFdx6829ss/yHLLGBMqdXiQuItVlbBkgxJ+Jm6Bny8UXMn9qxDEmchztvHzFq6lNsBcbATfOfvmUKaT54MG8yRpg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ha8qadys; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ha8qadys" Received: by smtp.kernel.org (Postfix) with ESMTPS id A3ABBC2BCFC; Mon, 24 Aug 2026 06:15:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787552110; bh=FLy/qTiAhZfI9GhBeq9b7ybYoYqfoqJ7jxv71DLMssA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ha8qadyspFFt1+vg60wdpR2RzJRfnGtLgnVzRSi4nVzTeIDjo2CmzDuMPcu7ySuPU C4e8yUpjRaW1Z21EP/yz5UjXdl6r7SSieOLY3k4rPDMNhdy7Y7nDpNFu4z+mO8IrQd f6Eo5UvIcpA/j7KRdpULAL3MsFYjPREpk2z66xPrluSmqzgntChhGDTcO+A3Gk3lmi Dr473nab85w3GkgAAZXv+93R0MBu6QIXLNVCVcYz3+Z4+4+ZcFpvTFrZVGJ2JDWsFw dYKZ+cMMF2/kx1DAgKJUOW0nvI2VK7sCfdg1JpYyh23QNKcmoaTglZX/bI+dUe1Wgy ft2UAY+4BCLJA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83BAAC5DF9D; Mon, 24 Aug 2026 06:15:10 +0000 (UTC) From: Jia Wang via B4 Relay Date: Mon, 24 Aug 2026 13:54:16 +0800 Subject: [PATCH 03/12] dt-bindings: riscv: cpus: Add UltraRISC CP100 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260824-ultrarisc-dts-v1-3-61ab7aebe9e5@ultrarisc.com> References: <20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com> In-Reply-To: <20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Mark Brown , Andi Shyti , Mika Westerberg , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Eugeniy Paltsev , Vinod Koul , Frank Li Cc: Paul Walmsley , Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org, netdev@vger.kernel.org, dmaengine@vger.kernel.org, Jia Wang X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787552108; l=751; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=PLH98AWMWhEDDtI7P4MBr8Ej9OKDTOxH4/kye1KfXcs=; b=uI8E83sWqzeJyxFJjF1Pxn9pu9ZOR1cxxf/juShwZi19Ep8HUOnUHoh4zL5GQxA//IsERyKUI 5ouqlO5rBXJBs9s/7mvkSQQFDH828iwCjF1SObjLasgHWv9mbMWyAhT X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Document the UltraRISC CP100 CPU compatible. The CP100 CPU is used in the UltraRISC DP1000 SoC. Signed-off-by: Jia Wang Acked-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index 0da219ae6769..85adf72899c9 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -67,6 +67,7 @@ properties: - thead,c908 - thead,c910 - thead,c920 + - ultrarisc,cp100 - const: riscv - items: - enum: --=20 2.34.1 From nobody Mon Sep 28 10:01:08 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 348CD3E3141; Mon, 24 Aug 2026 06:15:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787552111; cv=none; b=bHtQ1YTkw4bg/kx6CQNn65iDUfhfq7SjqLQY3tKOBicnWUCFuULVcUj1mjKdE6HiOHNaKnZq4b21r+sK5/idZdKXgsjUmDNw9AAslussjYw3KrJbBNTBXUN41xDuN6zayF8TvicheRS1NV6h/ZFnbFfYx7+lKDs/+wqOAcAirmo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787552111; c=relaxed/simple; bh=6glAL5dZPzWwvgIDi8+jSp/LCyYm+4YRxj09bMO/+2s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mIrRUVooytT6P0e3kRZhnZMJdxo9q9L4nhp3B93GVIpijfA3r9HJo173kvNUuYeIycu3lRc5CZrvYuOaSdPxPiYLi48rwQ8JoQdVGHYHVfnK2CwApHszh4xfAHSdgNus8nsRRkxr2z5Iz4kWEUeox6SRelzbs2C4q52Fxq35TUw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kktz2nYW; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kktz2nYW" Received: by smtp.kernel.org (Postfix) with ESMTPS id B5291C4AF0C; Mon, 24 Aug 2026 06:15:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787552110; bh=6glAL5dZPzWwvgIDi8+jSp/LCyYm+4YRxj09bMO/+2s=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=kktz2nYWbchpJ5dayseLdUAbLkYifh4aLmm4XVdcz4SQ/xyoXTCrqtq+bt244RHxi LJ7+BIBZE3jFG63E6Zg1C1oCqHQGf4bMA5EZE3ZYnRQKvSOhtcfRWMFk8pXhKfCROJ zJ1+mICrTkF4YOiCmNRakIyKs50/Ct/CFnHoJRHLF2zJ+eJIhdhWAmdA4ojJBkTukb vCx4NcbvHtnmR/JfHqjpa9KqDwUpIrS+A+rJXfKF1o/2ToEtpqETeeCxOS/drm0lpv pZu5xOS9cpbcRjf4+Vx4uu3gLml05klQyIvE/Np1GqVKr+zQA0vSuSP2Y8nA67lC6v yXORrm+1QPwYw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 966AAC61CE2; Mon, 24 Aug 2026 06:15:10 +0000 (UTC) From: Jia Wang via B4 Relay Date: Mon, 24 Aug 2026 13:54:17 +0800 Subject: [PATCH 04/12] dt-bindings: riscv: Add UltraRISC DP1000 board compatibles Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260824-ultrarisc-dts-v1-4-61ab7aebe9e5@ultrarisc.com> References: <20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com> In-Reply-To: <20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Mark Brown , Andi Shyti , Mika Westerberg , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Eugeniy Paltsev , Vinod Koul , Frank Li Cc: Paul Walmsley , Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org, netdev@vger.kernel.org, dmaengine@vger.kernel.org, Jia Wang X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787552108; l=1889; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=jWGrB8tM0PP2gL1fI25fr83ev1OyLQF1owAoac3KkAQ=; b=cdcJDw9lL1t8IDmHih5fCmmE70vfJtaDXXOK08WjpNEW9O87tb4HrKCtfydFxfkAexrQq/5cq 4l7r4wP6FxGCzJUXXUQU8Ym5hHg4rskpSsKGf6JVBpIwDOAz6SPK0Lu X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Document the compatibles for the Shenzhen Rongda M0 and Milk-V Titan boards, both based on the UltraRISC DP1000 SoC. Signed-off-by: Jia Wang Acked-by: Conor Dooley --- .../devicetree/bindings/riscv/ultrarisc.yaml | 27 ++++++++++++++++++= ++++ MAINTAINERS | 7 ++++++ 2 files changed, 34 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/ultrarisc.yaml b/Docum= entation/devicetree/bindings/riscv/ultrarisc.yaml new file mode 100644 index 000000000000..a51e63dbeca3 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/ultrarisc.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/ultrarisc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UltraRISC SoC-based boards + +maintainers: + - Jia Wang + +description: + UltraRISC DP1000 SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - shenrongda,m0 + - milkv,titan + - const: ultrarisc,dp1000 + +additionalProperties: true +... diff --git a/MAINTAINERS b/MAINTAINERS index d77dca044075..1148168e8f8e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23517,6 +23517,13 @@ F: include/dt-bindings/power/thead,th1520-power.h F: include/dt-bindings/reset/thead,th1520-reset.h F: include/linux/firmware/thead/thead,th1520-aon.h =20 +RISC-V ULTRARISC SoC SUPPORT +M: Jia Wang +L: linux-riscv@lists.infradead.org +S: Supported +T: git https://github.com/ultrarisc/linux.git +F: Documentation/devicetree/bindings/riscv/ultrarisc.yaml + RNBD BLOCK DRIVERS M: Md. Haris Iqbal M: Jack Wang --=20 2.34.1 From nobody Mon Sep 28 10:01:08 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A3E33E4504; Mon, 24 Aug 2026 06:15:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787552111; cv=none; b=fbUuYQxkroT9OlCpMGtqEV72xUKIvQhj8mx86BXcLm/ySPBW+yywTuiH9wL1A9FdcNOkr0oj0mugCkdw4vxkqQ+uo7Y8icEZjrAE1vKWXJjo1xZtDtX61ebVct7hN/nPmYo9qIa9zAVOPvWa/HcluwBtHlprErBJP9xbnqaF+68= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787552111; c=relaxed/simple; bh=CA2OaRx3uR5mae8p3mSwvWAfzEXykGeM7OaNdNFvjd4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ss539WuvOiuq0g9TpfOnaSpN1jWUVqaB8DVuSxYbh9RoJNs42lo8kMBLujg13PGrMe7Qh0TvAPQYhGJCaP51Cpx7m+SmE/A1adImkrliwu8ah+QCB3Q3oOQCeLlMrQuCJJKYtQJ9xk2XOagQby4Bv5RJNGuu2bDX15DnI3dAbfY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=h3G7eFwv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="h3G7eFwv" Received: by smtp.kernel.org (Postfix) with ESMTPS id E3C1CC4DDE5; Mon, 24 Aug 2026 06:15:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787552111; bh=CA2OaRx3uR5mae8p3mSwvWAfzEXykGeM7OaNdNFvjd4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=h3G7eFwvnb88wCXJMM7ttmKtWe70jNxYy8oOfDf7mw61ucSGdrIorxheFJQ2oKHuO +HuCTyJp6hniNMsz0dhiTBYMSgntozipYSTCWgCTTumcayReCRSeXAD6xZno87LRw/ L5VO8h2Vm79qq/t0faw5QjTgYyg3moktJlT7pF3kIPxNOldGQ+uR1wCaLjhtZeUk+T uwRLZTgOC0JcB7gMb0u0FopchEYuGOzIRWJTF0joD+8tMp9kFSIhGqIG31ofpbv1N7 FIHcMTU9ZuDIMsuWgbJAGkFGLbcJA3Qp09j+DJ7YeuevHR8WVYMqoOPU3qJhzbKPoT 2NTkiWpN/sfvg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB70DC5DF94; Mon, 24 Aug 2026 06:15:10 +0000 (UTC) From: Jia Wang via B4 Relay Date: Mon, 24 Aug 2026 13:54:18 +0800 Subject: [PATCH 05/12] dt-bindings: timer: Add UltraRISC DP1000 CLINT Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260824-ultrarisc-dts-v1-5-61ab7aebe9e5@ultrarisc.com> References: <20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com> In-Reply-To: <20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Mark Brown , Andi Shyti , Mika Westerberg , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Eugeniy Paltsev , Vinod Koul , Frank Li Cc: Paul Walmsley , Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org, netdev@vger.kernel.org, dmaengine@vger.kernel.org, Jia Wang X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787552108; l=911; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=L6jb4KXmGtvLsiicue+aqeQTQKu1hh49A3gJ3oqy6b4=; b=3VBgJyPcA6mmVBNWMcGIJ+1YMjutXZgCOfb4mFq+iDAvnYVGogpkSCmug1mhP9Sy9rifmwVGF wxCcGnbx7b+AMYHNcZfsWQjadMtbfgTg8AsrfwRJhtsVznGo49CzLMX X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Add compatible string for UltraRISC DP1000 CLINT. Signed-off-by: Jia Wang Acked-by: Conor Dooley --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Do= cumentation/devicetree/bindings/timer/sifive,clint.yaml index 3673836e14de..878f267d089b 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -40,6 +40,7 @@ properties: - starfive,jh8100-clint # StarFive JH8100 - starfive,jhb100-clint # StarFive JHB100 - tenstorrent,blackhole-clint # Tenstorrent Blackhole + - ultrarisc,dp1000-clint # UltraRISC DP1000 - const: sifive,clint0 # SiFive CLINT v0 IP block - items: - {} --=20 2.34.1 From nobody Mon Sep 28 10:01:08 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6927D3E44F0; Mon, 24 Aug 2026 06:15:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787552111; cv=none; b=qX12SwYsgd5JIHA/4KFNYdruNCghN3zHP1VkqJvoUMnMdboqLFtDZt8DdD2qnhorpjDoJy1iTwxfau+CtXj2CZ3RTCc1Y5DXQeoPRnf1cbIugiXd9n9KvgrS39ZQh9ZZdSoRYqHLOofEWDba0RV3l7zs7qNLa73kFVcFvZtwuI0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787552111; c=relaxed/simple; bh=5o3UdQ7NCWjfB/6BDLBC4HF2grF/7kX8adeAbxwnDkc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lTmLERG9FJoclzNtiMxgqWsnDQRQ9D9zy1WBcwDC9+XGC4xUU8CQXbH5iOB9m0U3EUE7Lv+JpOwk9SH/6yZo5MQcI9+c/xZWi571lQ+X+WLCXQZ7WyTVWE7nggY9KOWYZEN9w4uvAe2ZwfZo/HoIX5WXPQppUnwA/9tbx8FOL6Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=uZ7pWI8m; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uZ7pWI8m" Received: by smtp.kernel.org (Postfix) with ESMTPS id 01488C2BCFD; Mon, 24 Aug 2026 06:15:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787552111; bh=5o3UdQ7NCWjfB/6BDLBC4HF2grF/7kX8adeAbxwnDkc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=uZ7pWI8mLyk1JaJKanZk/INrlBvWP5BP4K0bLjq8VlbbezoLNX4UaCPGQv+5BRsjl Ze8dCT2/ftnpDqGMsvmiLKFYC8kbFIsPORQAB0xItlYIYJoqLfJ9PKsu7L3vNDqEzX 92Yen/64FrzhFwn4nQoTi6mRsOpsNfnf/6IzJWpyPHuX6WLQp2Pn+VNpAIWtaFVwZ9 LKq6MRMFExZWlTwxQv6GAl8pDX3lHfWRMq6whsVdpfCy6HYX1ohDvQHVF8gutxnOzJ rH9mvxr0lMn+SD728oWVEU8HiE8X3pc75MkP13lA/Q9Coi2eRt3gt0qqiKjFsafYPH MSHHIkvRlRS0A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE768C5DF81; Mon, 24 Aug 2026 06:15:10 +0000 (UTC) From: Jia Wang via B4 Relay Date: Mon, 24 Aug 2026 13:54:19 +0800 Subject: [PATCH 06/12] spi: dt-bindings: snps,dw-apb-ssi: Add compatible for UltraRISC DP1000 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260824-ultrarisc-dts-v1-6-61ab7aebe9e5@ultrarisc.com> References: <20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com> In-Reply-To: <20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Mark Brown , Andi Shyti , Mika Westerberg , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Eugeniy Paltsev , Vinod Koul , Frank Li Cc: Paul Walmsley , Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org, netdev@vger.kernel.org, dmaengine@vger.kernel.org, Jia Wang X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787552108; l=893; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=GOAvwSU+bClZtaYEoEYBIUWP7wk56GD6+csu9urD+2Q=; b=KOhSwVprVsR8XwUee2hGHuJ8P2eGS+xmvgFGjizmPpdfUWjvSB0byKgVtUM4XmMAaS+/De/RC sH207vJ1wA5DiQzv7OOIexIT25aDwh0wp7thQjFVDbySqHWWN9WSrTI X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Add the SoC-specific compatible string and use the generic one as fallback for the UltraRISC DP1000 SPI controller. Signed-off-by: Jia Wang Acked-by: Conor Dooley --- Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/D= ocumentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index 1e70c6804d5d..896205329d7e 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -63,6 +63,7 @@ properties: - mscc,jaguar2-spi - sophgo,sg2042-spi - thead,th1520-spi + - ultrarisc,dp1000-spi - const: snps,dw-apb-ssi - description: Vendor controllers compatible with v1.01a items: --=20 2.34.1 From nobody Mon Sep 28 10:01:08 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C6FC3E4514; Mon, 24 Aug 2026 06:15:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787552111; cv=none; b=PgRYdzIfaoMO1TBz2iD1moj/f6cWjtdYE8PjZ2p54VjTd6YzLbtPmJ89GwA/YU6mXW+xh/fhT62BRYUdDCFgz33w1vsujc3yZ6olbWeTjnkXUSiQL/AGWh/H/6Pamz/MGiBHX2/muBpLPWP/0/EtLQZBlzpKzCZpjIZ4sQ34gk4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787552111; c=relaxed/simple; bh=/tORglKOn/6hGNCzOPRziWVwHttzvbuXlVQzocvD4VY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=e+qyDA54p92IHPb1JNHEDF+EP/UYFxjXRxlQyJrePaevhj3Hg2m4K92YSYqkhZTEugr1Kmw7GjGRat0W4dl8gShran6hcVoUXrFmaF3wHY9477es3vGIpdmkm7ItzwBjdn9ph8Nv6dx21VzDQaNk+Nh8CVbUOzk3nMbcW81puck= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=so7BWFEm; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="so7BWFEm" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1496FC32782; Mon, 24 Aug 2026 06:15:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787552111; bh=/tORglKOn/6hGNCzOPRziWVwHttzvbuXlVQzocvD4VY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=so7BWFEmHR5F2wte9vg5VuHjetEVyy9NRI/bG6xxy9dOG6Bfy7KOlyNy6lO1pHU0+ +ZUSG92wSBwa+SUjgxmsgA8Q79S0LXUFF3RxWLcNOUtGovIhRO13YoXTnCwQEmVUCp R/LpDLvJW47shUxxYtcV8YnhgcpLYfV5c14LQlUH96Bx5ZmSzPHpOwyP0EQoINu/1k RpImfsYR7y5kdQt/4D2WSw50DVoclsaYycpLf2JU0KJfpsNEW9KNgXVV8yKB0/2sa0 PaUBmDAgpM4CTT9Na5dZj4B34zq4A7hvI7zP0RhNyBIdeaIdAT68tDovfkdQmjEsns M49TGLyC8/Pkg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1B8FC5DF9D; Mon, 24 Aug 2026 06:15:10 +0000 (UTC) From: Jia Wang via B4 Relay Date: Mon, 24 Aug 2026 13:54:20 +0800 Subject: [PATCH 07/12] dt-bindings: i2c: dw: Add compatible for UltraRISC DP1000 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260824-ultrarisc-dts-v1-7-61ab7aebe9e5@ultrarisc.com> References: <20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com> In-Reply-To: <20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Mark Brown , Andi Shyti , Mika Westerberg , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Eugeniy Paltsev , Vinod Koul , Frank Li Cc: Paul Walmsley , Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org, netdev@vger.kernel.org, dmaengine@vger.kernel.org, Jia Wang X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787552108; l=846; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=a3FLG1v/opm8P6Mx7tFBUWeLRZtmVFCN4Uxnx7ELy+8=; b=FZb78z8T9rITx8H9711DLMJwoTpitGFde0UxVr48CTWjgXqPmZIps0nVG5x8Ive0NSxtUTIag x3P+jfsIl4CDCgsd45dmaaxozFkO1pbWp2oQT4QQIDnp4SGSBiQMxvT X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Add the SoC-specific compatible string and use the generic one as fallback for the UltraRISC DP1000 I2C controller. Signed-off-by: Jia Wang Acked-by: Conor Dooley --- Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml= b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml index 467bdcbb8538..eee21ca8d7ed 100644 --- a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml @@ -44,6 +44,7 @@ properties: - mscc,ocelot-i2c - sophgo,sg2044-i2c - thead,th1520-i2c + - ultrarisc,dp1000-i2c - const: snps,designware-i2c =20 reg: --=20 2.34.1 From nobody Mon Sep 28 10:01:08 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AD923E44E0; Mon, 24 Aug 2026 06:15:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787552111; cv=none; b=DZk4tf8eVWBXbHzLj4/4EYUdv3+glC7p9Gc9gQbseD9k/H4Tpf/DaejY8lOFYTzfdcx8alCpu364a9/dvNNrjqMEf0yanLG1Csbcq6XIEsp6/0JivSokrvpZpYR/PxStdchnlbqgnsRHs4xbOfQ4EUVTMbnEo+rBSh+oZRlKWLw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787552111; c=relaxed/simple; bh=vzXhbUIp+JOMycGMc4kVLei7V7dGDSYy+8Y0EmXaucA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ojaxtfCzdKEX2jI4a09a6gW5E1shsXuJ+H9ws40pM8R4GlIUtK0RqlbVCCv03ilNVDRudEw/VuPix9FtWSVcCH/D5nYguLeIQuq46Bnh5bDDT0VArSAhMstZy2ZspqJGNvFIOwkcXNOJVqHa3FXp9wFkKtDVS7nnSXo+6H94kQw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VzgMO42y; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VzgMO42y" Received: by smtp.kernel.org (Postfix) with ESMTPS id 2B301C4AF14; Mon, 24 Aug 2026 06:15:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787552111; bh=vzXhbUIp+JOMycGMc4kVLei7V7dGDSYy+8Y0EmXaucA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=VzgMO42y/WEARNIYwXLi/mGUjhnNRHe/Ok7ZCRLItOF7chlD+jJW4nV/fEgxTYWCR G6FvG9opLs4YfeY6T0OSRq3fkt/DrVKVeXpCatWtgMyeVFbBqDUx4Au2fjcBMeQA3e 6GzQ88bN1SfJrhhMsfnbc15MgaZxjnSDzB1TQbmDANXoCt1S+N4F+jJ8dCjZd7NAAZ Rqh/TMKts3EuFD8LGvj8AKkag/9d4lrXRKGvZmJY5EfLHcTAbzcYF8WX+UShQ/mZHa ux8gGszN47WJbu5MwtEMtrNrOSTjFREBGrPyjahzjgYEOmTsGdBkEJehNULINeL2bN WAOq7jLObhuiA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13331C61CE2; Mon, 24 Aug 2026 06:15:11 +0000 (UTC) From: Jia Wang via B4 Relay Date: Mon, 24 Aug 2026 13:54:21 +0800 Subject: [PATCH 08/12] dt-bindings: net: snps,dwmac: Add compatible for UltraRISC DP1000 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260824-ultrarisc-dts-v1-8-61ab7aebe9e5@ultrarisc.com> References: <20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com> In-Reply-To: <20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Mark Brown , Andi Shyti , Mika Westerberg , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Eugeniy Paltsev , Vinod Koul , Frank Li Cc: Paul Walmsley , Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org, netdev@vger.kernel.org, dmaengine@vger.kernel.org, Jia Wang X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787552108; l=758; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=Q86cegl7t++dgBjUp6+7AoXi25GaD65bic8Z035YVIs=; b=THSNUqlenSAS4ni5Ye5ZxATHH6223T6W6rMJuIwRemA6bVK0aCCZw65tmt2JfJ7gqhcxyhPXc BoxQ78OqCvfDOw7MaXpXr1bvXQ5EGOge2Uq711Jg8TmOkQq0o+TyzPP X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Add the SoC-specific compatible string for the UltraRISC DP1000 GMAC controller to the DesignWare MAC binding. Signed-off-by: Jia Wang --- Documentation/devicetree/bindings/net/snps,dwmac.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Docume= ntation/devicetree/bindings/net/snps,dwmac.yaml index 2449311c6d28..2ed4564ae99d 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -119,6 +119,7 @@ properties: - starfive,jh7110-dwmac - tesla,fsd-ethqos - thead,th1520-gmac + - ultrarisc,dp1000-gmac =20 reg: minItems: 1 --=20 2.34.1 From nobody Mon Sep 28 10:01:08 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8CA53E51E8; Mon, 24 Aug 2026 06:15:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787552111; cv=none; b=ezOxUTpynmi8rkS2A18aRZxwZw4DiPDw39476REUsVlU4b8dEMrLBdCbnrOyF0KtSBBBD1M9laW6njAUZQ3aKsGgAkwitODsvgWiwl08wdVBgMnNYwQTqPa0T9rwQmm+sLmUv9jNji6880HDD0UesAn3Tlss8rUtzpIgTKGxrbY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787552111; c=relaxed/simple; bh=glx3nAmbQsN4q0EfNDaMpBD7eq+Eks/X4dswA2kjFcI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gMJuDgIWiSFoc1ApdIIxy6New3FMjoUTlFex1hgxVwccdezWdKhdu7Odat3J9L1DVDVnEUdOYrVvfwSJ8/eKCWDrs15MrytQt6voGFAzhX9a7TPbyYUW/lYOy1eUFZOxmE4HxKBOILpgkL27NPNzAt6e89Qj246G5NdkO7Lif+I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=smJDFDlk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="smJDFDlk" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3EF83C2BD01; Mon, 24 Aug 2026 06:15:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787552111; bh=glx3nAmbQsN4q0EfNDaMpBD7eq+Eks/X4dswA2kjFcI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=smJDFDlkT5CwXJaB8aNbBCFmQF+KwsGC0uuRp1x9fCO0kBwPOQxUuWwBVbs04DnVL 4jB0IwZtJeJXuVi5UlveQaeJEWdrdJSzzpyLBeUv64f/Gnh/CayMUHzn4IUOORRBZ1 iEa/c/VopCtQifrvE9MkVVD1cAUmSd+PlWeJDSq927FxgtISj2KZP4qfzV+iiyx7+X cf4ycSrr6lkLCXDiEjrL5POItKy+WY9utVAHaZ76I46zDWlio12BzS4ZN5DniA2Sp/ I7xLyjnx6C5GQmHhJ+q3MKfjnYRfPlNItfHMs4ixjISK1kbs+WRK/8qAttjWoX55WQ zUvb0vI4LvROg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27F70C61CE3; Mon, 24 Aug 2026 06:15:11 +0000 (UTC) From: Jia Wang via B4 Relay Date: Mon, 24 Aug 2026 13:54:22 +0800 Subject: [PATCH 09/12] dt-bindings: dma: snps,dw-axi-dmac: Add UltraRISC DP1000 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260824-ultrarisc-dts-v1-9-61ab7aebe9e5@ultrarisc.com> References: <20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com> In-Reply-To: <20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Mark Brown , Andi Shyti , Mika Westerberg , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Eugeniy Paltsev , Vinod Koul , Frank Li Cc: Paul Walmsley , Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org, netdev@vger.kernel.org, dmaengine@vger.kernel.org, Jia Wang X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787552108; l=814; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=4oeosRybkf+LUPam0Zh10Y726VZVVrxIb0o2ktnXvVs=; b=iwmXkiAPofSWAQ8A6OfDyPPy4yH7CvSvnz8uh+yNSBkdjiYoWnColYiK4XDpdjwCiOLNCQE0A EMJAq0q34gzBA9J+575SzH6hk+Wav9pzky7BoH0xmlsDziH62BJAo4U X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang The DP1000 integrates a DMA controller. Add its SoC-specific compatible with the generic fallback. Signed-off-by: Jia Wang Acked-by: Conor Dooley --- Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/= Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml index 0a30a455b0ee..f7b5891f41ae 100644 --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml @@ -27,6 +27,7 @@ properties: - enum: - altr,agilex5-axi-dma - sophgo,cv1800b-axi-dma + - ultrarisc,dp1000-axi-dma - const: snps,axi-dma-1.01a =20 reg: --=20 2.34.1 From nobody Mon Sep 28 10:01:08 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E93B3E49F6; Mon, 24 Aug 2026 06:15:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787552111; cv=none; b=ZSgK9Wf0K/vrG2EWas10AaZsdoBPMRR8zWzIUVMIhSuVwbXubM4bMMmTqYclU0qN52KXBuLQmvGzPaNfScNpUI+BdVTtTdu3OK576JwfvlglQzo2D4jpb1HX1Px9CLaRQmAIn9eHFUWrvoFFcBKg7D5focf//yysZbxqmq/44Ww= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787552111; c=relaxed/simple; bh=t8SbJSJbP/07LOGa8eQEHath0uBosDgzIyKlIz/zAB8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oZkyOCGmx+gNszjMUwgEu+2cRyw1haveGgH0R6ovnJ832Q5bqaKZe35L/TMbPAZk4FMMyTrR7/tPxnFRiSdLcSfs3N0K0nPF4F2tliPEoH/dAbLgSc248bxTMm+eSeSnFg+4xQf96W/1FrsVcBO2w+MClwQ0m1UCyLHZ1iOOf4E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XSq0BOe8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XSq0BOe8" Received: by smtp.kernel.org (Postfix) with ESMTPS id 5B3C5C4AF0F; Mon, 24 Aug 2026 06:15:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787552111; bh=t8SbJSJbP/07LOGa8eQEHath0uBosDgzIyKlIz/zAB8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=XSq0BOe8aFSo7WYZjGxs5V0JNU4DoqRTeimRpJH3wRgw/iIr+NwyxhS4Roz5jWOSJ 8tZ/GxKgpcEj216DdPcHM/AwXATYTfkH4k4L3CVeFcHzix4idVQUUN1xLX3P1qslsq eTbTdDPEZ7e3WrKfqgz6Pjfs8+kqvTQkKO+kCWpy+peG6i43f09i2GY04MEAVsPAIA jFxMtpqXvG7DSrvG4vc0q4s4mOkj/8qYXBago5BbMtHNl0z6qsP9PXAnSwSe5wdlyS rcncGv3WxjLHH15Lq8hBAt/hbXvzVkpcFVZDe2shR8Q8fTqE2ysFVdvGZPOwt+mJtR f8GZw0Ws11zNA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F8DDC5DF81; Mon, 24 Aug 2026 06:15:11 +0000 (UTC) From: Jia Wang via B4 Relay Date: Mon, 24 Aug 2026 13:54:23 +0800 Subject: [PATCH 10/12] riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260824-ultrarisc-dts-v1-10-61ab7aebe9e5@ultrarisc.com> References: <20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com> In-Reply-To: <20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Mark Brown , Andi Shyti , Mika Westerberg , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Eugeniy Paltsev , Vinod Koul , Frank Li Cc: Paul Walmsley , Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org, netdev@vger.kernel.org, dmaengine@vger.kernel.org, Jia Wang X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787552108; l=27157; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=K20Hnxb4RFIhG/FfPFjjgjtEU9u9FBz3mtyYlxXrpjA=; b=u4VRFTT+Vixu+SdFQQEWqlEj5JYsf+euS2JYV/2zzn/QIuPR10NxNKm4B9n9AXKeJ5cCEqh0a ZcuQa507e5rBYEpBII8ro6pQSbnVzVkIQvmSNtFZdGX+owu0jWJA2R7 X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Add the base device tree for the UltraRISC DP1000 SoC. It describes eight CP100 CPU cores, their cache topology, and essential peripherals including CLINT, PLIC, the clock controller, pinctrl, GPIO, UART, SPI, I2C, PCIe, GMAC, and the DMA controller. Signed-off-by: Jia Wang --- MAINTAINERS | 1 + arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 899 ++++++++++++++++++++++++++= ++++ 2 files changed, 900 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 1148168e8f8e..e7a962705154 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23523,6 +23523,7 @@ L: linux-riscv@lists.infradead.org S: Supported T: git https://github.com/ultrarisc/linux.git F: Documentation/devicetree/bindings/riscv/ultrarisc.yaml +F: arch/riscv/boot/dts/ultrarisc/ =20 RNBD BLOCK DRIVERS M: Md. Haris Iqbal diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dt= s/ultrarisc/dp1000.dtsi new file mode 100644 index 000000000000..470ab01e33b8 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi @@ -0,0 +1,899 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +/dts-v1/; + +#include + +/ { + compatible =3D "ultrarisc,dp1000"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <10000000>; + + cpu0: cpu@0 { + compatible =3D "ultrarisc,cp100", "riscv"; + reg =3D <0x0>; + device_type =3D "cpu"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type =3D "riscv,sv48"; + clock-frequency =3D <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x10000>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x10000>; + next-level-cache =3D <&l2_cache0>; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + + l2_cache0: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&cluster0_l3>; + }; + }; + + cpu1: cpu@1 { + compatible =3D "ultrarisc,cp100", "riscv"; + reg =3D <0x1>; + device_type =3D "cpu"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type =3D "riscv,sv48"; + clock-frequency =3D <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x10000>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x10000>; + next-level-cache =3D <&l2_cache1>; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + + cpu1_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + + l2_cache1: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&cluster0_l3>; + }; + }; + + cpu2: cpu@2 { + compatible =3D "ultrarisc,cp100", "riscv"; + reg =3D <0x2>; + device_type =3D "cpu"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type =3D "riscv,sv48"; + clock-frequency =3D <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x10000>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x10000>; + next-level-cache =3D <&l2_cache2>; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + + cpu2_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + + l2_cache2: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&cluster0_l3>; + }; + }; + + cpu3: cpu@3 { + compatible =3D "ultrarisc,cp100", "riscv"; + reg =3D <0x3>; + device_type =3D "cpu"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type =3D "riscv,sv48"; + clock-frequency =3D <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x10000>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x10000>; + next-level-cache =3D <&l2_cache3>; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + + cpu3_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + + l2_cache3: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&cluster0_l3>; + }; + }; + + cpu4: cpu@10 { + compatible =3D "ultrarisc,cp100", "riscv"; + reg =3D <0x10>; + device_type =3D "cpu"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type =3D "riscv,sv48"; + clock-frequency =3D <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x10000>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x10000>; + next-level-cache =3D <&l2_cache4>; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + + cpu4_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + + l2_cache4: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&cluster1_l3>; + }; + }; + cpu5: cpu@11 { + compatible =3D "ultrarisc,cp100", "riscv"; + reg =3D <0x11>; + device_type =3D "cpu"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type =3D "riscv,sv48"; + clock-frequency =3D <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x10000>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x10000>; + next-level-cache =3D <&l2_cache5>; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + + cpu5_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + + l2_cache5: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&cluster1_l3>; + }; + }; + cpu6: cpu@12 { + compatible =3D "ultrarisc,cp100", "riscv"; + reg =3D <0x12>; + device_type =3D "cpu"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type =3D "riscv,sv48"; + clock-frequency =3D <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x10000>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x10000>; + next-level-cache =3D <&l2_cache6>; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + + cpu6_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + + l2_cache6: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&cluster1_l3>; + }; + }; + + cpu7: cpu@13 { + compatible =3D "ultrarisc,cp100", "riscv"; + reg =3D <0x13>; + device_type =3D "cpu"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "h", + "zba", "zbb", "zbc", "zbs", "zicntr", + "zicsr", "zifencei", "zihpm", "ziccif", + "ziccrse", "ziccamoa", "za64rs", "zicbom", + "zicbop", "zicboz", "zkt", "svade", + "ssccptr", "sstvecd", "sscounterenw", + "shcounterenw", "shtvala", "shvstvecd", + "shvsatpa", "svvptc"; + mmu-type =3D "riscv,sv48"; + clock-frequency =3D <2000000000>; + /* + * L1 I-cache and D-cache: + * block-size 64B + * 4-way set associative, size 64KB + * per-core. + */ + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x10000>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x10000>; + next-level-cache =3D <&l2_cache7>; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + + cpu7_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + + l2_cache7: l2-cache { + /* + * L2 cache: + * cache-unified, block-size 64B + * 8-way set associative, size 512KB + * per-core. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-sets =3D <1024>; + cache-unified; + next-level-cache =3D <&cluster1_l3>; + }; + }; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + }; + + cluster1: cluster1 { + core0 { + cpu =3D <&cpu4>; + }; + + core1 { + cpu =3D <&cpu5>; + }; + + core2 { + cpu =3D <&cpu6>; + }; + + core3 { + cpu =3D <&cpu7>; + }; + }; + }; + + cluster0_l3: l3-cache0 { + /* + * L3 cache: + * cache-unified, block-size 64B + * 16-way set associative, size 4MB + * per-cluster. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <3>; + cache-size =3D <0x400000>; + cache-sets =3D <0x1000>; + cache-unified; + next-level-cache =3D <&l4_cache>; + }; + + cluster1_l3: l3-cache1 { + /* + * L3 cache: + * cache-unified, block-size 64B + * 16-way set associative, size 4MB + * per-cluster. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <3>; + cache-size =3D <0x400000>; + cache-sets =3D <0x1000>; + cache-unified; + next-level-cache =3D <&l4_cache>; + }; + }; + + l4_cache: l4-cache { + /* + * L4 cache: + * cache-unified, block-size 64B + * 16-way set associative, size 16MB + * shared by the SoC. + */ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <4>; + cache-size =3D <0x1000000>; + cache-sets =3D <0x4000>; + cache-unified; + }; + + osc_24m: clock-24m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + }; + + soc { + compatible =3D "simple-bus"; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + + clint: clint@8000000 { + compatible =3D "ultrarisc,dp1000-clint", "sifive,clint0"; + reg =3D <0x0 0x8000000 0x0 0x100000>; + interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>, + <&cpu5_intc 3>, <&cpu5_intc 7>, + <&cpu6_intc 3>, <&cpu6_intc 7>, + <&cpu7_intc 3>, <&cpu7_intc 7>; + }; + + plic: plic@9000000 { + compatible =3D "ultrarisc,dp1000-plic", "ultrarisc,cp100-plic"; + reg =3D <0x0 0x9000000 0x0 0x4000000>; + #interrupt-cells =3D <1>; + #address-cells =3D <0>; + interrupt-controller; + interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>, <&cpu0_intc 10= >, + <&cpu1_intc 11>, <&cpu1_intc 9>, <&cpu1_intc 10>, + <&cpu2_intc 11>, <&cpu2_intc 9>, <&cpu2_intc 10>, + <&cpu3_intc 11>, <&cpu3_intc 9>, <&cpu3_intc 10>, + <&cpu4_intc 11>, <&cpu4_intc 9>, <&cpu4_intc 10>, + <&cpu5_intc 11>, <&cpu5_intc 9>, <&cpu5_intc 10>, + <&cpu6_intc 11>, <&cpu6_intc 9>, <&cpu6_intc 10>, + <&cpu7_intc 11>, <&cpu7_intc 9>, <&cpu7_intc 10>; + riscv,ndev =3D <160>; + }; + + clkc: clock-controller@11080000 { + compatible =3D "ultrarisc,dp1000-clk"; + reg =3D <0x0 0x11080000 0x0 0x1000>; + clocks =3D <&osc_24m>; + #clock-cells =3D <1>; + }; + + pinctrl: pinctrl@11081000 { + compatible =3D "ultrarisc,dp1000-pinctrl"; + reg =3D <0x0 0x11081000 0x0 0x1000>; + }; + + gpio: gpio@20200000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0x0 0x20200000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-names =3D "bus", "db"; + clocks =3D <&clkc DP1000_CLK_SUBSYS>, + <&clkc DP1000_CLK_SUBSYS>; + + gpio_a: gpio-port@0 { + compatible =3D "snps,dw-apb-gpio-port"; + reg =3D <0>; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <16>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&plic>; + interrupts =3D <34>; + gpio-ranges =3D <&pinctrl 0 0 16>; + }; + + gpio_b: gpio-port@1 { + compatible =3D "snps,dw-apb-gpio-port"; + reg =3D <1>; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <8>; + gpio-ranges =3D <&pinctrl 0 16 8>; + }; + + gpio_c: gpio-port@2 { + compatible =3D "snps,dw-apb-gpio-port"; + reg =3D <2>; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <8>; + gpio-ranges =3D <&pinctrl 0 24 8>; + }; + + gpio_d: gpio-port@3 { + compatible =3D "snps,dw-apb-gpio-port"; + reg =3D <3>; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <8>; + gpio-ranges =3D <&pinctrl 0 32 8>; + }; + }; + + uart0: serial@20300000 { + compatible =3D "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0x20300000 0x0 0x10000>; + interrupt-parent =3D <&plic>; + interrupts =3D <17>; + clocks =3D <&clkc DP1000_CLK_UART0>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names =3D "baudclk", "apb_pclk"; + reg-io-width =3D <4>; + reg-shift =3D <2>; + }; + + uart1: serial@20310000 { + compatible =3D "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0x20310000 0x0 0x10000>; + interrupt-parent =3D <&plic>; + interrupts =3D <18>; + clocks =3D <&clkc DP1000_CLK_UART1>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names =3D "baudclk", "apb_pclk"; + reg-io-width =3D <4>; + reg-shift =3D <2>; + }; + + uart2: serial@20400000 { + compatible =3D "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0x20400000 0x0 0x10000>; + interrupt-parent =3D <&plic>; + interrupts =3D <25>; + clocks =3D <&clkc DP1000_CLK_UART2>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names =3D "baudclk", "apb_pclk"; + reg-io-width =3D <4>; + reg-shift =3D <2>; + }; + + uart3: serial@20410000 { + compatible =3D "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0x20410000 0x0 0x10000>; + interrupt-parent =3D <&plic>; + interrupts =3D <26>; + clocks =3D <&clkc DP1000_CLK_UART3>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names =3D "baudclk", "apb_pclk"; + reg-io-width =3D <4>; + reg-shift =3D <2>; + }; + + spi0: spi@20320000 { + compatible =3D "ultrarisc,dp1000-spi", "snps,dw-apb-ssi"; + reg =3D <0x0 0x20320000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clkc DP1000_CLK_SPI0>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names =3D "ssi_clk", "pclk"; + interrupt-parent =3D <&plic>; + interrupts =3D <19>; + num-cs =3D <3>; + }; + + spi1: spi@20420000 { + compatible =3D "ultrarisc,dp1000-spi", "snps,dw-apb-ssi"; + reg =3D <0x0 0x20420000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clkc DP1000_CLK_SPI1>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names =3D "ssi_clk", "pclk"; + interrupt-parent =3D <&plic>; + interrupts =3D <27>; + num-cs =3D <3>; + }; + + i2c0: i2c@20330000 { + compatible =3D "ultrarisc,dp1000-i2c", "snps,designware-i2c"; + reg =3D <0x0 0x20330000 0x0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <400000>; + clocks =3D <&clkc DP1000_CLK_I2C0>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names =3D "ref", "pclk"; + interrupt-parent =3D <&plic>; + interrupts =3D <20>; + }; + + i2c1: i2c@20340000 { + compatible =3D "ultrarisc,dp1000-i2c", "snps,designware-i2c"; + reg =3D <0x0 0x20340000 0x0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <400000>; + clocks =3D <&clkc DP1000_CLK_I2C1>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names =3D "ref", "pclk"; + interrupt-parent =3D <&plic>; + interrupts =3D <21>; + }; + + i2c2: i2c@20430000 { + compatible =3D "ultrarisc,dp1000-i2c", "snps,designware-i2c"; + reg =3D <0x0 0x20430000 0x0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <400000>; + clocks =3D <&clkc DP1000_CLK_I2C2>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names =3D "ref", "pclk"; + interrupt-parent =3D <&plic>; + interrupts =3D <28>; + }; + + i2c3: i2c@20440000 { + compatible =3D "ultrarisc,dp1000-i2c", "snps,designware-i2c"; + reg =3D <0x0 0x20440000 0x0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <400000>; + clocks =3D <&clkc DP1000_CLK_I2C3>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names =3D "ref", "pclk"; + interrupt-parent =3D <&plic>; + interrupts =3D <29>; + }; + + pcie_x16: pcie@21000000 { + compatible =3D "ultrarisc,dp1000-pcie"; + reg =3D <0x0 0x21000000 0x0 0x1000000>, + <0x0 0x4fff0000 0x0 0x10000>; + reg-names =3D "dbi", "config"; + clocks =3D <&clkc DP1000_CLK_PCIEX16_CORE>, + <&clkc DP1000_CLK_PCIE_DBI>, + <&clkc DP1000_CLK_PCIE_AUX>; + clock-names =3D "core", "dbi", "aux"; + ranges =3D <0x81000000 0x0 0x00000000 0x0 0x4fbf0000 0x0 0x00400000>, + <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, + <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + bus-range =3D <0x0 0xff>; + num-lanes =3D <16>; + interrupt-parent =3D <&plic>; + interrupts =3D <43>, <44>, <45>, <46>, <47>; + interrupt-names =3D "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0x0 0x0 0x0 0x1 &plic 44>, + <0x0 0x0 0x0 0x2 &plic 45>, + <0x0 0x0 0x0 0x3 &plic 46>, + <0x0 0x0 0x0 0x4 &plic 47>; + + status =3D "disabled"; + }; + + pcie_x4a: pcie@23000000 { + compatible =3D "ultrarisc,dp1000-pcie"; + reg =3D <0x0 0x23000000 0x0 0x1000000>, + <0x0 0x6fff0000 0x0 0x10000>; + reg-names =3D "dbi", "config"; + clocks =3D <&clkc DP1000_CLK_PCIEX4_CORE>, + <&clkc DP1000_CLK_PCIE_DBI>, + <&clkc DP1000_CLK_PCIE_AUX>; + clock-names =3D "core", "dbi", "aux"; + ranges =3D <0x81000000 0x0 0x00000000 0x0 0x6fbf0000 0x0 0x00400000>, + <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>, + <0xc3000000 0x80 0x00000000 0x80 0x00000000 0xd 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + bus-range =3D <0x0 0xff>; + num-lanes =3D <4>; + interrupt-parent =3D <&plic>; + interrupts =3D <63>, <64>, <65>, <66>, <67>; + interrupt-names =3D "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0x0 0x0 0x0 0x1 &plic 64>, + <0x0 0x0 0x0 0x2 &plic 65>, + <0x0 0x0 0x0 0x3 &plic 66>, + <0x0 0x0 0x0 0x4 &plic 67>; + + status =3D "disabled"; + }; + + pcie_x4b: pcie@24000000 { + compatible =3D "ultrarisc,dp1000-pcie"; + reg =3D <0x0 0x24000000 0x0 0x1000000>, + <0x0 0x7fff0000 0x0 0x10000>; + reg-names =3D "dbi", "config"; + clocks =3D <&clkc DP1000_CLK_PCIEX4_CORE>, + <&clkc DP1000_CLK_PCIE_DBI>, + <&clkc DP1000_CLK_PCIE_AUX>; + clock-names =3D "core", "dbi", "aux"; + ranges =3D <0x81000000 0x0 0x00000000 0x0 0x7fbf0000 0x0 0x00400000>, + <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>, + <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0xd 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + bus-range =3D <0x0 0xff>; + num-lanes =3D <4>; + interrupt-parent =3D <&plic>; + interrupts =3D <73>, <74>, <75>, <76>, <77>; + interrupt-names =3D "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0x0 0x0 0x0 0x1 &plic 74>, + <0x0 0x0 0x0 0x2 &plic 75>, + <0x0 0x0 0x0 0x3 &plic 76>, + <0x0 0x0 0x0 0x4 &plic 77>; + + status =3D "disabled"; + }; + + ethernet: ethernet@38000000 { + compatible =3D "ultrarisc,dp1000-gmac", "snps,dwmac-5.20", + "snps,dwmac"; + reg =3D <0x0 0x38000000 0x0 0x1000000>; + clocks =3D <&clkc DP1000_CLK_GMAC>; + clock-names =3D "stmmaceth"; + interrupt-parent =3D <&plic>; + interrupts =3D <84>; + interrupt-names =3D "macirq"; + snps,txpbl =3D <8>; + snps,rxpbl =3D <8>; + + status =3D "disabled"; + }; + + dmac: dma-controller@39000000 { + compatible =3D "ultrarisc,dp1000-axi-dma", "snps,axi-dma-1.01a"; + reg =3D <0x0 0x39000000 0x0 0x400>; + clocks =3D <&clkc DP1000_CLK_SYSPLL_DIV2>, + <&clkc DP1000_CLK_SUBSYS>; + clock-names =3D "core-clk", "cfgr-clk"; + #dma-cells =3D <1>; + dma-channels =3D <8>; + interrupt-parent =3D <&plic>; + interrupts =3D <152>; + snps,dma-masters =3D <1>; + snps,data-width =3D <4>; + snps,block-size =3D <512 512 512 512 512 512 512 512>; + snps,priority =3D <0 1 2 3 4 5 6 7>; + snps,axi-max-burst-len =3D <256>; + }; + }; +}; --=20 2.34.1 From nobody Mon Sep 28 10:01:08 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7ACC3E49F5; Mon, 24 Aug 2026 06:15:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787552111; cv=none; b=UkSC/3pbTuSHuJBRXnTQ+gS4TtRHUgVJ2mY2AJb6UqsB+UvIlbkwM1EnOKeSHq5wWSoaWfTvO7+k0GanS8trjfU83pGTaPZIqR8ejb/sE7LC2OzkK0NMXOo3ibvj3xyhZb4Tf9gP+foKIL8pzLH1FRivnXm3ix4p0XVxPYwot4g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787552111; c=relaxed/simple; bh=d/97sB9yXoZ5Hr4PrQPzx5HtGOwTN1VEBcKj6JjfMh0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JciWRtZvHzmBKXYBf85LQWwyPa0WOzttcWl9y15aKW2joRqkTVUh4nvwvLgTyF3XJ9pVsndyfEMqqArYPIAM30sP/NPxlXq3RaKT51g2iEXVzcK3kb2bQjztUzC3TuDB7y+6DhjIVQ+MTEYNJvnvwwlPsoEdLcbKFxaMAmD9NA0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jPZwxKc4; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jPZwxKc4" Received: by smtp.kernel.org (Postfix) with ESMTPS id 68485C4AF54; Mon, 24 Aug 2026 06:15:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787552111; bh=d/97sB9yXoZ5Hr4PrQPzx5HtGOwTN1VEBcKj6JjfMh0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=jPZwxKc4h/68zODeRfEL2qwO3k0cMbnHMgARpZetCkPsIxEyqG73mcsM75RZcxX/l K/0scLzOGrtCHjQfj7PNH1W5VYbWsUdWrxJUaHIsQUY+ijSz0YhYK8YCrH1CXUCbLF nGwYpcQQLJM412bqEDuj6oyGieAaQvtxrQiLI7KQH5Gq8LqUMB2TXHMIpsdOVYn6Z5 y5+EP+TfyoCWtOWAHSt3RJ9TmQVd5wOef+4ZzYPJY+olVhg4HI8WWMcJK1Hcm3udV9 VsK1dwirAZkBHvX9hUYeWYZXyL7xhZXE0CcxNt42ut62fg+ROT3zARiqyCH3eMDtnY ZKgjhIa1S/pEA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52F65C5DF9D; Mon, 24 Aug 2026 06:15:11 +0000 (UTC) From: Jia Wang via B4 Relay Date: Mon, 24 Aug 2026 13:54:24 +0800 Subject: [PATCH 11/12] riscv: dts: ultrarisc: Add Shenzhen Rongda M0 board device tree Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260824-ultrarisc-dts-v1-11-61ab7aebe9e5@ultrarisc.com> References: <20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com> In-Reply-To: <20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Mark Brown , Andi Shyti , Mika Westerberg , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Eugeniy Paltsev , Vinod Koul , Frank Li Cc: Paul Walmsley , Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org, netdev@vger.kernel.org, dmaengine@vger.kernel.org, Jia Wang X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787552108; l=6623; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=VdtPdgAxWwRO256lD7Yt9GobfVR5Y/a9bayAnZ+sowg=; b=RARhmPur7yhZH2cweeTkT3tEDxZqGP66VILv207fNDoxM+69X/On1VwolT40j4oWbN78hk9NF N4dYW2aJ8i1DLNbedALamHNdku0WgLz1+nAOjjBkyzFdyueQPq3UZX5 X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Shenzhen Rongda M0 is an mATX motherboard based on the UltraRISC DP1000 SoC. Signed-off-by: Jia Wang --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/ultrarisc/Makefile | 2 + arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h | 63 ++++++++++++ .../ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi | 79 ++++++++++++++ .../boot/dts/ultrarisc/dp1000-shenrongda-m0.dts | 114 +++++++++++++++++= ++++ 5 files changed, 259 insertions(+) diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index 69d8751fb17c..702882974251 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -12,3 +12,4 @@ subdir-y +=3D spacemit subdir-y +=3D starfive subdir-y +=3D tenstorrent subdir-y +=3D thead +subdir-y +=3D ultrarisc diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/u= ltrarisc/Makefile new file mode 100644 index 000000000000..454d849a6ce4 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ULTRARISC) +=3D dp1000-shenrongda-m0.dtb diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h b/arch/riscv/bo= ot/dts/ultrarisc/dp1000-pinctrl.h new file mode 100644 index 000000000000..4668e45d2335 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#ifndef _DP1000_PINCTRL_H +#define _DP1000_PINCTRL_H + +#define PA0 0 +#define PA1 1 +#define PA2 2 +#define PA3 3 +#define PA4 4 +#define PA5 5 +#define PA6 6 +#define PA7 7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 16 +#define PB1 17 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PC0 24 +#define PC1 25 +#define PC2 26 +#define PC3 27 +#define PC4 28 +#define PC5 29 +#define PC6 30 +#define PC7 31 +#define PD0 32 +#define PD1 33 +#define PD2 34 +#define PD3 35 +#define PD4 36 +#define PD5 37 +#define PD6 38 +#define PD7 39 +#define LPC0 40 +#define LPC1 41 +#define LPC2 42 +#define LPC3 43 +#define LPC4 44 +#define LPC5 45 +#define LPC6 46 +#define LPC7 47 +#define LPC8 48 +#define LPC9 49 +#define LPC10 50 +#define LPC11 51 +#define LPC12 52 + +#endif /* _DP1000_PINCTRL_H */ diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dts= i b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi new file mode 100644 index 000000000000..ab927c6cd614 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#include "dp1000.dtsi" +#include "dp1000-pinctrl.h" + +&pinctrl { + i2c0_pins: i2c0-pins { + pins =3D ; + function =3D "i2c"; + bias-pull-up; + drive-strength =3D <33>; + }; + + i2c1_pins: i2c1-pins { + pins =3D ; + function =3D "i2c"; + bias-pull-up; + drive-strength =3D <33>; + }; + + i2c2_pins: i2c2-pins { + pins =3D ; + function =3D "i2c"; + bias-pull-up; + drive-strength =3D <33>; + }; + + i2c3_pins: i2c3-pins { + pins =3D ; + function =3D "i2c"; + bias-pull-up; + drive-strength =3D <33>; + }; + + spi0_pins: spi0-pins { + pins =3D ; + function =3D "spi"; + bias-pull-up; + drive-strength =3D <33>; + }; + + spi1_pins: spi1-pins { + pins =3D ; + function =3D "spi"; + bias-pull-up; + drive-strength =3D <33>; + }; + + uart0_pins: uart0-pins { + pins =3D ; + function =3D "uart"; + bias-pull-up; + drive-strength =3D <33>; + }; + + uart1_pins: uart1-pins { + pins =3D ; + function =3D "uart"; + bias-pull-up; + drive-strength =3D <33>; + }; + + uart2_pins: uart2-pins { + pins =3D ; + function =3D "uart"; + bias-pull-up; + drive-strength =3D <33>; + }; + + uart3_pins: uart3-pins { + pins =3D ; + function =3D "uart"; + bias-pull-up; + drive-strength =3D <33>; + }; +}; diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts b/arch/= riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts new file mode 100644 index 000000000000..da831da819ef --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#include "dp1000-shenrongda-m0-pinctrl.dtsi" +#include + +/ { + model =3D "Shenzhen Rongda M0 Board"; + compatible =3D "shenrongda,m0", "ultrarisc,dp1000"; + + aliases { + serial0 =3D &uart0; + serial1 =3D &uart1; + serial2 =3D &uart2; + serial3 =3D &uart3; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins>; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_pins>; +}; + +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2_pins>; + + rtc@32 { + compatible =3D "whwave,sd3078"; + reg =3D <0x32>; + }; +}; + +&i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3_pins>; +}; + +&spi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi0_pins>; +}; + +&spi1 { + num-cs =3D <1>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi1_pins>; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pins>; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1_pins>; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart2_pins>; +}; + +&uart3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart3_pins>; +}; + +&pcie_x16 { + status =3D "okay"; +}; + +&pcie_x4a { + status =3D "okay"; +}; + +&pcie_x4b { + status =3D "okay"; +}; + +ðernet { + phy-handle =3D <&phy0>; + /* + * YT8531 RGMII timing on this board requires no PHY internal delays. + * Using "rgmii-id" together with rx/tx-internal-delay-ps results in RX C= RC + * errors and no usable traffic, so keep plain "rgmii" here. + */ + phy-mode =3D "rgmii"; + + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + phy0: phy@0 { + reg =3D <0>; + }; + }; +}; --=20 2.34.1 From nobody Mon Sep 28 10:01:08 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C93153E5A01; Mon, 24 Aug 2026 06:15:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787552111; cv=none; b=NIBsvs61RFH4yWfjZbBv1QjRNoR+znAC1rQfiJBCmEMRbsvOQddE0JH2OdgT91susZeHfMrvKQIVzUIeoY4VtdpS08gDgs4uY5ZHWfUglAEbl8PsN3vmc4KxKHOQNFdmaO5drwRYEHqBCA3KLK7J9bPhXsb1ifKC4RDG+Xgzh8o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787552111; c=relaxed/simple; bh=X5m53fEjiCLQUHwbyO6HUdCjFfSdafZX1sAdv/zfC/M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dmrulb9hb9qDdQiHqtSuDI3ffxmZN0e1BYZt2aYwjfaUUUNLlx+a/7fIzKGshq8IxUITVz6SFIGW9SKHlYJgRYzPiYtG/eUc3JbkdWs8AqK8Vb8wV0AIj+gY/Eh/KuB4rTOQ/scEm0bJKADJMz3JBfliemlgc9ajRs4RgCYMAtg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pG1BOiGk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pG1BOiGk" Received: by smtp.kernel.org (Postfix) with ESMTPS id 80A93C4AF15; Mon, 24 Aug 2026 06:15:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787552111; bh=X5m53fEjiCLQUHwbyO6HUdCjFfSdafZX1sAdv/zfC/M=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=pG1BOiGkqkdHlRvvF9FpLdWT8t0rM1iHdg6/2tNfs/3bbYoBuIVgwAn+BDQe5rmJI Q6BxWf+Xyqwj75XnIKRZZUda/AbvOU9G6a8Ev/JNkhfvnrabQ6Eq4yeGgfwOWCiHpt ToDtKcZBz5GWkMwAgbeRr/0Byx1P8viX4n8F03J/FKqbZ6hmTXBBGWxz8aTAVQKbb/ uQwcsZol/ct6w/w556uovCzqkXapHNWh/AuRgU945yySQ8s6jjGxoZzt4rNl328M5+ lBJ0gHnWXutmdjc4bdWAtHNcCORfnRNJC6OyJep01nhgt2ri0uuomyrkZgcj+p6z2W mjPNhfrYWwl5A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6911EC61CE2; Mon, 24 Aug 2026 06:15:11 +0000 (UTC) From: Jia Wang via B4 Relay Date: Mon, 24 Aug 2026 13:54:25 +0800 Subject: [PATCH 12/12] riscv: dts: ultrarisc: Add Milk-V Titan board device tree Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260824-ultrarisc-dts-v1-12-61ab7aebe9e5@ultrarisc.com> References: <20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com> In-Reply-To: <20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Mark Brown , Andi Shyti , Mika Westerberg , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Eugeniy Paltsev , Vinod Koul , Frank Li Cc: Paul Walmsley , Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org, netdev@vger.kernel.org, dmaengine@vger.kernel.org, Jia Wang X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787552108; l=7355; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=zBhtRfmKKWpJufh5JQfrWxerGCRdaDPbp3rtX+6ZO1c=; b=3jzES90pfxMiJBYWUQ6MSAJXJiiH4BhSUaV6y79VZz5pBaLoIzpUeePKM0sYg7t1D9FUKxt0+ iVoJ+mii09BB7enwkirZz2y1AzNIJIH1c1zy6xwP5iEgeJTyo+k19RX X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Milk-V Titan is an ITX motherboard based on the UltraRISC DP1000 SoC. Link: https://milkv.io/docs/titan/overview Signed-off-by: Jia Wang --- arch/riscv/boot/dts/ultrarisc/Makefile | 1 + .../dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi | 108 +++++++++++ .../boot/dts/ultrarisc/dp1000-milkv-titan.dts | 203 +++++++++++++++++= ++++ 3 files changed, 312 insertions(+) diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/u= ltrarisc/Makefile index 454d849a6ce4..dfd15c064d07 100644 --- a/arch/riscv/boot/dts/ultrarisc/Makefile +++ b/arch/riscv/boot/dts/ultrarisc/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ULTRARISC) +=3D dp1000-milkv-titan.dtb dtb-$(CONFIG_ARCH_ULTRARISC) +=3D dp1000-shenrongda-m0.dtb diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi = b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi new file mode 100644 index 000000000000..7a812e40a249 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#include "dp1000.dtsi" +#include "dp1000-pinctrl.h" + +&pinctrl { + i2c0_pins: i2c0-pins { + pins =3D ; + function =3D "i2c"; + bias-pull-up; + drive-strength =3D <33>; + }; + + i2c1_pins: i2c1-pins { + pins =3D ; + function =3D "i2c"; + bias-pull-up; + drive-strength =3D <33>; + }; + + i2c2_pins: i2c2-pins { + pins =3D ; + function =3D "i2c"; + bias-pull-up; + drive-strength =3D <33>; + }; + + i2c3_pins: i2c3-pins { + pins =3D ; + function =3D "i2c"; + bias-pull-up; + drive-strength =3D <33>; + }; + + io_pins: io-pins { + pins =3D ; + function =3D "gpio"; + bias-pull-up; + drive-strength =3D <33>; + }; + + gpio_keys_pins: gpio-keys-pins { + pins =3D ; + function =3D "gpio"; + bias-pull-up; + drive-strength =3D <33>; + }; + + mux_dcdc_i2c_pins: mux-dcdc-i2c-pins { + pins =3D ; + function =3D "gpio"; + }; + + mux_i2c3_pins: mux-i2c3-pins { + pins =3D ; + function =3D "gpio"; + }; + + mux_uart0_pins: mux-uart0-pins { + pins =3D ; + function =3D "gpio"; + }; + + spi0_pins: spi0-pins { + pins =3D ; + function =3D "spi"; + bias-pull-up; + drive-strength =3D <33>; + }; + + spi1_pins: spi1-pins { + pins =3D ; + function =3D "spi"; + bias-pull-up; + drive-strength =3D <33>; + }; + + uart0_pins: uart0-pins { + pins =3D ; + function =3D "uart"; + bias-pull-up; + drive-strength =3D <33>; + }; + + uart1_pins: uart1-pins { + pins =3D ; + function =3D "uart"; + bias-pull-up; + drive-strength =3D <33>; + }; + + uart2_pins: uart2-pins { + pins =3D ; + function =3D "uart"; + bias-pull-up; + drive-strength =3D <33>; + }; + + uart3_pins: uart3-pins { + pins =3D ; + function =3D "uart"; + bias-pull-up; + drive-strength =3D <33>; + }; +}; diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts b/arch/ri= scv/boot/dts/ultrarisc/dp1000-milkv-titan.dts new file mode 100644 index 000000000000..f1a0efee3d74 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#include "dp1000-milkv-titan-pinctrl.dtsi" +#include +#include +#include +#include +#include + +/ { + model =3D "Milk-V Titan"; + compatible =3D "milkv,titan", "ultrarisc,dp1000"; + + aliases { + serial0 =3D &uart0; + serial1 =3D &uart1; + serial2 =3D &uart2; + serial3 =3D &uart3; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio_keys_pins>; + + key-wakeup-0 { + label =3D "Wake-Up"; + gpios =3D <&gpio_a 14 GPIO_ACTIVE_LOW>; + linux,code =3D ; + linux,input-type =3D ; + debounce-interval =3D <10>; + wakeup-source; + wakeup-event-action =3D ; + }; + + key-wakeup-1 { + label =3D "Power"; + gpios =3D <&gpio_a 11 GPIO_ACTIVE_LOW>; + linux,code =3D ; + linux,input-type =3D ; + debounce-interval =3D <10>; + wakeup-source; + wakeup-event-action =3D ; + }; + + key-wakeup-2 { + label =3D "Wake-Up-by-USB"; + interrupts-extended =3D <&gpio_a 4 IRQ_TYPE_EDGE_FALLING>; + linux,code =3D ; + linux,input-type =3D ; + debounce-interval =3D <10>; + wakeup-source; + }; + }; +}; + +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins>; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_pins>; +}; + +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2_pins>; + + rtc@68 { + compatible =3D "st,m41t11"; + reg =3D <0x68>; + }; +}; + +&i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3_pins>; +}; + +&spi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi0_pins>; +}; + +&spi1 { + num-cs =3D <1>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi1_pins>; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pins>; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1_pins>; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart2_pins>; +}; + +&uart3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart3_pins>; +}; + +&pcie_x16 { + status =3D "okay"; +}; + +&pcie_x4a { + status =3D "okay"; +}; + +&pcie_x4b { + status =3D "okay"; +}; + +&gpio { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&io_pins &mux_dcdc_i2c_pins &mux_i2c3_pins &mux_uart0_pins= >; +}; + +&gpio_a { + dcdc-i2c-mux-hog { + gpio-hog; + gpios =3D <5 GPIO_ACTIVE_HIGH>; + output-low; + line-name =3D "dcdc-i2c-mux"; + }; + + i2c3-mux-hog { + gpio-hog; + gpios =3D <6 GPIO_ACTIVE_HIGH>; + output-low; + line-name =3D "i2c3-mux"; + }; + + uart0-mux-hog { + gpio-hog; + gpios =3D <7 GPIO_ACTIVE_HIGH>; + output-high; + line-name =3D "uart0-mux"; + }; +}; + +ðernet { + phy-handle =3D <&phy0>; + /* + * RTL8211F: board timing uses PHY strap delays; keep plain "rgmii". + * Enabling PHY internal delays via "rgmii-id" breaks Ethernet traffic. + */ + phy-mode =3D "rgmii"; + + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + phy0: phy@0 { + reg =3D <0>; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@1 { + label =3D "eth-link"; + reg =3D <1>; + color =3D ; + function =3D LED_FUNCTION_INDICATOR; + default-state =3D "keep"; + linux,default-trigger =3D "netdev"; + }; + + led@2 { + label =3D "eth-activity"; + reg =3D <2>; + color =3D ; + function =3D LED_FUNCTION_ACTIVITY; + default-state =3D "keep"; + linux,default-trigger =3D "netdev"; + }; + }; + }; + }; +}; --=20 2.34.1