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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-141861732f8sm21667830c88.10.2026.08.23.23.37.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Aug 2026 23:37:54 -0700 (PDT) From: Varadarajan Narayanan Date: Mon, 24 Aug 2026 12:07:41 +0530 Subject: [PATCH 1/5] dt-bindings: phy: qcom,qmp-usb: Add IPQ9650 USB3 PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260824-phy-v1-1-257d68a3210b@oss.qualcomm.com> References: <20260824-phy-v1-0-257d68a3210b@oss.qualcomm.com> In-Reply-To: <20260824-phy-v1-0-257d68a3210b@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI0MDA1NyBTYWx0ZWRfX186b1s/fZ0AI 67Ww8nDhEievDUXyBiahq/R/9HceZJfR4Kk4a9wM6ULNmA2Gn6ZwbNff5RSYPrzwwrFmVFfnoMm IS/UoymlCOeUzDqlT/qBU/B12G1+RhMsuzA8SfAgbpmT9elatZYxb85tGdTHcAXBL832o0bc98m QY8sSmnGTdfl1t+yIqtNeyHmcsuT+s3iJleN3QOSUHfbWWgsbcpxSWE45WEbKfoq47pSNWp9KX1 iPiqUoSX1AzviM4yNrWg32Sn/aIV26MCUQhmD1xLXmTC/dF+NEAeMajZk2z++Ftfj6EQzwH1OZA YA2qn4JaAMqVLPbYpV/jfy5sd8zg7YQ8tG0bjePDP1vfuicT3mOyHFZUnasfOPMh1AlHQaUWLVQ 1Dnpff6zg9x+k4At9Az0EwY2Z0pKRLUgjEbaZ1MjWl3ZRiwGJIQ4wbsMIeCFAuFrtPpfuBVibRj VVSlkTDliv4wsbw8iIQ== X-Authority-Analysis: v=2.4 cv=GvNyPE1C c=1 sm=1 tr=0 ts=6a8be6c8 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=CyeWGLuohibXKJY0YOUA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-ORIG-GUID: v-hrLuMFLpCsUamrU3Wn2GnfHh0Fmcou X-Proofpoint-Spam-Info: AW1haW4tMjYwODI0MDA1NyBTYWx0ZWRfXyALrrvZVFZEp 7ntmvIoyayl9+zxxIZTm9yO579dsecgXq7B7Qax671D+bdJlExchYgYsNnWVkfiyVuOKTC+OaeG lm37MQqHtLf3M+uox11OGzIZC5ZW1po= X-Proofpoint-GUID: v-hrLuMFLpCsUamrU3Wn2GnfHh0Fmcou X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-24_02,2026-08-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 adultscore=0 impostorscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608240057 Document the Qualcomm IPQ9650 USB3 QMP PHY compatible. Use a standalone compatible because the IPQ9650 PHY has register configuration data that differs from the currently supported SoCs and should not fall back to an existing definition. Signed-off-by: Varadarajan Narayanan Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | = 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-u= ni-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-= uni-phy.yaml index 01342823e57f..746c5a331f48 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.= yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.= yaml @@ -23,6 +23,7 @@ properties: - qcom,ipq6018-qmp-usb3-phy - qcom,ipq8074-qmp-usb3-phy - qcom,ipq9574-qmp-usb3-phy + - qcom,ipq9650-qmp-usb3-phy - qcom,msm8996-qmp-usb3-phy - qcom,qcs8300-qmp-usb3-uni-phy - qcom,qdu1000-qmp-usb3-uni-phy @@ -102,6 +103,7 @@ allOf: - qcom,ipq6018-qmp-usb3-phy - qcom,ipq8074-qmp-usb3-phy - qcom,ipq9574-qmp-usb3-phy + - qcom,ipq9650-qmp-usb3-phy - qcom,msm8996-qmp-usb3-phy - qcom,sdx55-qmp-usb3-uni-phy - qcom,sdx65-qmp-usb3-uni-phy --=20 2.34.1 From nobody Mon Sep 28 09:59:14 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 172A43E7624 for ; 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The PHY uses the SNPS HS 6 nm PHY fallback, so allow it in the binding. Signed-off-by: Varadarajan Narayanan --- Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.y= aml b/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml index 661759b25064..405bfad2080e 100644 --- a/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml @@ -20,6 +20,10 @@ properties: - qcom,sa8775p-usb-hs-phy - qcom,sc8280xp-usb-hs-phy - const: qcom,usb-snps-hs-5nm-phy + - items: + - enum: + - qcom,ipq9650-usb-hs-phy + - const: qcom,usb-snps-hs-6nm-phy - items: - enum: - qcom,qcs8300-usb-hs-phy --=20 2.34.1 From nobody Mon Sep 28 09:59:14 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEA8C3E4C61 for ; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-141861732f8sm21667830c88.10.2026.08.23.23.38.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Aug 2026 23:38:06 -0700 (PDT) From: Varadarajan Narayanan Date: Mon, 24 Aug 2026 12:07:43 +0530 Subject: [PATCH 3/5] phy: qcom: qmp-usb: Add IPQ9650 USB3 PHY configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260824-phy-v1-3-257d68a3210b@oss.qualcomm.com> References: <20260824-phy-v1-0-257d68a3210b@oss.qualcomm.com> In-Reply-To: <20260824-phy-v1-0-257d68a3210b@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI0MDA1NyBTYWx0ZWRfXxzvuRDG/TlVm SvCT6urWjw/hoQmlJaGm7zKGxBhZvXKGY93SX5kM4HEBPGGUjuP5rr98tIULk2JE1cGYdFMBkM/ ie+j1NEp4BZJnYeyp9AbRYbQjbFSeQU= X-Proofpoint-GUID: lEN8l8jVu9ohPON2C4GhPA4MEJkYlcrc X-Authority-Analysis: v=2.4 cv=fqXsol4f c=1 sm=1 tr=0 ts=6a8be6d0 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=1pfUWIqQpZhN5ooAS-4A:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI0MDA1NyBTYWx0ZWRfX9CSSKv9jV8bQ c18mKRw5Awq3nPmMUVjkOxT3U5U0SDRebvHtek5bkj2iOuVxqKrrQs8MXlLrSR9bKe1K3ecw63U nznxZsJDz3gVozDEsHyEBeKT8XPenj/K1Eg5gJfmxueD/ohky4AxhT3ubvVZduEJ82JRsDufsfN 41MGTh1DwyCES40ulWwVhVacxy8xr0hUeZbe4WZsR2d3yZ9/t21PghOokhoFUQaCc9g9tYDog1D in1F6fM+dsxq/Yr0bhEWaIqyEa/BWoOYup19kevNBZRcWjneNqgawjXNIu55A8t57ie2dPDNMbn k2/ZvsqbLmEG+nSVUwz4reFKCQoSw5E0luNEKxcbZ6um2m85sTp+2wJ/HCUywbIp+jFM8Bug+wK rCvPSv49rmN83Fi/5GKAZtLfVThQYhgiuYejqy7OVeDX0LxfbnwCHLoT9ZzUm+GcKuXywE+sZ4f cwY1UQFfhuoieNM0pyg== X-Proofpoint-ORIG-GUID: lEN8l8jVu9ohPON2C4GhPA4MEJkYlcrc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-24_02,2026-08-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 impostorscore=0 phishscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608240057 Add the USB3 QMP PHY configuration for IPQ9650, including the SoC-specific init tables and compatible data. IPQ9650 uses settings that do not match any existing supported SoC, so add a dedicated configuration to allow the driver to support it. Signed-off-by: Varadarajan Narayanan --- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 118 ++++++++++++++++++++++++++++= ++++ 1 file changed, 118 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm= /phy-qcom-qmp-usb.c index b0790bcf0bc8..e772e1fa27cf 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -400,6 +400,101 @@ static const struct qmp_phy_init_tbl ipq8074_usb3_pcs= _tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), }; =20 +static const struct qmp_phy_init_tbl ipq9650_usb3_serdes_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x7d), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xd4), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x68), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xa2), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x01), +}; + +static const struct qmp_phy_init_tbl ipq9650_usb3_tx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xb5), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x00), +}; + +static const struct qmp_phy_init_tbl ipq9650_usb3_rx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe4), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x64), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xf6), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x89), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x35), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), +}; + +static const struct qmp_phy_init_tbl ipq9650_usb3_pcs_tbl[] =3D { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x03), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x02), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x09), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0xa2), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40), +}; + +static const struct qmp_phy_init_tbl ipq9650_usb3_pcs_usb_tbl[] =3D { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), +}; + static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_EN_SEL, 0x14), QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x08), @@ -1596,6 +1691,26 @@ static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = =3D { .regs =3D qmp_v3_usb3phy_regs_layout, }; =20 +static const struct qmp_phy_cfg ipq9650_usb3phy_cfg =3D { + .offsets =3D &qmp_usb_offsets_v4, + + .serdes_tbl =3D ipq9650_usb3_serdes_tbl, + .serdes_tbl_num =3D ARRAY_SIZE(ipq9650_usb3_serdes_tbl), + .tx_tbl =3D ipq9650_usb3_tx_tbl, + .tx_tbl_num =3D ARRAY_SIZE(ipq9650_usb3_tx_tbl), + .rx_tbl =3D ipq9650_usb3_rx_tbl, + .rx_tbl_num =3D ARRAY_SIZE(ipq9650_usb3_rx_tbl), + .pcs_tbl =3D ipq9650_usb3_pcs_tbl, + .pcs_tbl_num =3D ARRAY_SIZE(ipq9650_usb3_pcs_tbl), + .pcs_usb_tbl =3D ipq9650_usb3_pcs_usb_tbl, + .pcs_usb_tbl_num =3D ARRAY_SIZE(ipq9650_usb3_pcs_usb_tbl), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .regs =3D qmp_v4_usb3phy_regs_layout, + + .has_pwrdn_delay =3D true, +}; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-141861732f8sm21667830c88.10.2026.08.23.23.38.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Aug 2026 23:38:11 -0700 (PDT) From: Varadarajan Narayanan Date: Mon, 24 Aug 2026 12:07:44 +0530 Subject: [PATCH 4/5] phy: qcom: snps-femto-v2: Move PHY init registers to config tables Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260824-phy-v1-4-257d68a3210b@oss.qualcomm.com> References: <20260824-phy-v1-0-257d68a3210b@oss.qualcomm.com> In-Reply-To: <20260824-phy-v1-0-257d68a3210b@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan X-Mailer: b4 0.14.3 X-Authority-Analysis: v=2.4 cv=DsJmPm/+ c=1 sm=1 tr=0 ts=6a8be6d4 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=zXcBnA3yxj2v5e4wiOoA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-GUID: oP-7e8MiZqoGaIrU1lrwLGhohM1G5_qf X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI0MDA1NyBTYWx0ZWRfXwJ1NJWreoOWm GBzCm20NFGoilRbMGD0VhW9ELB2hJvAILUeC7vdwZ+hRHRwuNYVsY0UdUf7ZNrnd54MAlxIx+cp pYM92iejKHhd+sNFS7p+rCt5uQlu9xsFNRQdZ9vJens3wSU8NGXfbtVUbV17HNX8krrx/nbIpCl yWpc3jaz3f9iW0UImxwH4TSP2e59BRaF5easBDSxiZhIfV31atDHzpec9e2W9JCoje+Kkl+Tlfu GSeLBOyXSJNcj6iRAhqVAWX0SrGVwzFqFBIdNjnzcmt3zXwPjS9L4PPWfQHJcbl8J3lSm6I0prs bwICCrtEYbpiGdIY5otgoKLMSxxVGCLUjX7XdeL+25N7oJAII2I1TBoNm5VReR7gWVS00utv+Pi 2YVRgI4POKJpZgQJpqZUjBJuOWwc/bvUJO0+4c/k9AjGNCY8t8SwRE8FSnyXlDQGtt1KkJVKMXx 4aGnEP08Xc21//Ej/lA== X-Proofpoint-ORIG-GUID: oP-7e8MiZqoGaIrU1lrwLGhohM1G5_qf X-Proofpoint-Spam-Info: AW1haW4tMjYwODI0MDA1NyBTYWx0ZWRfXx251VhvONREL JYEmmpeTmZiHgrxnbyeKn9I0wBizhwAHpphNljGepZt6hMzisDjZ5B6MMIrQErFGOIeq8yhZAgX Y01ySmVewtlvVgZKYtfK/xQr3gX8PBU= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-24_02,2026-08-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 clxscore=1015 adultscore=0 suspectscore=0 malwarescore=0 bulkscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608240057 The driver currently programs the common PHY register sequence directly in qcom_snps_hsphy_init(), with the fixed register writes split around the override parameter handling. This makes it hard to support SoCs that need a different sequence or different values. Move the fixed pre- and post-override register programming into per- compatible configuration tables, and keep the 7 nm override parameters in the same match-data structure. This allows the driver to share the common sequence while adding SoC-specific sequences for future platforms such as IPQ9650. Signed-off-by: Varadarajan Narayanan --- drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 120 ++++++++++++++++------= ---- 1 file changed, 74 insertions(+), 46 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c b/drivers/phy/qu= alcomm/phy-qcom-snps-femto-v2.c index 980ad1fb1e2e..5ffbe1a77dd4 100644 --- a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c +++ b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c @@ -104,6 +104,18 @@ struct phy_override_seq { u8 mask; }; =20 +struct phy_reg_config { + u32 offset; + u32 mask; + u32 val; +}; + +struct phy_config_data { + const struct phy_reg_config *pre; + const struct override_param_map *override; + const struct phy_reg_config *post; +}; + #define NUM_HSPHY_TUNING_PARAMS (9) =20 /** @@ -383,13 +395,42 @@ static const struct override_param_map sc7280_snps_7n= m_phy[] =3D { {}, }; =20 +static const struct phy_reg_config hs_5nm_phy_pre[] =3D { + { USB2_PHY_USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, UTMI_PHY_CMN_CTRL= _OVERRIDE_EN }, + { USB2_PHY_USB_PHY_UTMI_CTRL5, POR, POR }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, FSEL_MASK, 0 }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, PLLBTUNE, PLLBTUNE }, + { USB2_PHY_USB_PHY_REFCLK_CTRL, REFCLK_SEL_DEFAULT, REFCLK_SEL_MASK }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, VBUSVLDEXTSEL0, VBUSVLDEXTSEL0 }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL1, VBUSVLDEXT0, VBUSVLDEXT0 }, + { UINT_MAX, 0, 0 }, +}; + +static const struct phy_reg_config hs_5nm_phy_post[] =3D { + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2, VREGBYPASS, VREGBYPASS }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N }, + { USB2_PHY_USB_PHY_UTMI_CTRL0, SLEEPM, SLEEPM }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, SIDDQ, 0 }, + { USB2_PHY_USB_PHY_UTMI_CTRL5, POR, 0 }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL, 0 }, + { USB2_PHY_USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0 }, + { UINT_MAX, 0, 0 }, +}; + static int qcom_snps_hsphy_init(struct phy *phy) { struct qcom_snps_hsphy *hsphy =3D phy_get_drvdata(phy); + const struct phy_config_data *data; + const struct phy_reg_config *tmp; int ret, i; =20 dev_vdbg(&phy->dev, "%s(): Initializing SNPS HS phy\n", __func__); =20 + data =3D of_device_get_match_data(hsphy->dev); + if (!data) + return -ENODEV; + ret =3D regulator_bulk_enable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs); if (ret) return ret; @@ -414,24 +455,8 @@ static int qcom_snps_hsphy_init(struct phy *phy) goto disable_clks; } =20 - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0, - UTMI_PHY_CMN_CTRL_OVERRIDE_EN, - UTMI_PHY_CMN_CTRL_OVERRIDE_EN); - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5, - POR, POR); - qcom_snps_hsphy_write_mask(hsphy->base, - USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, - FSEL_MASK, 0); - qcom_snps_hsphy_write_mask(hsphy->base, - USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, - PLLBTUNE, PLLBTUNE); - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_REFCLK_CTRL, - REFCLK_SEL_DEFAULT, REFCLK_SEL_MASK); - qcom_snps_hsphy_write_mask(hsphy->base, - USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, - VBUSVLDEXTSEL0, VBUSVLDEXTSEL0); - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1, - VBUSVLDEXT0, VBUSVLDEXT0); + for (tmp =3D data->pre; tmp->offset !=3D UINT_MAX; tmp++) + qcom_snps_hsphy_write_mask(hsphy->base, tmp->offset, tmp->mask, tmp->val= ); =20 for (i =3D 0; i < ARRAY_SIZE(hsphy->update_seq_cfg); i++) { if (hsphy->update_seq_cfg[i].need_update) @@ -441,28 +466,8 @@ static int qcom_snps_hsphy_init(struct phy *phy) hsphy->update_seq_cfg[i].value); } =20 - qcom_snps_hsphy_write_mask(hsphy->base, - USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2, - VREGBYPASS, VREGBYPASS); - - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, - USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, - USB2_SUSPEND_N_SEL | USB2_SUSPEND_N); - - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL0, - SLEEPM, SLEEPM); - - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMM= ON0, - SIDDQ, 0); - - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5, - POR, 0); - - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, - USB2_SUSPEND_N_SEL, 0); - - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0, - UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0); + for (tmp =3D data->post; tmp->offset !=3D UINT_MAX; tmp++) + qcom_snps_hsphy_write_mask(hsphy->base, tmp->offset, tmp->mask, tmp->val= ); =20 hsphy->phy_initialized =3D true; =20 @@ -495,14 +500,34 @@ static const struct phy_ops qcom_snps_hsphy_gen_ops = =3D { .owner =3D THIS_MODULE, }; =20 +static const struct phy_config_data hs_5nm_phy =3D { + .pre =3D hs_5nm_phy_pre, + .post =3D hs_5nm_phy_post, +}; + +static const struct phy_config_data hs_7nm_phy =3D { + .pre =3D hs_5nm_phy_pre, + .override =3D sc7280_snps_7nm_phy, + .post =3D hs_5nm_phy_post, +}; + static const struct of_device_id qcom_snps_hsphy_of_match_table[] =3D { - { .compatible =3D "qcom,sm8150-usb-hs-phy", }, - { .compatible =3D "qcom,usb-snps-hs-5nm-phy", }, + { + .compatible =3D "qcom,sm8150-usb-hs-phy", + .data =3D &hs_5nm_phy, + }, + { + .compatible =3D "qcom,usb-snps-hs-5nm-phy", + .data =3D &hs_5nm_phy, + }, { .compatible =3D "qcom,usb-snps-hs-7nm-phy", - .data =3D &sc7280_snps_7nm_phy, + .data =3D &hs_7nm_phy, + }, + { + .compatible =3D "qcom,usb-snps-femto-v2-phy", + .data =3D &hs_5nm_phy, }, - { .compatible =3D "qcom,usb-snps-femto-v2-phy", }, { } }; MODULE_DEVICE_TABLE(of, qcom_snps_hsphy_of_match_table); @@ -541,11 +566,14 @@ static void qcom_snps_hsphy_read_override_param_seq(s= truct device *dev) s32 val; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-141861732f8sm21667830c88.10.2026.08.23.23.38.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Aug 2026 23:38:15 -0700 (PDT) From: Varadarajan Narayanan Date: Mon, 24 Aug 2026 12:07:45 +0530 Subject: [PATCH 5/5] phy: qcom: snps-femto-v2: Add IPQ9650 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260824-phy-v1-5-257d68a3210b@oss.qualcomm.com> References: <20260824-phy-v1-0-257d68a3210b@oss.qualcomm.com> In-Reply-To: <20260824-phy-v1-0-257d68a3210b@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI0MDA1NyBTYWx0ZWRfXwkz26rT4YMi+ GGawT2cJ1EjjXgt0Lb69rrdydyhQk9tOMO6yCx7CzxRU2QOnl9yNVccZX7eq6XJjfWrlNuGC5bS 7jNC6t51cEPVF5LLxtiY8Kze0ByzbfKaHJrZZAmKHUdU1hkCORI/uijA6yFX39kjap4gx41/CKu 3YNWxU+AHvUxWjdcVkL8k5AnOqYfez94qK+tl1/g93KeS2WOpnH7V5zSOz9UgIO0X8w4IYJcgfc RZHqo5sdVX/CxodM7Op/dP4OOZA96zDlSJpimS/KdTmSt+Gfq9f3OYXemRPOvVDnLA84IGCUOr2 hWuBwSiPmYhOk6TdJUKC0mNXh5CG8lcjj9fNJNSSoL9Ibu+qNFqsHAb83t8JtVdpgSp/du5eOqG ncWE9kcKeLfC2O2coqbf2if8jwgVQg9J5JJBUhUXOouL8nImw30UFecd4GQOqnpLPXJVzCM5Onx g2sDtb8Z20fr73viW2A== X-Proofpoint-GUID: 90xm93wo4lsm79N5sTMYoApQhkaPQCPa X-Proofpoint-Spam-Info: AW1haW4tMjYwODI0MDA1NyBTYWx0ZWRfXyKSW2uMbn/9g +mf/3IzCzqNC9W7r0nRuh5DX2jKB1B3OMRn7NmzKgx+CZvu0u1v4qszHd//+yTDfw+BZTI12ZQf s5AXnnobuKQiCsGU6NyAX1BOi7Q9fpQ= X-Authority-Analysis: v=2.4 cv=Xey5Co55 c=1 sm=1 tr=0 ts=6a8be6d9 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=Q9t0gmS3rCGuRMBXcNQA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-ORIG-GUID: 90xm93wo4lsm79N5sTMYoApQhkaPQCPa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-24_02,2026-08-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 clxscore=1015 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608240057 Add the 6 nm SNPS femto USB2 PHY configuration needed by IPQ9650. The PHYs on this SoC require a dedicated init sequence and override parameters before they can be enabled. Signed-off-by: Varadarajan Narayanan --- drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 62 +++++++++++++++++++++++= ++++ 1 file changed, 62 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c b/drivers/phy/qu= alcomm/phy-qcom-snps-femto-v2.c index 5ffbe1a77dd4..c18171f9464b 100644 --- a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c +++ b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c @@ -29,12 +29,15 @@ =20 #define USB2_PHY_USB_PHY_UTMI_CTRL5 (0x50) #define POR BIT(1) +#define ATERESET BIT(0) =20 #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) #define SIDDQ BIT(2) #define RETENABLEN BIT(3) #define FSEL_MASK GENMASK(6, 4) #define FSEL_DEFAULT (0x3 << 4) +#define FSEL_24MHZ (0x2 << 4) +#define VATESTENB_MASK GENMASK(1, 0) =20 #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58) #define VBUSVLDEXTSEL0 BIT(4) @@ -57,6 +60,13 @@ #define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X3 (0x78) #define PARAM_OVRD_MASK 0xFF =20 +#define USB2_PHY_USB_PHY_HS_PHY_TEST0 0x80 +#define TESTDATAIN_MASK GENMASK(7, 0) + +#define USB2_PHY_USB_PHY_HS_PHY_TEST1 0x84 +#define TESTDATAOUTSEL BIT(4) +#define TESTCLK BIT(6) + #define USB2_PHY_USB_PHY_CFG0 (0x94) #define UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN BIT(0) #define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1) @@ -78,6 +88,9 @@ =20 #define LS_FS_OUTPUT_IMPEDANCE_MASK GENMASK(3, 0) =20 +#define USB2_PHY_USB_PHY_FSEL_SEL 0xb8 +#define FSEL_SEL BIT(0) + static const char * const qcom_snps_hsphy_vreg_names[] =3D { "vdda-pll", "vdda33", "vdda18", }; @@ -328,6 +341,17 @@ static const struct override_param ls_fs_output_impeda= nce_sc7280[] =3D { { 1310, 0 }, }; =20 +static const struct override_param_map ipq9650_snps_6nm_phy[] =3D { + { + "qcom,pre-emphasis-amplitude-bp", + preemphasis_amplitude_sc7280, + ARRAY_SIZE(preemphasis_amplitude_sc7280), + USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1, + PREEMPHASIS_AMPLITUDE_MASK, + }, + {}, +}; + static const struct override_param_map sc7280_snps_7nm_phy[] =3D { { "qcom,hs-disconnect-bp", @@ -418,6 +442,34 @@ static const struct phy_reg_config hs_5nm_phy_post[] = =3D { { UINT_MAX, 0, 0 }, }; =20 +static const struct phy_reg_config hs_6nm_phy_pre[] =3D { + { USB2_PHY_USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, UTMI_PHY_CMN_CTRL= _OVERRIDE_EN }, + { USB2_PHY_USB_PHY_UTMI_CTRL5, POR, POR }, + { USB2_PHY_USB_PHY_FSEL_SEL, FSEL_SEL, FSEL_SEL }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, FSEL_MASK, FSEL_24MHZ }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, PLLBTUNE, PLLBTUNE }, + { USB2_PHY_USB_PHY_REFCLK_CTRL, REFCLK_SEL_MASK, REFCLK_SEL_DEFAULT }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, VBUSVLDEXTSEL0, VBUSVLDEXTSEL0 }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL1, VBUSVLDEXT0, VBUSVLDEXT0 }, + { UINT_MAX, 0, 0 }, +}; + +static const struct phy_reg_config hs_6nm_phy_post[] =3D { + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2, VREGBYPASS, VREGBYPASS }, + { USB2_PHY_USB_PHY_UTMI_CTRL5, ATERESET, 0 }, + { USB2_PHY_USB_PHY_HS_PHY_TEST1, TESTDATAOUTSEL, 0 }, + { USB2_PHY_USB_PHY_HS_PHY_TEST1, TESTCLK, 0 }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, VATESTENB_MASK, 0 }, + { USB2_PHY_USB_PHY_HS_PHY_TEST0, TESTDATAIN_MASK, 0 }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N }, + { USB2_PHY_USB_PHY_UTMI_CTRL0, SLEEPM, SLEEPM }, + { USB2_PHY_USB_PHY_UTMI_CTRL5, POR, 0 }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL, 0 }, + { USB2_PHY_USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0 }, + { UINT_MAX, 0, 0 }, +}; + static int qcom_snps_hsphy_init(struct phy *phy) { struct qcom_snps_hsphy *hsphy =3D phy_get_drvdata(phy); @@ -505,6 +557,12 @@ static const struct phy_config_data hs_5nm_phy =3D { .post =3D hs_5nm_phy_post, }; =20 +static const struct phy_config_data hs_6nm_phy =3D { + .pre =3D hs_6nm_phy_pre, + .override =3D ipq9650_snps_6nm_phy, + .post =3D hs_6nm_phy_post, +}; + static const struct phy_config_data hs_7nm_phy =3D { .pre =3D hs_5nm_phy_pre, .override =3D sc7280_snps_7nm_phy, @@ -520,6 +578,10 @@ static const struct of_device_id qcom_snps_hsphy_of_ma= tch_table[] =3D { .compatible =3D "qcom,usb-snps-hs-5nm-phy", .data =3D &hs_5nm_phy, }, + { + .compatible =3D "qcom,usb-snps-hs-6nm-phy", + .data =3D &hs_6nm_phy, + }, { .compatible =3D "qcom,usb-snps-hs-7nm-phy", .data =3D &hs_7nm_phy, --=20 2.34.1