From nobody Mon Sep 28 08:08:30 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED3A9391842; Mon, 24 Aug 2026 21:25:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787606750; cv=none; b=iI0PPl3pcccptpb4ql+x2vdNLzkIHlLiW/OtSSTqlwjBGHea0b0s5Fsxfob+wbRFx0l9wbjtxWlELAIDY0LU7QLrWbMQfCSx31Q9nDs7FX64jqTvS9Ud6QZDV3GTeUVOTj//p6nw7R8Go83nOW8K0IGlbyOjutbiHgWdkLZw3ZQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787606750; c=relaxed/simple; bh=MtrNk79y9UlhhIe4pbAdt5QRKJ67Z3i4LU97ujPXueM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=p2R88cn4o3Be8q95kVULvNpZ5uUI5OrBmaZP0GKIytfg8lIDyqHYquD4lHR8ED7by+4HTGoB6QvFRm7Zp/zg0u3BxzCyeCRoQ4pkyH/ZWg3ZNWuIUQUgAtmRkFlAsEw6/HJPjGxxtDsubz0n32/Y/yNZ00b/lpVzfe0MB0ckdTc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=LV1VGOuK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LV1VGOuK" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7D331C2BCF4; Mon, 24 Aug 2026 21:25:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787606749; bh=MtrNk79y9UlhhIe4pbAdt5QRKJ67Z3i4LU97ujPXueM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=LV1VGOuKH6vtbfL6sKT2y++7zjUIto9i952tLgrMaBj3pdijOa9gc7Dq8YJ4+d0h6 QQc2YP1OyOMJpDiZZGqUY8O3kUY0SB4n1ZHf+YG/I1ROurlJm/88Jj9xRhe3YG87vy EaqxNR5w7TUuaJAxFtLRjm7VGBPD6KEug7IhD0XtdminlLj3R/mOwNTxXxOfErwjWD 0Y/eNq7wi8qXZWub+0f+kbM3rphMeGhSS3YFkbe5CP8f9uz65k7fVRwmYnE2xih68v 31YEa5j9J6Y3Y2lFMNbCJMNThtU93YHZEuDrm3Gyfr2aCSneZbXT/yC9mONnuhzIX7 QiXEm7wc/rliw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C956C5DF9C; Mon, 24 Aug 2026 21:25:49 +0000 (UTC) From: Vincent Jardin via B4 Relay Date: Mon, 24 Aug 2026 23:25:29 +0200 Subject: [PATCH v3 1/3] arm64: dts: lx2160a: fix incorrect pinmux Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260824-for-upstream-lx2160a-pinmux-fix-v3-1-5556ff1e6be2@free.fr> References: <20260824-for-upstream-lx2160a-pinmux-fix-v3-0-5556ff1e6be2@free.fr> In-Reply-To: <20260824-for-upstream-lx2160a-pinmux-fix-v3-0-5556ff1e6be2@free.fr> To: Frank Li , Carlos Song , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Josua Mayer Cc: imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thibaut Collet , Vincent Jardin X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787606747; l=1674; i=vjardin@free.fr; s=20260525; h=from:subject:message-id; bh=tk7MyEzbkFZ9falPdlkYVsr2TClhONYWQaNZkpaH8F4=; b=sGMzLO+RIZh/oxKRvZgGXdsZ95+HjPTv+ykAhYxa76E4oapS1VBZ/VzyRGoiUEqngmIjPT6+f 99nZ4asHgAFB3p79gFJdvAGg6a1GsHqf76xMANmZqfx2eipXYrOoN7d X-Developer-Key: i=vjardin@free.fr; a=ed25519; pk=hppgLeFpGpKOi7LNwGEZ4jOYofJCoGd4Jf1ltAabiLw= X-Endpoint-Received: by B4 Relay for vjardin@free.fr/20260525 with auth_id=871 X-Original-From: Vincent Jardin Reply-To: vjardin@free.fr From: Vincent Jardin For gpio1 value set for pinctrl is outside the mask and so will do nothing. Add the missing offset for value field to be the same as the mask as expected. Fixes: 284ad7064aaa ("arm64: dts: lx2160a: complete pinmux for rcwsr12 conf= iguration word") Suggested-by: Thibaut Collet Reviewed-by: Josua Mayer Signed-off-by: Vincent Jardin --- arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi b/arch/arm64/boo= t/dts/freescale/fsl-lx216x.dtsi index ae6e37870c5e5..d4522a19405a9 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi @@ -1622,7 +1622,7 @@ fspi_data74_pins: xspi1-data74-pins { }; =20 gpio1_31_28_pins: xspi1-data74-gpio-pins { - pinctrl-single,bits =3D <0x0 0x1 (0x7 << 15)>; + pinctrl-single,bits =3D <0x0 (0x1 << 15) (0x7 << 15)>; }; =20 fspi_data30_pins: xspi1-data30-pins { @@ -1630,7 +1630,7 @@ fspi_data30_pins: xspi1-data30-pins { }; =20 gpio1_27_24_pins: xspi1-data30-gpio-pins { - pinctrl-single,bits =3D <0x0 0x1 (0x7 << 18)>; + pinctrl-single,bits =3D <0x0 (0x1 << 18) (0x7 << 18)>; }; =20 fspi_dqs_sck_cs10_pins: xspi1-base-pins { @@ -1638,7 +1638,7 @@ fspi_dqs_sck_cs10_pins: xspi1-base-pins { }; =20 gpio1_23_20_pins: xspi1-base-gpio-pins { - pinctrl-single,bits =3D <0x0 0x1 (0x7 << 21)>; + pinctrl-single,bits =3D <0x0 (0x1 << 21) (0x7 << 21)>; }; =20 esdhc0_cmd_data30_clk_vsel_pins: sdhc1-base-sdhc-vsel-pins { --=20 2.43.0 From nobody Mon Sep 28 08:08:30 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED31A391838; Mon, 24 Aug 2026 21:25:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787606750; cv=none; b=iUUoy9Uw+cLXo1Yt1pJWU1vYsL4yY6uTJg5ERaRoaL+RB3oTSTu80Uu60Ytjx3B/OAbpW1Ws+5yfwoUGZwkTSQQYret3ik4sNEeS22om+SgxZiN/fvCjHBByjl/o0V0TB1wwNeuUaL5eBfKjUEROz9misbbJ5pjiD/XAQfqiciE= ARC-Message-Signature: i=1; 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b=hv4JTlTMqyypWurdRVveg7buJvBnPVBxCqLMdFBUmNd5uIGkvG7EsMRfR0K34coBX he0IgTdpQY0aF+dqn0qXd61U1i39A+Svsq7a0XRoIZVnqyphSrGJ1HiNuz9h3C+WqJ Sby310uB1wFdItA647iGyr2XQ/mx/mem6h9bUO/Bqx8Rc3aCTcMq8Wz1+FahQwBkb3 vO1yFmb9asaXRrA3EaC8cxFx3TazL5umzboWrkZrK989WLyf61gMNA/GNEnEcyEE5G cqrvA6mVb6OpGlWAy1gzngbT2b6SKa2LBecbLwRWzbRrVf3WMz1XsuHWnctvlckQKN r1ol0I3RpCobw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C744C5DF9D; Mon, 24 Aug 2026 21:25:49 +0000 (UTC) From: Vincent Jardin via B4 Relay Date: Mon, 24 Aug 2026 23:25:30 +0200 Subject: [PATCH v3 2/3] arm64: dts: lx2160a: fix IIC1 pinmux submask rejected by pinctrl-single Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260824-for-upstream-lx2160a-pinmux-fix-v3-2-5556ff1e6be2@free.fr> References: <20260824-for-upstream-lx2160a-pinmux-fix-v3-0-5556ff1e6be2@free.fr> In-Reply-To: <20260824-for-upstream-lx2160a-pinmux-fix-v3-0-5556ff1e6be2@free.fr> To: Frank Li , Carlos Song , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Josua Mayer Cc: imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thibaut Collet , Vincent Jardin X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787606747; l=2317; i=vjardin@free.fr; s=20260525; h=from:subject:message-id; bh=RQSuv7sNb6qL2mxWfOmjTQhD0J0pZv301ma7dFDHaYg=; b=XH70Jv+EGNq2fIoIIIFRPNR518p0v4eNgaPII/lj8Wzxu7EH6ZmAKsUt3+o/d4lrI2zd6Jon0 fuknEF48DZZBbMsiQgWozBQ3ZVJd75e12SBy2VIMDjW8CPqw8f64Z6v X-Developer-Key: i=vjardin@free.fr; a=ed25519; pk=hppgLeFpGpKOi7LNwGEZ4jOYofJCoGd4Jf1ltAabiLw= X-Endpoint-Received: by B4 Relay for vjardin@free.fr/20260525 with auth_id=871 X-Original-From: Vincent Jardin Reply-To: vjardin@free.fr From: Vincent Jardin IIC1_PMUX is a single bit field at RCWSR14 bit 10, so the mask for the two iic1 pinmux nodes was narrowed from 0x7 to 0x1 to avoid writing the two reserved bits next to it. With pinctrl-single,bit-per-mux the driver does not take the supplied mask as the bits to modify. It derives the field from the node's pinctrl-single,function-mask, which is 0x7 here, and then requires the supplied mask to match it exactly: bit_pos =3D __ffs(mask); /* 10 */ mask_pos =3D ((pcs->fmask) << bit_pos); /* 0x7 << 10 =3D 0x1c00 */ submask =3D mask & mask_pos; /* 0x400 */ ... if (submask !=3D mask_pos) { dev_warn(pcs->dev, "Invalid submask 0x%x for %pOFn at 0x%x\n", submask, np, offset); continue; } A one bit mask gives submask 0x400 against mask_pos 0x1c00, so both nodes are rejected and the pins are never muxed with this message: pinctrl-single 70010012c.pinmux: Invalid submask 0x400 for iic1-i2c-pins pinctrl-single 70010012c.pinmux: Invalid submask 0x400 for iic1-gpio-pins The values are not changed: - 0x0 selects IIC1 - 0x1 << 10 selects GPIO_1[3:2]. Fixes: 7a3cc49ad1fc ("arm64: dts: lx2160a: change i2c0 (iic1) pinmux mask t= o one bit") Signed-off-by: Vincent Jardin --- arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi b/arch/arm64/boo= t/dts/freescale/fsl-lx216x.dtsi index d4522a19405a9..d9d4500a40510 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi @@ -1687,12 +1687,19 @@ i2c6_i2c7_pins: iic8-iic7-i2c-pins { }; =20 /* RCWSR14 */ + /* + * IIC1_PMUX is a single bit at RCWSR14[10], but bit-per-mux + * uses the mask for the field to clear before applying the + * value. + * So bits 11 and 12, which are reserved, are written as 0 + * on every mux switch, it is harmless. + */ i2c0_pins: iic1-i2c-pins { - pinctrl-single,bits =3D <0x8 0x0 (0x1 << 10)>; + pinctrl-single,bits =3D <0x8 0x0 (0x7 << 10)>; }; =20 gpio0_3_2_pins: iic1-gpio-pins { - pinctrl-single,bits =3D <0x8 (0x1 << 10) (0x1 << 10)>; + pinctrl-single,bits =3D <0x8 (0x1 << 10) (0x7 << 10)>; }; }; =20 --=20 2.43.0 From nobody Mon Sep 28 08:08:30 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED26A391835; Mon, 24 Aug 2026 21:25:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787606750; cv=none; b=Yfr5ycqMOb4Z9efIV84Vsw9gPrFZzh5ZSBi62h3N5c74Bw3TAP62gcN9lK2yCtZa71It32hwhxNpfMVP3jv4QzOuSv1+UkgaGhe2mw+f80cEV4lugZvmPn5swO9GAko43KpxSNE/D1wTgv6yLAG5iKNxe/HHJ36AFWppl/EFnig= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787606750; c=relaxed/simple; bh=7/5axdhQNXuY4I+yRWh2TmDa+ZyuwP/SOiSz4/cxhM4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sh0WrBcwIs5P3Q4oZ+6mJkTI+V8AxkteI/CLpQL8P/MD2WtbADw+jrG3+3nh3JSB4jU2ApKqGNLg4mXNA5FWnX/Tcc8Hp2K/Njsy14mZ3/LKdnou3o6DjchVFnU8KAONy6pPa96cZKlYoXiVD8XVntWBkEr4Yej091BdKq+cUec= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kZhy8Die; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kZhy8Die" Received: by smtp.kernel.org (Postfix) with ESMTPS id 9ABF8C2BCFB; Mon, 24 Aug 2026 21:25:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787606749; bh=7/5axdhQNXuY4I+yRWh2TmDa+ZyuwP/SOiSz4/cxhM4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=kZhy8DieTbw+ALnGykhI3m4qhio2noa/k4KS7zOU++MwKqhTBzE2cSqBpttHlJXPf Xp2vm2YXyBV5wMYD2TBUjTyB83tzoBDsMZu1J/yqjT+6TpvLYwwHU/+EE38tHEb/0Q vPsumbmv2/VB85EGWBhbwofwS/e35AY8xaP5XrDmoFn3f42mSRqGz64mHXvnZOP6+l UqhRBl4uD+sLTyG5CG6GN21mjhXsYZkECfuRhBTR/TShx125je/E2gNKQp1JjSbk+V XJccXhxA07Qe87wwD8rBVi1QyLWUqvWo9khsZl5xhbokc7R2fnzm4dOVo3FffdJgKZ bUaCiY6XJ78FA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CAD0C5DF81; Mon, 24 Aug 2026 21:25:49 +0000 (UTC) From: Vincent Jardin via B4 Relay Date: Mon, 24 Aug 2026 23:25:31 +0200 Subject: [PATCH v3 3/3] arm64: dts: lx2160a: fix the iic5 spi3 pinmux offset and value Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260824-for-upstream-lx2160a-pinmux-fix-v3-3-5556ff1e6be2@free.fr> References: <20260824-for-upstream-lx2160a-pinmux-fix-v3-0-5556ff1e6be2@free.fr> In-Reply-To: <20260824-for-upstream-lx2160a-pinmux-fix-v3-0-5556ff1e6be2@free.fr> To: Frank Li , Carlos Song , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Josua Mayer Cc: imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thibaut Collet , Vincent Jardin X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787606747; l=1585; i=vjardin@free.fr; s=20260525; h=from:subject:message-id; bh=QDg/PMlX4cUoUaMiOfnzx35qrvv5wjRXmhdG/ya3lcg=; b=w/L0OfexC4Q+IyPr+msl2FmmJigxz+valXAqzNpFZL1/w+8IKFjamnyUEiKTnalyeYRtJY5Jg YiehfGbb1fQC5+jpWIw0wSCtOeSE7OA1OvUKoeIUiXWkROC8xu0EzTq X-Developer-Key: i=vjardin@free.fr; a=ed25519; pk=hppgLeFpGpKOi7LNwGEZ4jOYofJCoGd4Jf1ltAabiLw= X-Endpoint-Received: by B4 Relay for vjardin@free.fr/20260525 with auth_id=871 X-Original-From: Vincent Jardin Reply-To: vjardin@free.fr From: Vincent Jardin The iic5-spi3-pins node has both of its first two cells wrong. The offset selects the register within the node's reg range, where: 0x0 is RCWSR12, 0x4 is RCWSR13, 0x8 is RCWSR14. An offset of 0x3 is not one of them and is not even aligned for the declared 32 bit register width. It is the only node in this pinmux that does not use 0x0, 0x4 neither 0x8. The value is wrong too: IIC5_PMUX is RCWSR12[11:9] and it encodes 0b000 for IIC5, 0b001 for GPIO_1[25:24], 0b010 for SDHC1_CLK_SYNC_OUT/IN, 0b011 for {IIC5_SCL,IIC5_SDA} =3D {SPI3_SOUT,SPI3_SIN}. This node selects the last of those, so it needs 0x3, not the 0x2, which is the value of the neighbouring sdhc1 clock sync node it was copied from. Fixes: 284ad7064aaa ("arm64: dts: lx2160a: complete pinmux for rcwsr12 conf= iguration word") Reviewed-by: Josua Mayer Signed-off-by: Vincent Jardin --- arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi b/arch/arm64/boo= t/dts/freescale/fsl-lx216x.dtsi index d9d4500a40510..bccf2d6730230 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi @@ -1602,7 +1602,7 @@ esdhc0_clksync_pins: iic5-sdhc-clk-pins { }; =20 dspi2_miso_mosi_pins: iic5-spi3-pins { - pinctrl-single,bits =3D <0x3 (0x2 << 9) (0x7 << 9)>; + pinctrl-single,bits =3D <0x0 (0x3 << 9) (0x7 << 9)>; }; =20 i2c5_pins: iic6-i2c-pins { --=20 2.43.0