From nobody Mon Sep 28 10:47:24 2026 Received: from sender5-op-o15.zoho.com (sender5-op-o15.zoho.com [165.173.182.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A6793859E0 for ; Sat, 22 Aug 2026 22:20:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=165.173.182.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787437257; cv=pass; b=RCWkDIOLYC7BcXdIm0BqrULpKBF8IJ3IClQ2+r0edWJbXg+meX+jfnTUA/dEi7xSKqWPgARdjnOG17PJ+Kjmq9ezCrafTVCFE+61KjsYx3kXNxDvkTb1jkim9KHeT1YVIIDK+VF9jHvMzVUJvFmFCtbk/TqJYdgBH8gk8GRij6c= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787437257; c=relaxed/simple; bh=29ZY0ibdjcc/LypnZG343DWhzf5vuhUx8loLavzF0F8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=klzZgfWSEq1v3EYsLmUAeM2FvJwXgmXy9tCU7ChZxaowbMKpSiPPiJjqbsBb6742YkshwDb1FDQVt1vBcYOuS2F0ZH5njJBaz9Y2RuFwXkl1CfUPQeJqheGFQ3oLlpPBeJ9vJnHUxCjvUnYLjTOKk1CqyMMSxRphFpbdQXOtw+8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=rong.moe; spf=pass smtp.mailfrom=rong.moe; dkim=pass (2048-bit key) header.d=rong.moe header.i=i@rong.moe header.b=kmAI1E5C; arc=pass smtp.client-ip=165.173.182.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=rong.moe Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rong.moe Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rong.moe header.i=i@rong.moe header.b="kmAI1E5C" ARC-Seal: i=1; a=rsa-sha256; t=1787437234; cv=none; d=zohomail.com; s=zohoarc; b=R/COo5iHEg/753np8FR1Mzvrj5l6ZJv056jHg13eL3jqJ8uDVrz6cJBAhPnDR6crbfDnNNFmwQkV6BSuqWG7pLBnkyxVyZqnsLRQNgXQerv+HOj0LEy3jj5naBkOBnIHK2eUccrsGdg/+fy9h4OTJNB6Cz8IwoawmP9KrawvE0I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787437234; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:Subject:Subject:To:To:Message-Id:Reply-To; bh=pO7qKbXpDFi/GJZswEbXeFN6/0MHZtN04J3AAJYstBg=; b=K3EbjBWZIUsl4CBUdEMMEoPu/XwN95byXkwmRjy8JTVnyvFDBMGNa057puzoROJdCwQ4k7dbjS/vmAn3XCCjJc6EabN4xQPhluD0Xll16W+vPhQHLz2Dpe3DaWGjoWGHzSGE4VIiJs+gZ3wvmeOUxnnFhmOhVxUTuYJwRhCuT54= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=rong.moe; spf=pass smtp.mailfrom=i@rong.moe; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1787437234; s=zmail2048; d=rong.moe; i=i@rong.moe; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=pO7qKbXpDFi/GJZswEbXeFN6/0MHZtN04J3AAJYstBg=; b=kmAI1E5C44HahBru6LvBGaEVbwh+2pGjUA5TxUP4fNhi0nP3K0ZJThWyQKjSNHvp ShPdPgXw/PyvZOllNb008JLWWIhum02iicoFwAxXc1eOy9b6zL437U9jSKAqiwLKISf Ji91nR+mdRmtAddNsGOJ0dCnEH8WoPc4pB9o0gLlJebhTQFshNsdGIRZPg1yfqCw6qL h6jArh1ihvzPaBY2/cuUqWuvaJgkUUKgu2fczSStgiKpoUtKdCXq5IcYuM8srX0mIYE 8EqQc3AGPQbxe/bJmJn+iuyLAnueRltV3XIxLHg/bsduXhc8fGA/hs6bqZztghDi9b/ FDvAFvYBlw== Received: by mx.zohomail.com with SMTPS id 1787437233301359.360788980586; Sat, 22 Aug 2026 15:20:33 -0700 (PDT) From: Rong Zhang Date: Sun, 23 Aug 2026 06:20:15 +0800 Subject: [PATCH v3 1/3] iommu/amd: Do not request ACS when IOMMU is not going to be initialized Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260823-amd-iommu-fix-acs-v3-1-dd768e09d771@rong.moe> References: <20260823-amd-iommu-fix-acs-v3-0-dd768e09d771@rong.moe> In-Reply-To: <20260823-amd-iommu-fix-acs-v3-0-dd768e09d771@rong.moe> To: "Joerg Roedel (AMD)" , Suravee Suthikulpanit , Vasant Hegde , Will Deacon , Robin Murphy , Huang Rui Cc: Ankit Soni , Sairaj Kodilkar , iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Rong Zhang X-Mailer: b4 0.17-dev-1f2f7 X-ZohoMailClient: External The AMD IOMMU Initialization State Machine has the following state transition diagram (only the very first states are showed, and the `IOMMU_' prefix is omitted): START_STATE | v [0] detect_ivrs() --> NOT_FOUND | ok v IVRS_DETECTED | v [1] amd_iommu_disabled? (amd_iommu=3Doff) --> IOMMU_CMDLINE_DISABLED | no v [2] early_amd_iommu_init() | +-- [3] amd_iommu_detected? (!iommu=3Doff && ...) -+ | yes | +-- ... --> IOMMU_INIT_ERROR <-------------------+ | ok v IOMMU_ACPI_FINISHED | v ... [0] always calls pci_request_acs() as long as there's a valid IVRS table and no Stoney Ridge graphics. This is not optimal as ACS is not required in an [amd_]iommu=3Doff boot. In a normal boot, ACS is requested due to amd_iommu_detect() requesting IVRS_DETECTED. pci_request_acs+0x9/0x18 iommu_go_to_state+0x106/0x1a20 amd_iommu_detect+0x1c/0x50 pci_iommu_alloc+0x26/0x40 mm_core_init+0xa/0x120 start_kernel+0x527/0x7a0 x86_64_start_reservations+0x24/0x30 x86_64_start_kernel+0xd1/0xe0 common_startup_64+0x13e/0x158 This is intended to ensure ACS is requested before the PCI core initialization, or else a !CONFIG_IRQ_REMAP, nointremap or intremap=3Doff boot would be broken. However, in an amd_iommu=3Doff boot, the state machine still requests ACS at the exact same time, as amd_iommu_detect() has nothing to do with amd_iommu_disabled. Even worse, in an iommu=3Doff boot, though amd_iommu_detect() bails out early, ACS is still requested due to amd_iommu_prepare() requesting IOMMU_ACPI_FINISHED, which is called by irq_remapping_prepare() thanks to CONFIG_X86_LOCAL_APIC (always set on X86_64) and CONFIG_IRQ_REMAP (enabled by defconfig), unless nointremap or intremap=3Doff is also passed to cmdline. pci_request_acs+0x9/0x18 iommu_go_to_state+0x106/0x1a20 amd_iommu_prepare+0x15/0x40 irq_remapping_prepare+0x43/0x60 enable_IR_x2apic+0x22/0x190 x86_64_probe_apic+0xa/0x50 apic_intr_mode_init+0x70/0xd0 x86_late_time_init+0x28/0x40 start_kernel+0x6f9/0x7a0 ... In both cases, [2] is still gated due to the [1] or [3] check, so that IOMMU can be disabled per cmdline. Technically, it makes no sense to detect IVRS at all in an [amd_]iommu=3Doff boot or if IOMMU is not supported due to platform settings. This is probably why amd_iommu_detect() bails out before requesting IVRS_DETECTED. Apparently only bailing out there is not sufficient, and the bailing-out paths should really have been parts of the state machine. Clean up the initialization routines by moving the bailing-out paths and [1] to the right place in the state machine (i.e., before [0]), and always requesting IVRS_DETECTED in amd_iommu_detect() to initialize the state machine early and properly. Note that the condition (iommu_detected && !gart_iommu_aperture) is dropped as it's dead code since the relevant code being removed. It meant to detect what commit 6631ee9d0099 ("x86, AMD IOMMU: add dma_ops initialization function") had introduced, but commit d7f077697533 ("x86/amd-iommu: Fall back to GART if initialization fails") has removed it. Later, commit 78013eaadf69 ("x86: remove the IOMMU table infrastructure") ensured AMD IOMMU being detected before Intel's and led to iommu_detected =3D=3D gart_iommu_aperture in any case. Signed-off-by: Rong Zhang Reviewed-by: Ankit Soni --- drivers/iommu/amd/init.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 40726dfef273..0fd0801a873f 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -3470,6 +3470,8 @@ static void amd_iommu_apply_erratum_snp(void) #endif } =20 +static bool amd_iommu_sme_check(void); + /*************************************************************************= *** * * AMD IOMMU Initialization State Machine @@ -3482,7 +3484,13 @@ static int __init state_next(void) =20 switch (init_state) { case IOMMU_START_STATE: - if (!detect_ivrs()) { + if (no_iommu || amd_iommu_disabled) { + init_state =3D IOMMU_CMDLINE_DISABLED; + ret =3D -EINVAL; + } else if (!amd_iommu_sme_check()) { + init_state =3D IOMMU_INIT_ERROR; + ret =3D -EINVAL; + } else if (!detect_ivrs()) { init_state =3D IOMMU_NOT_FOUND; ret =3D -ENODEV; } else { @@ -3490,13 +3498,8 @@ static int __init state_next(void) } break; case IOMMU_IVRS_DETECTED: - if (amd_iommu_disabled) { - init_state =3D IOMMU_CMDLINE_DISABLED; - ret =3D -EINVAL; - } else { - ret =3D early_amd_iommu_init(); - init_state =3D ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED; - } + ret =3D early_amd_iommu_init(); + init_state =3D ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED; break; case IOMMU_ACPI_FINISHED: early_enable_iommus(); @@ -3695,12 +3698,6 @@ void __init amd_iommu_detect(void) { int ret; =20 - if (no_iommu || (iommu_detected && !gart_iommu_aperture)) - goto disable_snp; - - if (!amd_iommu_sme_check()) - goto disable_snp; - ret =3D iommu_go_to_state(IOMMU_IVRS_DETECTED); if (ret) goto disable_snp; --=20 2.55.0 From nobody Mon Sep 28 10:47:24 2026 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 874BB38F92F for ; Sat, 22 Aug 2026 22:21:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.12 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787437277; cv=pass; b=elIExowh02aJmQAFr85cvSF02soQ0m9AsPf/755rPOC18T4mlnHRYN69w5fQthiulLh7jAjw5epeS4H235onlC5CC88Rup3M/gXpc0Rg5bAI/+tsKiJasBq0uyPUe+o3yL4HI45KLD4tst/UcoyVZ1/Pf2+kvuh0uEG54OwY9+4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787437277; c=relaxed/simple; bh=h8TfqPX2WpbnFrAtyGDcw4nT6/QR3iW+y9fFy/kl0X0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZdctcyG0EBay3maCbmC42yMVjqVsUPcB5VPL98gp/0MfierZUVPar8U9vWvhT6/V9Xb6MDGVGcMoLvCL7oYon15SGj9VSrBzsfsB5xZVlWedYQ0VlI2RuM+e0zKNOnsEC1+bQWTZKv7O2DVhyy8vFb2fOyEOte0WcedPZ+YTZYQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=rong.moe; spf=pass smtp.mailfrom=rong.moe; dkim=pass (2048-bit key) header.d=rong.moe header.i=i@rong.moe header.b=XE7FoOW6; arc=pass smtp.client-ip=136.143.188.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=rong.moe Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rong.moe Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rong.moe header.i=i@rong.moe header.b="XE7FoOW6" ARC-Seal: i=1; a=rsa-sha256; t=1787437238; cv=none; d=zohomail.com; s=zohoarc; b=Z8dsnHSvCFZLeKQGnUeTeD57uew0Ndr4mqgGFUgWbZ3D9EJE/ZC6V3Uv2Ut8jna2TusSUETxh2k7YyQ+G9gVFhAc4Yz1upENpNBncmCCnp4UkkQXFGXpgWsxUNXt5ZUw/YCgyTcl3Rrpcdot90J+9EcDPPecZQxVfwMxiTJQjEQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787437238; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:Subject:Subject:To:To:Message-Id:Reply-To; bh=GtGsTB5Glx57MwzxsA8bZzWGARAfxh0/aSNYEXk1fWM=; b=NP6dqMCrRPc7lkAjgBW5zKLD3RN4bF257130ywHvtuVci4yW4AcMRlgTjVs6n/jSSGmmT2ZrsYfHf/qlTsfVdwAP58WdwHE6T1GF0A90TJlJbI0TZIcXy9DUtnawqW3yprNzKwVVqnJ8mOg+zfRUNjD+ONX1cqgSd21yt2gKbsw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=rong.moe; spf=pass smtp.mailfrom=i@rong.moe; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1787437238; s=zmail2048; d=rong.moe; i=i@rong.moe; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=GtGsTB5Glx57MwzxsA8bZzWGARAfxh0/aSNYEXk1fWM=; b=XE7FoOW6Sbn3rfjLyBlFmI8ewyv84Squjei40GGv/74Pib7lGh/xHQF+kABwqbJ9 PYax8k33bpafPCFEEwLEiHDZ26ngSoMDIc8E21Lsr8b6kVXpjIguoa7az5ya9PhMEAw PCFD/wp7UrBF4XBso/q+NFHImvqgwVWXIiShlSiFKtOTOEwe8/2FTChkYCIZMegBZ9v Zih0Mvlt57wVxiSkgFRw00YL9FBW9ALK2fYU/F9IvUnlF0J/5WdVlNNlRc4ku/cNNSK bdPwQEtvUVJzXXc054KOu5+i1eC0YFimvGVHvnAOJ2Vy2aiHuI+Aycm2z8mFbfRBWNa wGoaaruSCw== Received: by mx.zohomail.com with SMTPS id 1787437237161845.8381860069328; Sat, 22 Aug 2026 15:20:37 -0700 (PDT) From: Rong Zhang Date: Sun, 23 Aug 2026 06:20:16 +0800 Subject: [PATCH v3 2/3] iommu/amd: Disallow implicit START_STATE => IVRS_DETECTED transition Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260823-amd-iommu-fix-acs-v3-2-dd768e09d771@rong.moe> References: <20260823-amd-iommu-fix-acs-v3-0-dd768e09d771@rong.moe> In-Reply-To: <20260823-amd-iommu-fix-acs-v3-0-dd768e09d771@rong.moe> To: "Joerg Roedel (AMD)" , Suravee Suthikulpanit , Vasant Hegde , Will Deacon , Robin Murphy , Huang Rui Cc: Ankit Soni , Sairaj Kodilkar , iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Rong Zhang X-Mailer: b4 0.17-dev-1f2f7 X-ZohoMailClient: External Xen PV intentionally skips calling amd_iommu_detect() in order to gate IOMMU initialization, as the Xen hypervisor has taken over the hardware. However, due to amd_iommu_prepare() requesting ACPI_FINISHED while setting up APIC, the state machine is still progressed, only to be stopped midway due to the `!amd_iommu_detected' check in early_amd_iommu_init(). This is worthless and fragile. It unnecessarily calls detect_ivrs(), which leads to extra overhead, i.e., getting the IVRS table and accessing the PCI config space. Disallow implicit START_STATE =3D> IVRS_DETECTED transition, so that amd_iommu_prepare() and other paths no longer progress the state machine accidentally. This should also help prevent potential bugs if more housekeeping work is added to amd_iommu_detect() in the future. Signed-off-by: Rong Zhang Reviewed-by: Ankit Soni --- drivers/iommu/amd/init.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 0fd0801a873f..72b5b11b9d75 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -3571,6 +3571,19 @@ static int __init iommu_go_to_state(enum iommu_init_= state state) { int ret =3D -EINVAL; =20 + /* + * Some essential housekeeping work is done by amd_iommu_detect(). + * Skipping calling it implies that the platform (e.g., Xen hypervisor) + * has taken over the hardware. Progressing the state machine in this + * case is worthless and fragile. + * + * There are several paths requesting later states, so disallow implicit + * START_STATE =3D> IVRS_DETECTED transition to prevent these paths from + * accidentally progressing the state machine. + */ + if (init_state =3D=3D IOMMU_START_STATE && state !=3D IOMMU_IVRS_DETECTED) + goto out; + while (init_state !=3D state) { if (init_state =3D=3D IOMMU_NOT_FOUND || init_state =3D=3D IOMMU_INIT_ERROR || @@ -3579,6 +3592,7 @@ static int __init iommu_go_to_state(enum iommu_init_s= tate state) ret =3D state_next(); } =20 +out: /* * SNP platform initilazation requires IOMMUs to be fully configured. * If the SNP support on IOMMUs has NOT been checked, simply mark SNP --=20 2.55.0 From nobody Mon Sep 28 10:47:24 2026 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13E3C38655B for ; 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mx.zohomail.com; dkim=pass header.i=rong.moe; spf=pass smtp.mailfrom=i@rong.moe; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1787437244; s=zmail2048; d=rong.moe; i=i@rong.moe; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=iyt8shaTMGeCWxc+lY/CB0B5V7Tna7mdBfZQ1b4z7Co=; b=E6lun4qZnSURhKYpf1nGsx3Akfgchk5ZzjWk46B79yDt8VvsItsfmjlYcr51NbEo kSITpbToEJIyh3QXQsQJOxV86z1HYCSs1jizi5CX8Cr7UIFP2SmTKOMiUarD7Jpnsb2 YhqPxWUl8aZrSbrBSlypGrmbrjpDGywvPhGQECTjrOYlBGrJyOecEN/JhwV7pF7P4E6 Sk+lRd436Ccd6O9Dc5+lbLogz9WIX1HvMeJ/qNvb6pzEd2vGjRusPw37OTsXMuHQmHU V/xZeDvw1zTaTB4J98rDJlS8Rt6g5UqljWVzkN/6dY4aq3ZHGEwBd6agi9Wq2ngOTWi 7S+Cw6VIkw== Received: by mx.zohomail.com with SMTPS id 1787437243614168.4123985263932; Sat, 22 Aug 2026 15:20:43 -0700 (PDT) From: Rong Zhang Date: Sun, 23 Aug 2026 06:20:17 +0800 Subject: [PATCH v3 3/3] iommu/amd: Remove ad-hoc checks that are never true Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260823-amd-iommu-fix-acs-v3-3-dd768e09d771@rong.moe> References: <20260823-amd-iommu-fix-acs-v3-0-dd768e09d771@rong.moe> In-Reply-To: <20260823-amd-iommu-fix-acs-v3-0-dd768e09d771@rong.moe> To: "Joerg Roedel (AMD)" , Suravee Suthikulpanit , Vasant Hegde , Will Deacon , Robin Murphy , Huang Rui Cc: Ankit Soni , Sairaj Kodilkar , iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Rong Zhang X-Mailer: b4 0.17-dev-1f2f7 X-ZohoMailClient: External The state transitions of the AMD IOMMU Initialization State Machine imply that some ad-hoc checks will never be true. In detail, they are only reachable if the previous state transitions have succeeded, but the conditions are only true if the previous state transitions have failed. Therefore, remove the redundant ad-hoc checks. Signed-off-by: Rong Zhang Reviewed-by: Ankit Soni --- drivers/iommu/amd/init.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 72b5b11b9d75..d81adb8efe0e 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -163,7 +163,6 @@ int amd_iommu_gpt_level =3D PAGE_MODE_4_LEVEL; int amd_iommu_guest_ir =3D AMD_IOMMU_GUEST_IR_VAPIC; static int amd_iommu_xt_mode =3D IRQ_REMAP_XAPIC_MODE; =20 -static bool amd_iommu_detected; static bool amd_iommu_disabled __initdata; static bool amd_iommu_force_enable __initdata; static bool amd_iommu_irtcachedis; @@ -3222,9 +3221,6 @@ static int __init early_amd_iommu_init(void) acpi_status status; u8 efr_hats, max_vasize; =20 - if (!amd_iommu_detected) - return -ENODEV; - status =3D acpi_get_table("IVRS", 0, &ivrs_base); if (status =3D=3D AE_NOT_FOUND) return -ENODEV; @@ -3303,7 +3299,7 @@ static int __init early_amd_iommu_init(void) } =20 /* Disable any previously enabled IOMMUs */ - if (!is_kdump_kernel() || amd_iommu_disabled) + if (!is_kdump_kernel()) disable_iommus(); =20 if (amd_iommu_irq_remap) @@ -3398,12 +3394,6 @@ static __init void iommu_snp_enable(void) if (!cc_platform_has(CC_ATTR_HOST_SEV_SNP)) return; =20 - /* SNP support required IOMMU to be ON */ - if (no_iommu) { - pr_warn("SNP: IOMMU disabled, SNP cannot be supported.\n"); - goto disable_snp; - } - amd_iommu_snp_mode0_sup =3D check_feature2(FEATURE_SNP_PAGE_MODE0_SUP); /* * If SNP page mode 0 is not enabled, then SNP support requires that IOMMU @@ -3716,7 +3706,6 @@ void __init amd_iommu_detect(void) if (ret) goto disable_snp; =20 - amd_iommu_detected =3D true; iommu_detected =3D 1; x86_init.iommu.iommu_init =3D amd_iommu_init; return; --=20 2.55.0