From nobody Mon Sep 28 11:39:22 2026 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97CCA3749E1; Sat, 22 Aug 2026 07:48:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.251.229.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787384918; cv=none; b=MeLjGno7L8adFdsVdvJ1eK/CVNnsLtTTt0VamS37jxXj+xrMdnSJMxhT6QG8u3DQB7nU9R9yH0lem2tUh6EWamMRvWHApY7XEtc9nmgFI7ZFZA8E313f5/AiBLADzzqOPT0CFJnp9X1/4canHxAtRSHaPPV01UIxDk74eB2Qags= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787384918; c=relaxed/simple; bh=eEKcp+ZFeX/Ksan9V6AYgrDLNZy6ma+EOy9OsvdWJDg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rqVlt7wzoBjxpjxaucW7o7N2oNcGhGk/2vfwWc9F/3N0ihk+RVUPP1U/3pYc9F+vEhIH4SLu/XdwFheuGz3JHGEhZ7BfFd1iHASwu6/ebnIRS7K2nDJozVeH/U/g+mLTNJ3KxKEYx40hMWDeetIKRluflC4Sk91AcPGwXeZ0x1M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com; spf=pass smtp.mailfrom=nabladev.com; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b=eIsFXOOI; arc=none smtp.client-ip=178.251.229.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nabladev.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b="eIsFXOOI" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 4937D11C816; Sat, 22 Aug 2026 09:48:29 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1787384910; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=Odsb7mrDdpSm6YigiuUwk+GtdjNZDbTtQ5jOjfU5W1I=; b=eIsFXOOIVYKHSWd7LVpLwO78iE4CvSivRKndkdHlqQOqRHqT/Ei6qgBep1wMhfmssbLc7Z MWZPpNwm9nQPcwWswY4QS8E5efuToAKmOvMWwI6lhrySkVaR91jelJcV8MTdzAuOzDurtu ANxqguOGHEbNhNm0uPT2Uwg/Rssl3ofvL0zT7FM4iXd5ZCTi/78luzMtrw1YBzNwC+fDIT GLUOhUJJpau7Lj8/t+eve3E+pF17QTb93e4B9FYsz7svrwQbVstHp6Iu+fEt/j5fY+miQ4 7o3Rkgy/tMR0Lg39dPatnvDYf6eAXQTYaMJv7StoNyXmo5sEeZIpBKYLDlK9GA== From: Marek Vasut To: linux-usb@vger.kernel.org Cc: fabrice.gasnier@foss.st.com, Pankaj Dev , Rahul Kumar , =?UTF-8?q?Cl=C3=A9ment=20Le=20Goffic?= , Marek Vasut , Alexandre Torgue , Christian Bruel , Conor Dooley , Greg Kroah-Hartman , Krzysztof Kozlowski , Maxime Coquelin , Neil Armstrong , Rob Herring , Rosen Penev , Thinh Nguyen , Vinod Koul , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v3 1/9] dt-bindings: phy: Document ST STM32MP25 USB2-FEMTO PHY Date: Sat, 22 Aug 2026 09:46:34 +0200 Message-ID: <20260822074816.548662-2-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260822074816.548662-1-marex@nabladev.com> References: <20260822074816.548662-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 From: Pankaj Dev Document USB2 PHY for STM32MP25 USB2 controllers, which includes the USB2.0 host-only controller and USB 2.0 part of the DWC3 controller. Two such PHYs in total are present in STM32MP25 SoC, they both are slightly different, therefore they use different compatible string to discern them. Signed-off-by: Pankaj Dev Co-developed-by: Rahul Kumar Signed-off-by: Rahul Kumar Co-developed-by: Fabrice Gasnier Signed-off-by: Fabrice Gasnier Co-developed-by: Cl=C3=A9ment Le Goffic Signed-off-by: Cl=C3=A9ment Le Goffic Co-developed-by: Marek Vasut Signed-off-by: Marek Vasut --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Thinh Nguyen Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- V2: - Fix up Sob/Cdb lines - Fix up compatible string in example - Use additionalProperties: false - Expand description: - Use clock-cells =3D <1> to discern OSC and future PLL clock from the = PHY V3: - Move clock-cells next to PHY cells - Fix the bindings - Fix up Sob/Cdb lines further --- .../bindings/phy/st,stm32-usb2phy.yaml | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/st,stm32-usb2phy.= yaml diff --git a/Documentation/devicetree/bindings/phy/st,stm32-usb2phy.yaml b/= Documentation/devicetree/bindings/phy/st,stm32-usb2phy.yaml new file mode 100644 index 0000000000000..cc5044790beea --- /dev/null +++ b/Documentation/devicetree/bindings/phy/st,stm32-usb2phy.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/st,stm32-usb2phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 MPU High-Speed USB PHY + +description: + USB2 PHY block in STM32 is attached to USB 2.0 Host controller and + USB 2.0 side of DWC3 DRD controller, and provides the USB LS/FS/HS + connectivity. Both PHYs are the FEMTO-PHY, but their configuration + bits in the system control register are different for each variant. + +maintainers: + - Fabrice Gasnier + - Marek Vasut + - Pankaj Dev + +properties: + compatible: + enum: + - st,stm32mp25-usb2phy1 + - st,stm32mp25-usb2phy2 + + "#clock-cells": + const: 1 + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + vdd33-supply: + description: Phandle to regulator providing 3V3 power supply to the US= B2 HS PHY + +required: + - compatible + - "#clock-cells" + - "#phy-cells" + - clocks + - resets + - vdd33-supply + +additionalProperties: false + +examples: + - | + #include + #include + + usb-phy@2400 { + compatible =3D "st,stm32mp25-usb2phy1"; + reg =3D <0x2400 0x24>; + #phy-cells =3D <0>; + #clock-cells =3D <1>; + clocks =3D <&rcc CK_KER_USB2PHY1>; + resets =3D <&rcc USB2PHY1_R>; + vdd33-supply =3D <&vdd33usb>; + }; --=20 2.53.0 From nobody Mon Sep 28 11:39:22 2026 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED74B39C015; Sat, 22 Aug 2026 07:48:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.251.229.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787384924; cv=none; b=Z3dThJ1gTQHOCDh7k8Sb0sPrTq1myOCsL/Bua0rLWpqW2prAeIqSOIWVYCRKAqyh9Ptf7oPFyC0opoVUwN/UtKW1ag0YSAB1hyj/4rpDJgsPmMlmVecQ92VXiQ8FWiRp9H6YvkizA8/stgUls5M3tJ8deBc+nTVNTp6x7poj1Uk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787384924; c=relaxed/simple; bh=hdotd/2BQXdBGUbBuLG+C+OTjiQeXNOW1iIu31ueBE0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YUft0P/JJ9pzkDpM9mAp+MCJe9pZJAXyQFnVQyDEHr5QCc18Y5rJNIgDFdr+VUf27avxyMZUiJvQKklArA0aaM1pSxeCoiBH+1d8P2qWOmICK4VbxlL5bkYZDk+iWTOLKRxnHd17vworSzL9dXv1SbFhWQ9WK4Cspmcb9rc4qX8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com; spf=pass smtp.mailfrom=nabladev.com; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b=KVQFlsDb; arc=none smtp.client-ip=178.251.229.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nabladev.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b="KVQFlsDb" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id B2C3C11C7E4; Sat, 22 Aug 2026 09:48:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1787384915; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=xUdenENyQwUjQyGoVFMtjr5yG4Sdwpi0MV+U54TXptw=; b=KVQFlsDb3Fgg0H+AWN/tkmI4/mrr2W1fKJQIrhiBf1sRlxEiNWNNTQYfu+H6JLYFxoJqj0 5k3xQVmOxIMTP/YIhsbPup7pSoj+kjLY6vlL7q1B0T6aSonDSFkjFzvOK68wYsPawCdDSP clIoO9swsrfEZAiZirvC4X3z00ONcM+dCdSHwHFNgWM06EHFN/PeTRHaxvwM34mmdjuwn+ PFUwUx6HsJnwneFVSTI1IZCe+/YWHKQldarAIgQNz/cMzIePZGpU7NwA+swNW6LlrS5bXQ 05Zhs40RrU2SudzGi4jNZPniqwawdTJNWZOnZRglySGYOkjVN7s9VTDxkp+mew== From: Marek Vasut To: linux-usb@vger.kernel.org Cc: fabrice.gasnier@foss.st.com, Pankaj Dev , Rahul Kumar , Christian Bruel , Marek Vasut , Alexandre Torgue , Conor Dooley , Greg Kroah-Hartman , Krzysztof Kozlowski , Maxime Coquelin , Neil Armstrong , Rob Herring , Rosen Penev , Thinh Nguyen , Vinod Koul , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v3 2/9] phy: stm32: Add support for ST STM32MP25 USB2-FEMTO PHY Date: Sat, 22 Aug 2026 09:46:35 +0200 Message-ID: <20260822074816.548662-3-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260822074816.548662-1-marex@nabladev.com> References: <20260822074816.548662-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" From: Pankaj Dev Add USB2 PHY driver for STM32MP25 USB2 controllers, which includes the USB2.0 host-only controller and USB 2.0 part of the DWC3 controller. Two such PHYs in total are present in STM32MP25 SoC, they both are slightly different, therefore they use different compatible string to discern them. Signed-off-by: Pankaj Dev Co-developed-by: Rahul Kumar Signed-off-by: Rahul Kumar Co-developed-by: Fabrice Gasnier Signed-off-by: Fabrice Gasnier Co-developed-by: Christian Bruel Signed-off-by: Christian Bruel Co-developed-by: Marek Vasut Signed-off-by: Marek Vasut --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Thinh Nguyen Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- V2: - Fix up Sob/Cdb lines - Operate PHY as a syscon subnode V3: - Update copyright years - Register two sets of clock, one 480 MHz PLL and one CMN - Split PHY ops per PHY, since the PHY2 does not have set mode ops - Fix up Sob/Cdb lines further --- drivers/phy/st/Kconfig | 10 + drivers/phy/st/Makefile | 1 + drivers/phy/st/phy-stm32-usb2phy.c | 406 +++++++++++++++++++++++++++++ 3 files changed, 417 insertions(+) create mode 100644 drivers/phy/st/phy-stm32-usb2phy.c diff --git a/drivers/phy/st/Kconfig b/drivers/phy/st/Kconfig index 49206185e5633..2835bb67bca9e 100644 --- a/drivers/phy/st/Kconfig +++ b/drivers/phy/st/Kconfig @@ -58,3 +58,13 @@ config PHY_STM32_USBPHYC used by an HS USB Host controller, and the second one is shared between an HS USB OTG controller and an HS USB Host controller, selected by a USB switch. + +config PHY_STM32_USB2PHY + tristate "STMicroelectronics STM32MP25 USB2.0 PHY Controller driver" + depends on ARCH_STM32 || COMPILE_TEST + depends on COMMON_CLK + select GENERIC_PHY + help + Enable this to support the High-Speed USB 2.0 transceivers that are + part of the STMicroelectronics STM32MP25 SoCs. The PHY itself is a + Synopsys FEMTO-PHY. diff --git a/drivers/phy/st/Makefile b/drivers/phy/st/Makefile index cb80e954ea9f0..4945df5ed78a8 100644 --- a/drivers/phy/st/Makefile +++ b/drivers/phy/st/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) +=3D phy-spear1340-mip= hy.o obj-$(CONFIG_PHY_STIH407_USB) +=3D phy-stih407-usb.o obj-$(CONFIG_PHY_STM32_COMBOPHY) +=3D phy-stm32-combophy.o obj-$(CONFIG_PHY_STM32_USBPHYC) +=3D phy-stm32-usbphyc.o +obj-$(CONFIG_PHY_STM32_USB2PHY) +=3D phy-stm32-usb2phy.o diff --git a/drivers/phy/st/phy-stm32-usb2phy.c b/drivers/phy/st/phy-stm32-= usb2phy.c new file mode 100644 index 0000000000000..8c68b2d208d73 --- /dev/null +++ b/drivers/phy/st/phy-stm32-usb2phy.c @@ -0,0 +1,406 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * STMicroelectronics STM32 USB2 PHY Controller driver + * Currently Only supported for STM32MP25 + * + * Copyright (C) 2022-2026 STMicroelectronics + * Author(s): Pankaj Dev . + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SYSCFG_USB2PHY2CR_USB2PHY2CMN BIT(2) +#define SYSCFG_USB2PHY2CR_VBUSVALID BIT(4) +#define SYSCFG_USB2PHY2CR_VBUSVLDEXTSEL BIT(5) +#define SYSCFG_USB2PHY2CR_VBUSVLDEXT BIT(6) + +#define USBH_NUM_CLK 2 + +struct stm32_usb2phy { + struct phy *phy; + struct regmap *regmap; + struct device *dev; + struct reset_control *rstc; + struct clk *phyref; + struct regulator *vdd33; + const struct stm32mp2_usb2phy_hw_data *hw_data; + atomic_t en_refcnt; + enum phy_mode mode; + u32 cr_offset; + bool is_init; + struct clk_hw clkpll_hw; + struct clk_hw clkcmn_hw; + /* Must be last */ + struct clk_hw_onecell_data onecell; +}; + +struct stm32mp2_usb2phy_hw_data { + u32 phyrefsel_mask; + const struct phy_ops *phy_ops; +}; + +static int stm32_usb2phy_enable(struct stm32_usb2phy *phy_dev) +{ + const struct stm32mp2_usb2phy_hw_data *phy_data =3D phy_dev->hw_data; + unsigned int refsel; + unsigned long rate; + int ret; + + /* Check if a phy is already init or clkpll in use */ + if (atomic_inc_return(&phy_dev->en_refcnt) > 1) + return 0; + + rate =3D clk_get_rate(phy_dev->phyref); + if (rate =3D=3D 19200000) + refsel =3D 0; + else if (rate =3D=3D 20000000) + refsel =3D 1; + else if (rate =3D=3D 24000000) + refsel =3D 2; + else + return -EINVAL; + + ret =3D regmap_update_bits(phy_dev->regmap, + phy_dev->cr_offset, + phy_data->phyrefsel_mask, + field_prep(phy_data->phyrefsel_mask, refsel)); + if (ret) + return ret; + + ret =3D regulator_enable(phy_dev->vdd33); + if (ret) + return ret; + + ret =3D clk_prepare_enable(phy_dev->phyref); + if (ret) + goto error_regdis; + + ret =3D reset_control_deassert(phy_dev->rstc); + if (ret) + goto error_clkdis; + + return 0; + +error_clkdis: + clk_disable_unprepare(phy_dev->phyref); +error_regdis: + regulator_disable(phy_dev->vdd33); + + return ret; +} + +static int stm32_usb2phy_disable(struct stm32_usb2phy *phy_dev) +{ + int ret; + + /* Check if a phy is still init or clkpll in use */ + if (atomic_dec_return(&phy_dev->en_refcnt) > 0) + return 0; + + ret =3D reset_control_assert(phy_dev->rstc); + if (ret) + return ret; + + clk_disable_unprepare(phy_dev->phyref); + + return regulator_disable(phy_dev->vdd33); +} + +static int stm32_usb2phy_set_mode(struct phy *phy, enum phy_mode mode, int= submode) +{ + struct stm32_usb2phy *phy_dev =3D phy_get_drvdata(phy); + u32 mask =3D SYSCFG_USB2PHY2CR_USB2PHY2CMN | + SYSCFG_USB2PHY2CR_VBUSVALID | + SYSCFG_USB2PHY2CR_VBUSVLDEXT; + u32 val =3D 0; + int ret; + + if (mode =3D=3D PHY_MODE_USB_HOST) { + if (submode !=3D USB_ROLE_NONE) + val =3D SYSCFG_USB2PHY2CR_VBUSVALID; + } else if (mode =3D=3D PHY_MODE_USB_DEVICE) { + val =3D SYSCFG_USB2PHY2CR_USB2PHY2CMN | + SYSCFG_USB2PHY2CR_VBUSVLDEXTSEL; + if (submode !=3D USB_ROLE_NONE) + val |=3D SYSCFG_USB2PHY2CR_VBUSVLDEXT; + mask |=3D SYSCFG_USB2PHY2CR_VBUSVLDEXTSEL; + } else { + return -EINVAL; + } + + ret =3D regmap_update_bits(phy_dev->regmap, phy_dev->cr_offset, mask, val= ); + if (ret) + return ret; + + phy_dev->mode =3D mode; + + return 0; +} + +static int stm32_usb2phy1_init(struct phy *phy) +{ + struct stm32_usb2phy *phy_dev =3D phy_get_drvdata(phy); + int ret; + + ret =3D stm32_usb2phy_enable(phy_dev); + if (ret) + return ret; + + phy_dev->is_init =3D true; + + return 0; +} + +static int stm32_usb2phy2_init(struct phy *phy) +{ + struct stm32_usb2phy *phy_dev =3D phy_get_drvdata(phy); + int ret; + + ret =3D stm32_usb2phy_enable(phy_dev); + if (ret) + return ret; + + if (phy_dev->mode !=3D PHY_MODE_INVALID) { + ret =3D stm32_usb2phy_set_mode(phy, phy_dev->mode, USB_ROLE_NONE); + if (ret) { + stm32_usb2phy_disable(phy_dev); + return ret; + } + } + + phy_dev->is_init =3D true; + + return 0; +} + +static int stm32_usb2phy_exit(struct phy *phy) +{ + struct stm32_usb2phy *phy_dev =3D phy_get_drvdata(phy); + int ret; + + ret =3D stm32_usb2phy_disable(phy_dev); + if (ret) + return ret; + + phy_dev->is_init =3D false; + + return 0; +} + +static const struct phy_ops stm32_usb2phy1_data =3D { + .init =3D stm32_usb2phy1_init, + .exit =3D stm32_usb2phy_exit, + .owner =3D THIS_MODULE, +}; + +static const struct phy_ops stm32_usb2phy2_data =3D { + .init =3D stm32_usb2phy2_init, + .exit =3D stm32_usb2phy_exit, + .set_mode =3D stm32_usb2phy_set_mode, + .owner =3D THIS_MODULE, +}; + +static int stm32_usb2phy_clkpll_prepare(struct clk_hw *hw) +{ + struct stm32_usb2phy *phy_dev =3D container_of(hw, struct stm32_usb2phy, + clkpll_hw); + + return stm32_usb2phy_enable(phy_dev); +} + +static void stm32_usb2phy_clkpll_unprepare(struct clk_hw *hw) +{ + struct stm32_usb2phy *phy_dev =3D container_of(hw, struct stm32_usb2phy, + clkpll_hw); + + stm32_usb2phy_disable(phy_dev); +} + +static unsigned long stm32_usb2phy_clkpll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return 480000000; +} + +static const struct clk_ops stm32_usb2phy_clkpll_ops =3D { + .prepare =3D stm32_usb2phy_clkpll_prepare, + .unprepare =3D stm32_usb2phy_clkpll_unprepare, + .recalc_rate =3D stm32_usb2phy_clkpll_recalc_rate, +}; + +static int stm32_usb2phy_clkcmn_prepare(struct clk_hw *hw) +{ + struct stm32_usb2phy *phy_dev =3D container_of(hw, struct stm32_usb2phy, + clkcmn_hw); + + return regmap_clear_bits(phy_dev->regmap, phy_dev->cr_offset, + SYSCFG_USB2PHY2CR_USB2PHY2CMN); +} + +static void stm32_usb2phy_clkcmn_unprepare(struct clk_hw *hw) +{ + struct stm32_usb2phy *phy_dev =3D container_of(hw, struct stm32_usb2phy, + clkcmn_hw); + + regmap_set_bits(phy_dev->regmap, phy_dev->cr_offset, + SYSCFG_USB2PHY2CR_USB2PHY2CMN); +} + +static const struct clk_ops stm32_usb2phy_clkcmn_ops =3D { + .prepare =3D stm32_usb2phy_clkcmn_prepare, + .unprepare =3D stm32_usb2phy_clkcmn_unprepare, +}; + +static int stm32_usb2phy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct device *dev =3D &pdev->dev; + struct stm32_usb2phy *phy_dev; + char *pllname, *cmnname; + const __be32 *offset; + struct phy *phy; + int ret; + + phy_dev =3D devm_kzalloc(dev, struct_size(phy_dev, onecell.hws, USBH_NUM_= CLK), GFP_KERNEL); + if (!phy_dev) + return -ENOMEM; + + phy_dev->dev =3D dev; + dev_set_drvdata(dev, phy_dev); + + phy_dev->rstc =3D devm_reset_control_get(dev, NULL); + if (IS_ERR(phy_dev->rstc)) + return dev_err_probe(dev, PTR_ERR(phy_dev->rstc), "Failed to get USB2PHY= reset\n"); + + phy_dev->phyref =3D devm_clk_get(dev, NULL); + if (IS_ERR(phy_dev->phyref)) + return dev_err_probe(dev, PTR_ERR(phy_dev->phyref), "Failed to get phyre= f clk\n"); + + phy_dev->vdd33 =3D devm_regulator_get_optional(dev, "vdd33"); + if (IS_ERR(phy_dev->vdd33)) + return dev_err_probe(dev, PTR_ERR(phy_dev->vdd33), "Failed to get vdd3v3= supply\n"); + + phy_dev->regmap =3D syscon_node_to_regmap(dev->of_node->parent); + if (IS_ERR(phy_dev->regmap)) + return dev_err_probe(dev, PTR_ERR(phy_dev->regmap), "Failed to get regma= p\n"); + + offset =3D of_get_address(dev->of_node, 0, NULL, NULL); + if (!offset) + return dev_err_probe(dev, -EINVAL, "Failed to get regmap offset\n"); + + phy_dev->cr_offset =3D be32_to_cpu(*offset); + + phy_dev->hw_data =3D device_get_match_data(dev); + + phy =3D devm_phy_create(dev, NULL, phy_dev->hw_data->phy_ops); + if (IS_ERR(phy)) + return dev_err_probe(dev, PTR_ERR(phy), "Failed to create PHY\n"); + + phy_dev->phy =3D phy; + phy_set_drvdata(phy, phy_dev); + + phy_provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (IS_ERR(phy_provider)) + return PTR_ERR(phy_provider); + + pllname =3D devm_kasprintf(dev, GFP_KERNEL, "clk_%s_48m", + of_node_full_name(dev->of_node)); + if (!pllname) + return -ENOMEM; + + cmnname =3D devm_kasprintf(dev, GFP_KERNEL, "clk_%s_cmn", + of_node_full_name(dev->of_node)); + if (!cmnname) + return -ENOMEM; + + phy_dev->onecell.num =3D USBH_NUM_CLK; + phy_dev->onecell.hws[0] =3D &phy_dev->clkpll_hw; + phy_dev->onecell.hws[1] =3D &phy_dev->clkcmn_hw; + + phy_dev->clkpll_hw.init =3D CLK_HW_INIT_NO_PARENT(pllname, &stm32_usb2phy= _clkpll_ops, 0); + ret =3D devm_clk_hw_register(phy_dev->dev, &phy_dev->clkpll_hw); + if (ret) + return dev_err_probe(phy_dev->dev, ret, "Failed to register PLL clock\n"= ); + + phy_dev->clkcmn_hw.init =3D CLK_HW_INIT_HW(cmnname, &phy_dev->clkpll_hw, + &stm32_usb2phy_clkcmn_ops, 0); + ret =3D devm_clk_hw_register(phy_dev->dev, &phy_dev->clkcmn_hw); + if (ret) + return dev_err_probe(phy_dev->dev, ret, "Failed to register CMN clock\n"= ); + + ret =3D devm_of_clk_add_hw_provider(phy_dev->dev, of_clk_hw_onecell_get, = &phy_dev->onecell); + if (ret) + return dev_err_probe(phy_dev->dev, ret, "Failed to add clock provider\n"= ); + + return 0; +} + +static int stm32_usb2phy_suspend(struct device *dev) +{ + struct stm32_usb2phy *phy_dev =3D dev_get_drvdata(dev); + + if (phy_dev->is_init) + return stm32_usb2phy_disable(phy_dev); + + return 0; +} + +static int stm32_usb2phy_resume(struct device *dev) +{ + struct stm32_usb2phy *phy_dev =3D dev_get_drvdata(dev); + + if (phy_dev->is_init) + return stm32_usb2phy_enable(phy_dev); + + return 0; +} + +/* STM32MP25xx USB 2.0 PHY attached to USB 2.0 Host controller */ +static const struct stm32mp2_usb2phy_hw_data stm32mp25_usb2phy1_hwdata =3D= { + .phyrefsel_mask =3D GENMASK(6, 4), + .phy_ops =3D &stm32_usb2phy1_data, +}; + +/* STM32MP25xx USB 2.0 PHY attached to USB 2.0 part of DWC3 controller */ +static const struct stm32mp2_usb2phy_hw_data stm32mp25_usb2phy2_hwdata =3D= { + .phyrefsel_mask =3D GENMASK(14, 12), + .phy_ops =3D &stm32_usb2phy2_data, +}; + +static const struct of_device_id stm32_usb2phy_of_match[] =3D { + { .compatible =3D "st,stm32mp25-usb2phy1", .data =3D &stm32mp25_usb2phy1_= hwdata }, + { .compatible =3D "st,stm32mp25-usb2phy2", .data =3D &stm32mp25_usb2phy2_= hwdata }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, stm32_usb2phy_of_match); + +static DEFINE_SIMPLE_DEV_PM_OPS(stm32_usb2phy_pm_ops, + stm32_usb2phy_suspend, stm32_usb2phy_resume); + +static struct platform_driver stm32_usb2phy_driver =3D { + .probe =3D stm32_usb2phy_probe, + .driver =3D { + .name =3D "stm32-usb2phy", + .of_match_table =3D stm32_usb2phy_of_match, + .pm =3D pm_sleep_ptr(&stm32_usb2phy_pm_ops) + } +}; + +module_platform_driver(stm32_usb2phy_driver); + +MODULE_AUTHOR("Pankaj Dev "); +MODULE_DESCRIPTION("STMicroelectronics Generic USB2PHY driver for stm32"); +MODULE_LICENSE("GPL"); --=20 2.53.0 From nobody Mon Sep 28 11:39:22 2026 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 574C139CD07; Sat, 22 Aug 2026 07:48:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.251.229.89 ARC-Seal: i=1; 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spf=pass smtp.mailfrom=nabladev.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b="bT1KYw9m" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 4BCD111C814; Sat, 22 Aug 2026 09:48:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1787384921; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=dHGNNdjbX2tcoPtYPHkVrNbZLNhLOGaAgeIztRF8jLc=; b=bT1KYw9mntE9tY1XNkNwqA1habI1lUnirgFsZeHcc8peXSwITWlHphNPPELgwwR5OI6BEd g2aBHRmLKWs8gce7qanmB4Vnyo2iglC5rjCROWX1QH48Mr4kfAC7T8MqfD5aFRw8ZC/LCd H2yDRbMpvQtrC0C/IWkZIAW4fvNyf6lskcRV9VFYMGUtR5nDr5LAwdSvJ7NYKZaeS3zNB0 d+RwyxFYw+KV2k/e7NXHfJJQJWqgh32HPpTwNjKjEVENKGwT5KYJjZt5yDph2Tn11pjEe9 uyPMEdgLmXORXTTZ0vo3+KDKgJgRnKOh+0h5fj2bU5QfwmMg2lpcw0LFeelmVA== From: Marek Vasut To: linux-usb@vger.kernel.org Cc: fabrice.gasnier@foss.st.com, Marek Vasut , Alexandre Torgue , Christian Bruel , Conor Dooley , Greg Kroah-Hartman , Krzysztof Kozlowski , Maxime Coquelin , Neil Armstrong , Pankaj Dev , Rahul Kumar , Rob Herring , Rosen Penev , Thinh Nguyen , Vinod Koul , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v3 3/9] dt-bindings: usb: generic-ehci: Document access-controllers property Date: Sat, 22 Aug 2026 09:46:36 +0200 Message-ID: <20260822074816.548662-4-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260822074816.548662-1-marex@nabladev.com> References: <20260822074816.548662-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Document the access-controllers for EHCI USB controllers in case access checks need to be performed to use them. Signed-off-by: Marek Vasut --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Thinh Nguyen Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- V2: No change V3: No change --- Documentation/devicetree/bindings/usb/generic-ehci.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Docu= mentation/devicetree/bindings/usb/generic-ehci.yaml index ae9fb70d0212c..6bca56681cdfe 100644 --- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml +++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml @@ -80,6 +80,9 @@ properties: minItems: 1 maxItems: 2 =20 + access-controllers: + maxItems: 1 + dma-coherent: true =20 interrupts: --=20 2.53.0 From nobody Mon Sep 28 11:39:22 2026 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E92DB391E4B; Sat, 22 Aug 2026 07:48:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.251.229.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787384934; cv=none; b=ju6M6Cf7jVmZvEZf2CHWPi48OHzAYM9X/WH+eQu3djPdXuDBGpLWRC9hEvAzLGmAWHCroOcIYvLyMLwxHqPiaYwMbwf9u5qipomf/k1bPyrHboLFJIRnRe3ItvzQ2/nJ1hOw46h6kzoODO3QjoYkfS7IGKbsZdGt65CGLVisTYg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787384934; c=relaxed/simple; bh=eQZzTX69ZNqNqAVNaiEOHKkGcpWQykz0c0VoBBtx8WY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=b2aSI7pQnkED3xJ28FVAF7Uw/SBAINYPnAai2pCOW3CVIC+ZaIX1j9t1+WErf2N79WNNWNJpfpH5dadlDCzrzu/FXQ6gGr5PbtcBdzQrI15zdY+hNsazHoX9mmVGx8ElZcFpgtkfttk/ibsxacz6SUoo1nlcufuh51GLk+MAbUY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com; spf=pass smtp.mailfrom=nabladev.com; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b=hxqyHfyc; arc=none smtp.client-ip=178.251.229.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nabladev.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b="hxqyHfyc" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id D7BF411C817; Sat, 22 Aug 2026 09:48:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1787384926; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=oSf/Qc+FVc/kqJH918JkgIf54jA4VBkL3h/ZDBCPZbQ=; b=hxqyHfycLXWCe1z+CA64ka4fT/oY2RmS4jJsP6+qVvd9+JuMRPLZyW8Zx88kzoGBzUCc/u ujUIGoJJMJBmNPXe/MJ2JyZEdqEObr/iYucJGJyYhsNOYiGPyYpug5jHBtSYxBfBIxAFvU PbNszxxGjbkm1woedkd0MSqK/kPKo1asNvZeDZwIx6GbzVFhn/KRbGHUJf+Xbt/No/EjyO ZVQAta6bn9bXUe0cYG23kIVeV590xYeULeVlhGmOI2UPZK/qxghinGmXJEv3E2mu50WKC1 /JRmvmAQA0tCMRJ6Em7MxLX7p7i9nvFsg0V8PnAbeSxMSdvaeWyXIKB691MfJA== From: Marek Vasut To: linux-usb@vger.kernel.org Cc: fabrice.gasnier@foss.st.com, Marek Vasut , Alexandre Torgue , Christian Bruel , Conor Dooley , Greg Kroah-Hartman , Krzysztof Kozlowski , Maxime Coquelin , Neil Armstrong , Pankaj Dev , Rahul Kumar , Rob Herring , Rosen Penev , Thinh Nguyen , Vinod Koul , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v3 4/9] dt-bindings: usb: generic-ohci: Document access-controllers property Date: Sat, 22 Aug 2026 09:46:37 +0200 Message-ID: <20260822074816.548662-5-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260822074816.548662-1-marex@nabladev.com> References: <20260822074816.548662-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Document the access-controllers for OHCI USB controllers in case access checks need to be performed to use them. Signed-off-by: Marek Vasut --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Thinh Nguyen Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- V2: No change V3: No change --- Documentation/devicetree/bindings/usb/generic-ohci.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Docu= mentation/devicetree/bindings/usb/generic-ohci.yaml index 322808aaa2839..8e3522a3faa76 100644 --- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml +++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml @@ -65,6 +65,9 @@ properties: reg: maxItems: 1 =20 + access-controllers: + maxItems: 1 + dma-coherent: true =20 interrupts: --=20 2.53.0 From nobody Mon Sep 28 11:39:22 2026 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3233039B97E; Sat, 22 Aug 2026 07:48:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.251.229.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787384940; cv=none; b=lMsFLWzVqofdQm8ctHf4Ocj3CgpxB8HRnipDYdDptuRvyOSJ7GqyEjFpT8sLWzXu52SM+SGj+lVM/56kU0kK8yT2t/HPeQ1YPMSXDxSzh8oici0i6pUI8yGVFIPE9sFAUaT2RAVwalTs0xeBJ9djQNdO6W1DLZOjJLHpIKh5ngo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787384940; c=relaxed/simple; bh=sN0iw09XNa32HD6vUppix+w2BkLRdmQM6OSi7enZVHE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hrRN1oB/DbTol4NvEsBeRAj3ca4JfOjKcM3azwp7qARwW8qd5PA+1ojkgRO49keFwyy1LgBri05KpFllR39hdlExpJ5Ms2N0BWeT/CUybJh+ACLUoCviJOwo9yI78DesePbyTTo/KoQwPfBo9bge6pYr5x8h3xF8uWNlZxn7kLw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com; spf=pass smtp.mailfrom=nabladev.com; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b=PSccTpou; arc=none smtp.client-ip=178.251.229.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nabladev.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b="PSccTpou" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 4235F11C81B; Sat, 22 Aug 2026 09:48:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1787384932; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=XviFG8sDQ7+lvUoVjqxltW2yCT0wFNF6qXQo7VooJMo=; b=PSccTpouFtFJFKkzAnp60JcxIUWQFk0oWnf0QdHeV5AKzoK6YndUJy1g0TlNCNxkXOC6Pc WbjV4mgWlc3MpenrSMPCKfRxoG3rWrRutSb974IdHtMDugySgvo8IZwXtfVE8Z92MIFwHS CgPQGxMfClzuJ12fV1vBvKPixQ4Pnwy7Exk4rHhI1icl/6o7eziN47DOfzUOYOsVhyIq4n FjpeHbl3hdLP2YcPTWd+Ev318wSzohJjPJ90ZuE6u4/4RuRrFwjitDNLvFzWTMBAmDj6wc EKN7FPwAUX+Q6GbqC8v3vArfevm2czWIxM4/u3OPjaxf3lHyUDZ0M8XUC8drQA== From: Marek Vasut To: linux-usb@vger.kernel.org Cc: fabrice.gasnier@foss.st.com, Marek Vasut , Pankaj Dev , =?UTF-8?q?Cl=C3=A9ment=20Le=20Goffic?= , Gatien Chevallier , Alexandre Torgue , Christian Bruel , Conor Dooley , Greg Kroah-Hartman , Krzysztof Kozlowski , Maxime Coquelin , Neil Armstrong , Rahul Kumar , Rob Herring , Rosen Penev , Thinh Nguyen , Vinod Koul , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v3 5/9] dt-bindings: usb: dwc3: Document ST STM32MP2 DWC3 xHCI USB controller Date: Sat, 22 Aug 2026 09:46:38 +0200 Message-ID: <20260822074816.548662-6-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260822074816.548662-1-marex@nabladev.com> References: <20260822074816.548662-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 The ST STM32MP2 SoC contains single instance of DWC3 USB controller with glue logic wrapper around it controlled by syscon. Document the glue logic and DWC3 controller. Co-developed-by: Pankaj Dev Signed-off-by: Pankaj Dev Co-developed-by: Cl=C3=A9ment Le Goffic Signed-off-by: Cl=C3=A9ment Le Goffic Co-developed-by: Gatien Chevallier Signed-off-by: Gatien Chevallier Signed-off-by: Marek Vasut --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Thinh Nguyen Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- V2: Fix up Sob/Cdb lines V3: - Document maximum-speed - Switch resets to maxItems: 1 - Drop label from example - Use generic over-current-active-low - Use ref: snps,dwc3-common.yaml and drop generic dr_mode/maximum-speed= /phys/phy-names --- .../bindings/usb/st,stm32mp25-dwc3.yaml | 97 +++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/st,stm32mp25-dwc3= .yaml diff --git a/Documentation/devicetree/bindings/usb/st,stm32mp25-dwc3.yaml b= /Documentation/devicetree/bindings/usb/st,stm32mp25-dwc3.yaml new file mode 100644 index 0000000000000..96bd557327252 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/st,stm32mp25-dwc3.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/st,stm32mp25-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 MPU DWC3 USB SoC controller + +description: + The STM32 MPU DWC3 USB SoC controller block supports both + Host(SS/HS/FS/LS) and Device(SS/HS/FS) mode operation + +maintainers: + - Fabrice Gasnier + - Marek Vasut + +allOf: + - $ref: snps,dwc3-common.yaml# + +properties: + compatible: + const: st,stm32mp25-dwc3 + + reg: + maxItems: 1 + + access-controllers: + maxItems: 1 + + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + items: + - const: ref + - const: bus_early + - const: suspend + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + over-current-active-low: + type: boolean + description: Over-Current signal polarity is active-low + + st,syscfg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: Phandle to system configuration controller. + items: + - items: + - description: phandle to syscfg + - description: USB3DR control offset within syscfg + + st,enable-port-power-control: + type: boolean + description: Enable Host-Mode Port Power Control (bit-3 of capability = param HCCPARAMS) + + st,vbusen-active-low: + type: boolean + description: VBUS-ENABLE signal polarity is active-low + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - phys + - phy-names + - resets + - st,syscfg + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + usb@48300000 { + compatible =3D "st,stm32mp25-dwc3"; + reg =3D <0x48300000 0x100000>; + clocks =3D <&rcc CK_KER_USB2PHY2>, <&rcc CK_BUS_USB3DR>, <&rcc CK_= KER_USB2PHY2>; + clock-names =3D "ref", "bus_early", "suspend"; + interrupts =3D ; + phys =3D <&usb2_phy>, <&usb3_phy>; + phy-names =3D "usb2-phy", "usb3-phy"; + resets =3D <&rcc USB3DR_R>; + over-current-active-low; + st,syscfg =3D <&syscfg 0x4800>; + st,vbusen-active-low; + }; --=20 2.53.0 From nobody Mon Sep 28 11:39:22 2026 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B195B3905F4; Sat, 22 Aug 2026 07:49:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.251.229.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787384946; cv=none; b=NRZFSKRwAjibl4zTG3wkTjjdiGzllSSnHc05rHgpWN6VBPGtG4t/gpahCjeb99qYIifkEXGzNFEW+Yft4+UtBj+CKW3SNcQa2Ql/W8Gcg3UIzWRJPhwEy28Gc1uMGiHqhKAJfOBiTFIkuK4tJAJFfzMDDcfE1ve1aPxUsPAIxn0= ARC-Message-Signature: i=1; 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Sat, 22 Aug 2026 09:48:56 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1787384937; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=2L5O99jQ5jMH3/ZfNLN4ePAqoJtT/Ha0IVk0UXWwOWs=; b=Uy9wex9zeflIc5sXrnf6UpDhjwFjGqxghrNV+rL8o9+jBbZnUe6/EpCCU5z1lHUmgybsd+ FJ3ds0cpwFDAgB+cW6gGsQU9s4YyKlaODnkiPkruoRv03n9OMnlvnfBHUGDRFUAfGQDuro bwhgXXWixa+rfw47QQUUjaNaVZrdQhZ8CWFE0OvyJpOl6a3l2MCKpMQtIGJlOlId56EGxz bwy+zPwa/GDPgRufWnuWJpqNe//2WZwQGpF91O+kTPKmnXSO91mXTiaWWTzugi77stCJTP rJJd0Im4lOh8XY5NxaONAHlZJynAKWv1f2DhRua9kGB/vOij5voujgLiHUD97Q== From: Marek Vasut To: linux-usb@vger.kernel.org Cc: fabrice.gasnier@foss.st.com, Marek Vasut , Alexandre Torgue , Christian Bruel , Conor Dooley , Greg Kroah-Hartman , Krzysztof Kozlowski , Maxime Coquelin , Neil Armstrong , Pankaj Dev , Rahul Kumar , Rob Herring , Rosen Penev , Thinh Nguyen , Vinod Koul , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v3 6/9] usb: dwc3: dwc3-generic-plat: Add ST STM32MP2 DWC3 xHCI USB controller glue Date: Sat, 22 Aug 2026 09:46:39 +0200 Message-ID: <20260822074816.548662-7-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260822074816.548662-1-marex@nabladev.com> References: <20260822074816.548662-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The ST STM32MP2 SoC contains one instance of DWC3 USB controller with glue logic wrapper around it controlled by syscon. Extend the generic DWC3 platform driver with ST STM32MP2 glue logic specifics. Signed-off-by: Marek Vasut --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Thinh Nguyen Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- V2: No change V3: - Use generic over-current-active-low --- drivers/usb/dwc3/dwc3-generic-plat.c | 44 ++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-g= eneric-plat.c index ca69ac0eb07ce..f670576511b59 100644 --- a/drivers/usb/dwc3/dwc3-generic-plat.c +++ b/drivers/usb/dwc3/dwc3-generic-plat.c @@ -22,6 +22,12 @@ #define EIC7700_HSP_AXI_LP_XM_CSYSREQ BIT(0) #define EIC7700_HSP_AXI_LP_XS_CSYSREQ BIT(16) =20 +#define STM32MP2_USB3DRCR_HOST_PORT_POWER_CONTROL_PRESENT BIT(0) +#define STM32MP2_USB3DRCR_OVRCUR_POLARITY BIT(1) +#define STM32MP2_USB3DRCR_VBUSEN_POLARITY BIT(2) +#define STM32MP2_USB3DRCR_USB2ONLYH BIT(3) +#define STM32MP2_USB3DRCR_USB2ONLYD BIT(4) + struct dwc3_generic { struct device *dev; struct dwc3 dwc; @@ -85,6 +91,38 @@ static int dwc3_spacemit_k1_init(struct dwc3_generic *dw= c3g) return 0; } =20 +static int dwc3_stm32mp25_init(struct dwc3_generic *dwc3g) +{ + struct device *dev =3D dwc3g->dev; + bool ovrcur_polarity_low =3D device_property_read_bool(dev, "over-current= -active-low"); + bool prt_pwr_ctrl =3D device_property_read_bool(dev, "st,enable-port-powe= r-control"); + bool usb2only_conf =3D device_property_match_string(dev, "phy-names", "us= b3-phy") < 0; + bool vbusen_polarity_low =3D device_property_read_bool(dev, "st,vbusen-ac= tive-low"); + struct regmap *regmap; + u32 drcr; + + regmap =3D syscon_regmap_lookup_by_phandle_args(dev->of_node, "st,syscfg"= , 1, &drcr); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "No st,syscfg phandle specifi= ed\n"); + + return regmap_update_bits(regmap, drcr, + STM32MP2_USB3DRCR_HOST_PORT_POWER_CONTROL_PRESENT | + STM32MP2_USB3DRCR_OVRCUR_POLARITY | + STM32MP2_USB3DRCR_VBUSEN_POLARITY | + STM32MP2_USB3DRCR_USB2ONLYD | + STM32MP2_USB3DRCR_USB2ONLYH, + FIELD_PREP(STM32MP2_USB3DRCR_HOST_PORT_POWER_CONTROL_PRESENT, + prt_pwr_ctrl) | + FIELD_PREP(STM32MP2_USB3DRCR_OVRCUR_POLARITY, + ovrcur_polarity_low) | + FIELD_PREP(STM32MP2_USB3DRCR_VBUSEN_POLARITY, + vbusen_polarity_low) | + FIELD_PREP(STM32MP2_USB3DRCR_USB2ONLYD, + !!usb2only_conf) | + FIELD_PREP(STM32MP2_USB3DRCR_USB2ONLYH, + !!usb2only_conf)); +} + static int dwc3_generic_probe(struct platform_device *pdev) { const struct dwc3_generic_config *plat_config; @@ -231,12 +269,18 @@ static const struct dwc3_generic_config eic7700_dwc3 = =3D { .properties =3D DWC3_DEFAULT_PROPERTIES, }; =20 +static const struct dwc3_generic_config stm32mp25_dwc3 =3D { + .init =3D dwc3_stm32mp25_init, + .properties =3D DWC3_DEFAULT_PROPERTIES, +}; + static const struct of_device_id dwc3_generic_of_match[] =3D { { .compatible =3D "spacemit,k1-dwc3", &spacemit_k1_dwc3}, { .compatible =3D "spacemit,k3-dwc3", }, { .compatible =3D "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3}, { .compatible =3D "eswin,eic7700-dwc3", &eic7700_dwc3}, { .compatible =3D "starfive,jhb100-dwc3", }, + { .compatible =3D "st,stm32mp25-dwc3", &stm32mp25_dwc3 }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, dwc3_generic_of_match); --=20 2.53.0 From nobody Mon Sep 28 11:39:22 2026 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2EB639E9BD; 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charset="utf-8" The st,stm32mp23-syscfg and st,stm32mp25-syscfg can have subnodes, which represent the USB 2.0 FEMTO-PHY. Turn the syscfg into "simple-mfd" so the PHYs would get populated by the OS. Signed-off-by: Marek Vasut --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Thinh Nguyen Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- V2: New patch V3: Fix the bindings --- .../bindings/arm/stm32/st,stm32-syscon.yaml | 24 +++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.ya= ml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index 95d2319afe235..4db4198c5dd7a 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -22,11 +22,12 @@ properties: - st,stm32mp151-pwr-mcu - st,stm32mp157-syscfg - st,stm32mp21-syscfg - - st,stm32mp23-syscfg - - st,stm32mp25-syscfg - const: syscon - items: - - const: st,stm32-tamp + - enum: + - st,stm32-tamp + - st,stm32mp23-syscfg + - st,stm32mp25-syscfg - const: syscon - const: simple-mfd =20 @@ -39,6 +40,17 @@ properties: "#clock-cells": const: 0 =20 + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + +patternProperties: + "^phy@[0-9a-f]+$": + type: object + $ref: /schemas/phy/st,stm32-usb2phy.yaml + required: - compatible - reg @@ -57,10 +69,14 @@ allOf: - if: properties: compatible: - const: st,stm32mp25-syscfg + enum: + - st,stm32mp23-syscfg + - st,stm32mp25-syscfg then: required: - "#clock-cells" + - "#address-cells" + - "#size-cells" =20 additionalProperties: false =20 --=20 2.53.0 From nobody Mon Sep 28 11:39:22 2026 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C0203905F4; Sat, 22 Aug 2026 07:49:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.251.229.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787384956; cv=none; b=HtpYt0xhNferfUDvvX/juR3X7TwxjOd0UGkRjbKHazjNVriQv7U8l+9KhksvArkjcKM1M5L3e5ocjGV8+6/brSSfE9iJtKLMnO47luxFCVk3AH1e4pLSNW8Zw6wbkjWl/hAxxgpYzCOU5eXaRoiMBYoQ2FyYLOExYM2qhYHRHCw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787384956; c=relaxed/simple; bh=oYGopDZtlez8Lg9IrQfwe3oP/GawgCa43UVMfMdy5sA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cY0fduhKDKokZvuqMw6PBfrEGdagXHxnpfmFiB7Wg0h4VcJhLYZQl0Dfn4BpeKjX12atjwLzmkmwLpjHd+lW4Wm+yJBhPMLGFN/EQ0toKRz4CxYrZdyR2ivQdxls8LqiFtwHETeb+R034KrZq2CEbj0eMoOkk2M5DPGRU3zF94s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com; spf=pass smtp.mailfrom=nabladev.com; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b=cbo9CniP; arc=none smtp.client-ip=178.251.229.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nabladev.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b="cbo9CniP" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 457FA11C81C; Sat, 22 Aug 2026 09:49:07 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1787384948; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=iBhqzMVK5zne1S+uuCopXVke1Xrx6/v2FxnVelrP7A4=; b=cbo9CniPneGqLQ+3ou3fWIwu7D3bQ+UoK6xdmhAy5rbbD3n1zUDQmDMRr+HBYmojY+MmXW vO+GsEvesHtYeWQSqgjCNyM4JSht8KPQNRpd50KBy1GfsNgqNf02yCiVzZMexAyi/PvgRH vJ/xa2rip71/W0+Pf/Vk2wZdH90e0thCcAcIW70ns0uuaAr3Txvy0DbD07t/qwwrSdrmJk hHjD57CoEzML5AbNWQfTojEBwBAD3cSNO4gpAZeSTJXoEOgLCRl3KfgNxBjYeGJ3tko6+t ri09T+/C0QsmHwOEnaorXApnHWzS1BR5HJEpAZ+k4Qc3xykyvP5kfIaTvQkWWw== From: Marek Vasut To: linux-usb@vger.kernel.org Cc: fabrice.gasnier@foss.st.com, Marek Vasut , Alexandre Torgue , Francois Choleau , Christian Bruel , Conor Dooley , Greg Kroah-Hartman , Krzysztof Kozlowski , Maxime Coquelin , Neil Armstrong , Pankaj Dev , Rahul Kumar , Rob Herring , Rosen Penev , Thinh Nguyen , Vinod Koul , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v3 8/9] arm64: dts: st: Add USB nodes on stm32mp231 Date: Sat, 22 Aug 2026 09:46:41 +0200 Message-ID: <20260822074816.548662-9-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260822074816.548662-1-marex@nabladev.com> References: <20260822074816.548662-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Add USB controller and PHY nodes to stm32mp231 DT. This includes two USB 2.0 FEMTO PHYs, USB 2.0 host controller and DWC3 DRD controller nodes. Co-developed-by: Alexandre Torgue Signed-off-by: Alexandre Torgue Co-developed-by: Francois Choleau Signed-off-by: Francois Choleau Signed-off-by: Marek Vasut --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Thinh Nguyen Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- V2: - Fix up Sob/Cdb lines - Move PHY into syscfg subnode - Turn st,stm32mp23-syscfg into simple-mfd - Use clock-cells =3D <1> to discern OSC and future PLL clock from the = PHY V3: - Drop combophy which is not present on MP23 - Describe OHCI clock as the CMN clock --- arch/arm64/boot/dts/st/stm32mp231.dtsi | 67 +++++++++++++++++++++++++- 1 file changed, 66 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/s= t/stm32mp231.dtsi index 4505fc0e3b537..314a514f31024 100644 --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include =20 / { #address-cells =3D <2>; @@ -862,6 +863,48 @@ stmmac_axi_config_1: stmmac-axi-config { snps,wr_osr_lmt =3D <0x7>; }; }; + + usbh_ohci: usb@482e0000 { + compatible =3D "generic-ohci"; + reg =3D <0x482e0000 0x1000>; + access-controllers =3D <&rifsc 63>; + clocks =3D <&usb2_phy1 1>, <&rcc CK_BUS_USB2OHCI>; + interrupts =3D ; + phys =3D <&usb2_phy1>; + phy-names =3D "usb"; + resets =3D <&rcc USBH_R>; + status =3D "disabled"; + }; + + usbh_ehci: usb@482f0000 { + compatible =3D "generic-ehci"; + reg =3D <0x482f0000 0x1000>; + access-controllers =3D <&rifsc 63>; + clocks =3D <&usb2_phy1 0>, <&rcc CK_BUS_USB2EHCI>; + companion =3D <&usbh_ohci>; + interrupts =3D ; + phys =3D <&usb2_phy1>; + phy-names =3D "usb"; + resets =3D <&rcc USBH_R>; + status =3D "disabled"; + }; + + usb3dr: usb@48300000 { + compatible =3D "st,stm32mp25-dwc3"; + reg =3D <0x48300000 0x100000>; + access-controllers =3D <&rifsc 66>; + clocks =3D <&rcc CK_KER_USB2PHY2>, + <&rcc CK_BUS_USB3DR>, + <&rcc CK_KER_USB2PHY2>; + clock-names =3D "ref", "bus_early", "suspend"; + interrupts =3D ; + maximum-speed =3D "high-speed"; + phys =3D <&usb2_phy2>; + phy-names =3D "usb2-phy"; + resets =3D <&rcc USB3DR_R>; + st,syscfg =3D <&syscfg 0x4800>; + status =3D "disabled"; + }; }; =20 bsec: efuse@44000000 { @@ -1062,9 +1105,31 @@ exti1: interrupt-controller@44220000 { }; =20 syscfg: syscon@44230000 { - compatible =3D "st,stm32mp23-syscfg", "syscon"; + compatible =3D "st,stm32mp23-syscfg", "syscon", "simple-mfd"; reg =3D <0x44230000 0x10000>; #clock-cells =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + usb2_phy1: phy@2400 { + compatible =3D "st,stm32mp25-usb2phy1"; + reg =3D <0x2400 0x24>; + #phy-cells =3D <0>; + #clock-cells =3D <1>; + clocks =3D <&rcc CK_KER_USB2PHY1>; + resets =3D <&rcc USB2PHY1_R>; + status =3D "disabled"; + }; + + usb2_phy2: phy@2800 { + compatible =3D "st,stm32mp25-usb2phy2"; + reg =3D <0x2800 0xc>; + #phy-cells =3D <0>; + #clock-cells =3D <1>; + clocks =3D <&rcc CK_KER_USB2PHY2EN>; + resets =3D <&rcc USB2PHY2_R>; + status =3D "disabled"; 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smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com; spf=pass smtp.mailfrom=nabladev.com; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b=i/SXzMS2; arc=none smtp.client-ip=178.251.229.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nabladev.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b="i/SXzMS2" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A91EB11C820; Sat, 22 Aug 2026 09:49:12 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1787384953; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=wof+pJXbG+zlMHLSCaXku6i83ZCIZasPbrJqZbEELpI=; b=i/SXzMS2497Cc0QdRlNDbeEU+Rjr90khaCqVDwmkNLiyuE4YbxeUlT36FVfeAn9tdD+kay QEDR0EjhKXcMG9HMOeYwNWe2FuUrX+qUeNMmIBUINrgTvJm/kCrmCrDtqb1n6Y1E0SwdLU QBkWiE8xiawG+heEtjif4+UF7C8Y1a9Epsvtl8CDLGrFkl3lp3hyeC+le5hwdhQqxRM1aT P8H4xOv+AEgw1iCj2NazF0Zf7VB27tgjwNxTsXlXvI7nGDS+BuLZFSv8anvYjRF35IhVlg l5qt2z9jH8fWY58WSCSm69gpA8cJGivp2zaGa0hGkPWP+FtbmikeuaYV5mcJiw== From: Marek Vasut To: linux-usb@vger.kernel.org Cc: fabrice.gasnier@foss.st.com, Pankaj Dev , Marek Vasut , Alexandre Torgue , Christian Bruel , Conor Dooley , Greg Kroah-Hartman , Krzysztof Kozlowski , Maxime Coquelin , Neil Armstrong , Rahul Kumar , Rob Herring , Rosen Penev , Thinh Nguyen , Vinod Koul , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v3 9/9] arm64: dts: st: Add USB nodes on stm32mp251 Date: Sat, 22 Aug 2026 09:46:42 +0200 Message-ID: <20260822074816.548662-10-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260822074816.548662-1-marex@nabladev.com> References: <20260822074816.548662-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" From: Pankaj Dev Add USB controller and PHY nodes to stm32mp251 DT. This includes two USB 2.0 FEMTO PHYs, USB 2.0 host controller and DWC3 DRD controller nodes. Signed-off-by: Pankaj Dev Co-developed-by: Marek Vasut Signed-off-by: Marek Vasut --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Thinh Nguyen Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- V2: - Fix up Sob/Cdb lines - Move PHY into syscfg subnode - Turn st,stm32mp25-syscfg into simple-mfd - Use clock-cells =3D <1> to discern OSC and future PLL clock from the = PHY V3: - Describe OHCI clock as the CMN clock - Fix up Sob/Cdb lines further --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 65 +++++++++++++++++++++++++- 1 file changed, 64 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 6e985f115b195..dd2f7ddd9b634 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1746,6 +1746,47 @@ stmmac_axi_config_1: stmmac-axi-config { }; }; =20 + usbh_ohci: usb@482e0000 { + compatible =3D "generic-ohci"; + reg =3D <0x482e0000 0x1000>; + access-controllers =3D <&rifsc 63>; + clocks =3D <&usb2_phy1 1>, <&rcc CK_BUS_USB2OHCI>; + interrupts =3D ; + phys =3D <&usb2_phy1>; + phy-names =3D "usb"; + resets =3D <&rcc USBH_R>; + status =3D "disabled"; + }; + + usbh_ehci: usb@482f0000 { + compatible =3D "generic-ehci"; + reg =3D <0x482f0000 0x1000>; + access-controllers =3D <&rifsc 63>; + clocks =3D <&usb2_phy1 0>, <&rcc CK_BUS_USB2EHCI>; + companion =3D <&usbh_ohci>; + interrupts =3D ; + phys =3D <&usb2_phy1>; + phy-names =3D "usb"; + resets =3D <&rcc USBH_R>; + status =3D "disabled"; + }; + + usb3dr: usb@48300000 { + compatible =3D "st,stm32mp25-dwc3"; + reg =3D <0x48300000 0x100000>; + access-controllers =3D <&rifsc 66>; + clocks =3D <&rcc CK_KER_USB2PHY2>, + <&rcc CK_BUS_USB3DR>, + <&rcc CK_KER_USB2PHY2>; + clock-names =3D "ref", "bus_early", "suspend"; + interrupts =3D ; + phys =3D <&usb2_phy2>, <&combophy PHY_TYPE_USB3>; + phy-names =3D "usb2-phy", "usb3-phy"; + resets =3D <&rcc USB3DR_R>; + st,syscfg =3D <&syscfg 0x4800>; + status =3D "disabled"; + }; + pcie_ep: pcie-ep@48400000 { compatible =3D "st,stm32mp25-pcie-ep"; reg =3D <0x48400000 0x100000>, @@ -2002,9 +2043,31 @@ exti1: interrupt-controller@44220000 { }; =20 syscfg: syscon@44230000 { - compatible =3D "st,stm32mp25-syscfg", "syscon"; + compatible =3D "st,stm32mp25-syscfg", "syscon", "simple-mfd"; reg =3D <0x44230000 0x10000>; #clock-cells =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + usb2_phy1: phy@2400 { + compatible =3D "st,stm32mp25-usb2phy1"; + reg =3D <0x2400 0x24>; + #phy-cells =3D <0>; + #clock-cells =3D <1>; + clocks =3D <&rcc CK_KER_USB2PHY1>; + resets =3D <&rcc USB2PHY1_R>; + status =3D "disabled"; + }; + + usb2_phy2: phy@2800 { + compatible =3D "st,stm32mp25-usb2phy2"; + reg =3D <0x2800 0xc>; + #phy-cells =3D <0>; + #clock-cells =3D <1>; + clocks =3D <&rcc CK_KER_USB2PHY2EN>; + resets =3D <&rcc USB2PHY2_R>; + status =3D "disabled"; + }; }; =20 pinctrl: pinctrl@44240000 { --=20 2.53.0