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Fri, 21 Aug 2026 13:48:46 -0700 (PDT) From: Bhargav Joshi Date: Sat, 22 Aug 2026 02:18:03 +0530 Subject: [PATCH] dt-bindings: pinctrl: ti,pinctrl-palmas: Convert to DT schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260822-ti-pinctrl-palmas-v1-1-a4d49e7f2dab@gmail.com> X-B4-Tracking: v=1; b=H4sIAAAAAAAC/x3MTQqAIBBA4avErBuo6YfqKtFCdKoBM9GIQLp70 vJbvJcgchCOMBUJAt8S5XQZdVmA3pXbGMVkA1XUVwMRXoJenL6CRa/soSIydz3TqBrTNpA7H3i V53/Oy/t+X6rHvGMAAAA= X-Change-ID: 20260822-ti-pinctrl-palmas-ee56e29a3d43 To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Laxman Dewangan Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, goledhruva@gmail.com, m-chawdhry@ti.com, daniel.baluta@gmail.com, simona.toaca@nxp.com, j.bhargav.u@gmail.com X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787345318; l=6098; i=j.bhargav.u@gmail.com; h=from:subject:message-id; bh=qHMHjHxt9qOFlhTACZWJ0m273uXcnrod6sFq22eDzR8=; b=j74mL6e9aZUj6abhaSI1AfjNlgDwwilM+qW6klRFeW8ZkeHUbsjPKpcQQjQz2yHprxjVj9hl4 kFlLWWrwY4QA0m0QZcZ1k9Czuj9c6rTAEypF0La72Oz/UEdvf8Ihwc6 X-Developer-Key: i=j.bhargav.u@gmail.com; a=ed25519; pk=IqNDwUZKECEA+n8wXctFLBbYL9NhFstZNbOznm/nX1k= Convert TI Palmas pin control text binding to DT schema. The legacy binding allowed any subnode name. Restrict them to standard prefixes to prevent the validator from accidentally evaluating standard integer properties (like phandle) as child nodes. Signed-off-by: Bhargav Joshi --- .../bindings/pinctrl/ti,palmas-pinctrl.yaml | 175 +++++++++++++++++= ++++ 1 file changed, 175 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/ti,palmas-pinctrl.ya= ml b/Documentation/devicetree/bindings/pinctrl/ti,palmas-pinctrl.yaml new file mode 100644 index 000000000000..c07e3a782ef0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ti,palmas-pinctrl.yaml @@ -0,0 +1,175 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ti,palmas-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI Palmas Pincontrol + +maintainers: + - Laxman Dewangan + +description: + The pins of Palmas device can be set on different option and provides + the configuration for Pull UP/DOWN, open drain etc. + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + enum: + - ti,palmas-pinctrl + - ti,tps65913-pinctrl + - ti,tps80036-pinctrl + + ti,palmas-enable-dvfs1: + type: boolean + description: + Enable DVFS1. Configure pins for DVFS1 mode. + Selection primary or secondary function associated to I2C2_SCL_SCE, + I2C2_SDA_SDO pin/pad for DVFS1 interface. + + ti,palmas-enable-dvfs2: + type: boolean + description: + Enable DVFS2. Configure pins for DVFS2 mode. + Selection primary or secondary function associated to GPADC_START + and SYSEN2 pin/pad for DVFS2 interface. + + ti,palmas-override-powerhold: + type: boolean + description: + This is applicable for PMICs for which GPIO7 is configured in POWERH= OLD + mode which has higher priority over DEV_ON bit and keeps the PMIC + supplies on even after the DEV_ON bit is turned off. This property e= nables + driver to over ride the POWERHOLD value to GPIO7 so as to turn off t= he PMIC + in power off scenarios. So for GPIO7 if ti,palmas-override-powerhold= is set + then the GPIO_7 field should never be muxed to anything else. + It should be set to POWERHOLD by default and only in case of + power off scenarios the driver will over ride the mux value. + +patternProperties: + '^(pinmux|pins?-[a-z0-9-]+)$': + type: object + additionalProperties: false + patternProperties: + '^(pin.*|gpio[0-9]+|vac|powergood|nreswarm|pwrdown|gpadc_start|reset= _in|nsleep|enable[12]|int)$': + type: object + allOf: + - $ref: /schemas/pinctrl/pinmux-node.yaml + - $ref: /schemas/pinctrl/pincfg-node.yaml + additionalProperties: false + properties: + pins: + items: + enum: + - gpio0 + - gpio1 + - gpio2 + - gpio3 + - gpio4 + - gpio5 + - gpio6 + - gpio7 + - gpio8 + - gpio9 + - gpio10 + - gpio11 + - gpio12 + - gpio13 + - gpio14 + - gpio15 + - vac + - powergood + - nreswarm + - pwrdown + - gpadc_start + - reset_in + - nsleep + - enable1 + - enable2 + - int + + function: + description: + Selects the mux function. There are 4 special functions opt0, + opt1, opt2 and opt3. If any of these functions is selected t= hen + directly pins register will be written with 0, 1, 2 or 3 + respectively if it is valid for that pin or list of pins. + enum: + - gpio + - led + - pwm + - regen + - sysen + - clk32kgaudio + - id + - vbus_det + - chrg_det + - vac + - vacok + - powergood + - usb_psel + - msecure + - pwrhold + - int + - nreswarm + - simrsto + - simrsti + - low_vbat + - wireless_chrg1 + - rcm + - pwrdown + - gpadc_start + - reset_in + - nsleep + - enable + - opt0 + - opt1 + - opt2 + - opt3 + + bias-disable: true + bias-pull-up: true + bias-pull-down: true + drive-open-drain: true + + required: + - pins + +required: + - compatible + +additionalProperties: false + +examples: + - | + pmic { + pinctrl { + compatible =3D "ti,tps65913-pinctrl"; + ti,palmas-enable-dvfs1; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&palmas_pins_state>; + + pinmux { + gpio0 { + pins =3D "gpio0"; + function =3D "id"; + bias-pull-up; + }; + + vac { + pins =3D "vac"; + function =3D "vacok"; + bias-pull-down; + }; + + gpio5 { + pins =3D "gpio5"; + function =3D "opt0"; + drive-open-drain =3D <1>; + }; + }; + }; + }; --- base-commit: 818bebeb63dd6bf5f4e07e145f6cdbace520a34c change-id: 20260822-ti-pinctrl-palmas-ee56e29a3d43 Best regards, --=20 Bhargav