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Fri, 21 Aug 2026 08:41:03 -0700 (PDT) From: Sreeshankar K To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, konradybcio@kernel.org, tglx@kernel.org, ulfh@kernel.org Cc: bmasney@redhat.com, radu@rendec.net, abel.vesa@oss.qualcomm.com, lpieralisi@kernel.org, quic_tdas@quicinc.com, danila@mainlining.org, davidwronek@gmail.com, mani@kernel.org, robimarko@gmail.com, linux@gurudas.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K , Krzysztof Kozlowski , Konrad Dybcio , Dmitry Baryshkov Subject: [PATCH v4 01/13] dt-bindings: arm: qcom,ids: Add SoC ID for SM7250 Date: Fri, 21 Aug 2026 15:40:18 +0000 Message-ID: <20260821154030.2514-2-sreeshankar0910@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821154030.2514-1-sreeshankar0910@gmail.com> References: <20260821154030.2514-1-sreeshankar0910@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the ID for the Qualcomm SM7250 SoC. Signed-off-by: Sreeshankar K Acked-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- include/dt-bindings/arm/qcom,ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/q= com,ids.h index 2cf433f61..b63e4a0b8 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -209,6 +209,7 @@ #define QCOM_ID_IPQ8172 397 #define QCOM_ID_IPQ8173 398 #define QCOM_ID_IPQ8174 399 +#define QCOM_ID_SM7250 400 #define QCOM_ID_IPQ6018 402 #define QCOM_ID_IPQ6028 403 #define QCOM_ID_SDM429W 416 --=20 2.43.0 From nobody Mon Sep 28 12:33:39 2026 Received: from mail-pj1-f43.google.com (mail-pj1-f43.google.com [209.85.216.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A710336D51F for ; Fri, 21 Aug 2026 15:41:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Add SoC ID for Qualcomm SM7250 SoC. Signed-off-by: Sreeshankar K Reviewed-by: Dmitry Baryshkov Reviewed-by: Abel Vesa --- drivers/soc/qcom/socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 1836e226a..63ee5cd56 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -450,6 +450,7 @@ static const struct soc_id soc_id[] =3D { { qcom_board_id(IPQ8172) }, { qcom_board_id(IPQ8173) }, { qcom_board_id(IPQ8174) }, + { qcom_board_id(SM7250) }, { qcom_board_id(IPQ6018) }, { qcom_board_id(IPQ6028) }, { qcom_board_id(SDM429W) }, --=20 2.43.0 From nobody Mon Sep 28 12:33:39 2026 Received: from mail-pj1-f52.google.com (mail-pj1-f52.google.com [209.85.216.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E7C842047E for ; Fri, 21 Aug 2026 15:41:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.52 ARC-Seal: i=1; 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Fri, 21 Aug 2026 08:41:23 -0700 (PDT) Received: from localhost.localdomain ([152.58.217.163]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1416ae5f1ffsm42903185c88.13.2026.08.21.08.41.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 08:41:23 -0700 (PDT) From: Sreeshankar K To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, konradybcio@kernel.org, tglx@kernel.org, ulfh@kernel.org Cc: bmasney@redhat.com, radu@rendec.net, abel.vesa@oss.qualcomm.com, lpieralisi@kernel.org, quic_tdas@quicinc.com, danila@mainlining.org, davidwronek@gmail.com, mani@kernel.org, robimarko@gmail.com, linux@gurudas.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K , Krzysztof Kozlowski Subject: [PATCH v4 03/13] dt-bindings: clock: Add SM7250 global clock controller Date: Fri, 21 Aug 2026 15:40:20 +0000 Message-ID: <20260821154030.2514-4-sreeshankar0910@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821154030.2514-1-sreeshankar0910@gmail.com> References: <20260821154030.2514-1-sreeshankar0910@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree bindings for global clock controller on SM7250 SoC. Signed-off-by: Sreeshankar K Reviewed-by: Krzysztof Kozlowski --- Dependencies: This commit depends on the following patch: > [PATCH] dt-bindings: clock: qcom,sm6375-gcc: Merge SM7150 into SM6375 Link: https://lore.kernel.org/linux-arm-msm/20260817082457.64797-2-krzyszto= f.kozlowski@oss.qualcomm.com .../bindings/clock/qcom,sm6375-gcc.yaml | 4 +- include/dt-bindings/clock/qcom,sm7250-gcc.h | 163 ++++++++++++++++++ 2 files changed, 166 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/clock/qcom,sm7250-gcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml b= /Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml index b4ad2ad14..39a2d2839 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml @@ -4,13 +4,14 @@ $id: http://devicetree.org/schemas/clock/qcom,sm6375-gcc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Qualcomm Global Clock & Reset Controller on SM6375 and SM7150 +title: Qualcomm Global Clock & Reset Controller on SM6375, SM7150 and SM72= 50 =20 maintainers: - Konrad Dybcio - Bjorn Andersson - Danila Tikhonov - David Wronek + - Sreeshankar K =20 description: | Qualcomm global clock control module provides the clocks, resets and pow= er @@ -26,6 +27,7 @@ properties: enum: - qcom,sm6375-gcc - qcom,sm7150-gcc + - qcom,sm7250-gcc =20 clocks: items: diff --git a/include/dt-bindings/clock/qcom,sm7250-gcc.h b/include/dt-bindi= ngs/clock/qcom,sm7250-gcc.h new file mode 100644 index 000000000..765fdc38f --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm7250-gcc.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2026, Sreeshankar K + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM7250_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SM7250_H + +/* GCC clocks */ +#define GPLL0 0 +#define GPLL0_OUT_EVEN 1 +#define GPLL6 2 +#define GPLL9 3 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 4 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 5 +#define GCC_BOOT_ROM_AHB_CLK 6 +#define GCC_CAMERA_AHB_CLK 7 +#define GCC_CAMERA_HF_AXI_CLK 8 +#define GCC_CAMERA_SF_AXI_CLK 9 +#define GCC_CAMERA_XO_CLK 10 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 11 +#define GCC_CPUSS_AHB_CLK 12 +#define GCC_CPUSS_AHB_CLK_SRC 13 +#define GCC_CPUSS_GNOC_CLK 14 +#define GCC_CPUSS_RBCPR_CLK 15 +#define GCC_DDRSS_GPU_AXI_CLK 16 +#define GCC_DISP_GPLL0_CLK_SRC 17 +#define GCC_DISP_AHB_CLK 18 +#define GCC_DISP_HF_AXI_CLK 19 +#define GCC_DISP_SF_AXI_CLK 20 +#define GCC_DISP_XO_CLK 21 +#define GCC_GP1_CLK 22 +#define GCC_GP1_CLK_SRC 23 +#define GCC_GP2_CLK 24 +#define GCC_GP2_CLK_SRC 25 +#define GCC_GP3_CLK 26 +#define GCC_GP3_CLK_SRC 27 +#define GCC_GPU_CFG_AHB_CLK 28 +#define GCC_GPU_GPLL0_CLK_SRC 29 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 30 +#define GCC_GPU_IREF_CLK 31 +#define GCC_GPU_MEMNOC_GFX_CLK 32 +#define GCC_GPU_SNOC_DVM_GFX_CLK 33 +#define GCC_NPU_AXI_CLK 34 +#define GCC_NPU_BWMON2_AXI_CLK 35 +#define GCC_NPU_BWMON_AXI_CLK 36 +#define GCC_NPU_BWMON_CFG_AHB_CLK 37 +#define GCC_NPU_CFG_AHB_CLK 38 +#define GCC_NPU_DMA_CLK 39 +#define GCC_NPU_GPLL0_CLK_SRC 40 +#define GCC_NPU_GPLL0_DIV_CLK_SRC 41 +#define GCC_PDM2_CLK 42 +#define GCC_PDM2_CLK_SRC 43 +#define GCC_PDM_AHB_CLK 44 +#define GCC_PDM_XO4_CLK 45 +#define GCC_PRNG_AHB_CLK 46 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 47 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 48 +#define GCC_QMIP_DISP_AHB_CLK 49 +#define GCC_QMIP_RT_DISP_AHB_CLK 50 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 51 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 52 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 53 +#define GCC_QUPV3_WRAP0_CORE_CLK 54 +#define GCC_QUPV3_WRAP0_S0_CLK 55 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 56 +#define GCC_QUPV3_WRAP0_S1_CLK 57 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 58 +#define GCC_QUPV3_WRAP0_S2_CLK 59 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 60 +#define GCC_QUPV3_WRAP0_S3_CLK 61 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 62 +#define GCC_QUPV3_WRAP0_S4_CLK 63 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 64 +#define GCC_QUPV3_WRAP0_S5_CLK 65 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 66 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 67 +#define GCC_QUPV3_WRAP1_CORE_CLK 68 +#define GCC_QUPV3_WRAP1_S0_CLK 69 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 70 +#define GCC_QUPV3_WRAP1_S1_CLK 71 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 72 +#define GCC_QUPV3_WRAP1_S2_CLK 73 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 74 +#define GCC_QUPV3_WRAP1_S3_CLK 75 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 76 +#define GCC_QUPV3_WRAP1_S4_CLK 77 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 78 +#define GCC_QUPV3_WRAP1_S5_CLK 79 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 80 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 81 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 82 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 83 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 84 +#define GCC_SDCC1_AHB_CLK 85 +#define GCC_SDCC1_APPS_CLK 86 +#define GCC_SDCC1_APPS_CLK_SRC 87 +#define GCC_SDCC1_ICE_CORE_CLK 88 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 89 +#define GCC_SDCC2_AHB_CLK 90 +#define GCC_SDCC2_APPS_CLK 91 +#define GCC_SDCC2_APPS_CLK_SRC 92 +#define GCC_SDCC4_AHB_CLK 93 +#define GCC_SDCC4_APPS_CLK 94 +#define GCC_SDCC4_APPS_CLK_SRC 95 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 96 +#define GCC_UFS_1X_CLKREF_CLK 97 +#define GCC_UFS_PHY_AHB_CLK 98 +#define GCC_UFS_PHY_AXI_CLK 99 +#define GCC_UFS_PHY_AXI_CLK_SRC 100 +#define GCC_UFS_PHY_ICE_CORE_CLK 101 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 102 +#define GCC_UFS_PHY_PHY_AUX_CLK 103 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 104 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 105 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 106 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 107 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 108 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 109 +#define GCC_USB30_PRIM_MASTER_CLK 110 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 111 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 112 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 113 +#define GCC_USB30_PRIM_SLEEP_CLK 114 +#define GCC_USB3_PRIM_CLKREF_CLK 115 +#define GCC_USB3_PRIM_PHY_AUX_CLK 116 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 117 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 118 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 119 +#define GCC_VIDEO_AHB_CLK 120 +#define GCC_VIDEO_AXI_CLK 121 +#define GCC_VIDEO_XO_CLK 122 + +/* GCC resets */ +#define GCC_DPM_BCR 0 +#define GCC_GPU_BCR 1 +#define GCC_MMSS_BCR 2 +#define GCC_NPU_BWMON_BCR 3 +#define GCC_NPU_BCR 4 +#define GCC_PDM_BCR 5 +#define GCC_PRNG_BCR 6 +#define GCC_QUPV3_WRAPPER_0_BCR 7 +#define GCC_QUPV3_WRAPPER_1_BCR 8 +#define GCC_QUSB2PHY_PRIM_BCR 9 +#define GCC_SDCC1_BCR 10 +#define GCC_SDCC2_BCR 11 +#define GCC_SDCC4_BCR 12 +#define GCC_UFS_PHY_BCR 13 +#define GCC_USB30_PRIM_BCR 14 +#define GCC_USB3_DP_PHY_PRIM_BCR 15 +#define GCC_USB3_PHY_PRIM_BCR 16 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mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, konradybcio@kernel.org, tglx@kernel.org, ulfh@kernel.org Cc: bmasney@redhat.com, radu@rendec.net, abel.vesa@oss.qualcomm.com, lpieralisi@kernel.org, quic_tdas@quicinc.com, danila@mainlining.org, davidwronek@gmail.com, mani@kernel.org, robimarko@gmail.com, linux@gurudas.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K Subject: [PATCH v4 04/13] clk: qcom: Add Global Clock Controller (GCC) driver for SM7250 Date: Fri, 21 Aug 2026 15:40:21 +0000 Message-ID: <20260821154030.2514-5-sreeshankar0910@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821154030.2514-1-sreeshankar0910@gmail.com> References: <20260821154030.2514-1-sreeshankar0910@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the global clock controller found on SM7250 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by: Sreeshankar K --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-sm7250.c | 2274 +++++++++++++++++++++++++++++++++ 3 files changed, 2284 insertions(+) create mode 100644 drivers/clk/qcom/gcc-sm7250.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 7d84c2f1d..532d8f002 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1416,6 +1416,15 @@ config SM_GCC_7150 Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, SD/UFS, PCIe etc. =20 +config SM_GCC_7250 + tristate "SM7250 Global Clock Controller" + depends on ARM64 || COMPILE_TEST + select QCOM_GDSC + help + Support for the global clock controller on SM7250 devices. + Say Y if you want to use peripheral devices such as UART, + SPI, I2C, USB, SD/UFS etc. + config SM_GCC_MILOS tristate "Milos Global Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 58f9a5eb6..18414089c 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -174,6 +174,7 @@ obj-$(CONFIG_SM_GCC_6125) +=3D gcc-sm6125.o obj-$(CONFIG_SM_GCC_6350) +=3D gcc-sm6350.o obj-$(CONFIG_SM_GCC_6375) +=3D gcc-sm6375.o obj-$(CONFIG_SM_GCC_7150) +=3D gcc-sm7150.o +obj-$(CONFIG_SM_GCC_7250) +=3D gcc-sm7250.o obj-$(CONFIG_SM_GCC_8150) +=3D gcc-sm8150.o obj-$(CONFIG_SM_GCC_8250) +=3D gcc-sm8250.o obj-$(CONFIG_SM_GCC_8350) +=3D gcc-sm8350.o diff --git a/drivers/clk/qcom/gcc-sm7250.c b/drivers/clk/qcom/gcc-sm7250.c new file mode 100644 index 000000000..eb68a1b54 --- /dev/null +++ b/drivers/clk/qcom/gcc-sm7250.c @@ -0,0 +1,2274 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2026, Sreeshankar K + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_EVEN, + P_GPLL0_OUT_MAIN, + P_GPLL6_OUT_MAIN, + P_GPLL9_OUT_MAIN, + P_SLEEP_CLK, +}; + +static struct clk_alpha_pll gpll0 =3D { + .offset =3D 0x0, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpll0", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpll0_out_even[] =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll0_out_even =3D { + .offset =3D 0x0, + .post_div_shift =3D 8, + .post_div_table =3D post_div_table_gpll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_gpll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gpll0_out_even", + .parent_hws =3D (const struct clk_hw*[]){ + &gpll0.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_lucid_ops, + }, +}; + +static struct clk_alpha_pll gpll6 =3D { + .offset =3D 0x13000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(6), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpll6", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll9 =3D { + .offset =3D 0x1c000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(9), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpll9", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ops, + }, + }, +}; + +static const struct parent_map gcc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct clk_parent_data gcc_parent_data_0_ao[] =3D { + { .index =3D DT_BI_TCXO_AO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_SLEEP_CLK, 5 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data gcc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL6_OUT_MAIN, 2 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll6.clkr.hw }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL9_OUT_MAIN, 2 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll9.clkr.hw }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_5[] =3D { + { P_BI_TCXO, 0 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_5[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_cpuss_ahb_clk_src =3D { + .cmd_rcgr =3D 0x48010, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_cpuss_ahb_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_cpuss_ahb_clk_src", + .parent_data =3D gcc_parent_data_0_ao, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0_ao), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_gp1_clk_src =3D { + .cmd_rcgr =3D 0x64004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gp1_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_gp2_clk_src =3D { + .cmd_rcgr =3D 0x65004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gp2_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_gp3_clk_src =3D { + .cmd_rcgr =3D 0x66004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gp3_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] =3D { + F(9600000, P_BI_TCXO, 2, 0, 0), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pdm2_clk_src =3D { + .cmd_rcgr =3D 0x33010, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pdm2_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_pdm2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] =3D { + F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), + F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), + F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), + F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), + F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), + F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), + F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), + F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), + F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), + F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), + F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s0_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src =3D { + .cmd_rcgr =3D 0x17010, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s1_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src =3D { + .cmd_rcgr =3D 0x17140, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s1_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src =3D { + .cmd_rcgr =3D 0x17270, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s3_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src =3D { + .cmd_rcgr =3D 0x173a0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s4_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src =3D { + .cmd_rcgr =3D 0x174d0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s4_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s5_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src =3D { + .cmd_rcgr =3D 0x17600, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s5_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s0_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src =3D { + .cmd_rcgr =3D 0x18010, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s1_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src =3D { + .cmd_rcgr =3D 0x18140, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s1_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src =3D { + .cmd_rcgr =3D 0x18270, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s3_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src =3D { + .cmd_rcgr =3D 0x183a0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s4_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src =3D { + .cmd_rcgr =3D 0x184d0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s4_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s5_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src =3D { + .cmd_rcgr =3D 0x18600, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s5_clk_src_init, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] =3D { + F(144000, P_BI_TCXO, 16, 3, 25), + F(400000, P_BI_TCXO, 12, 1, 4), + F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3), + F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), + F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_apps_clk_src =3D { + .cmd_rcgr =3D 0x26024, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_sdcc1_apps_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc1_apps_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .flags =3D CLK_OPS_PARENT_ENABLE, + .ops =3D &clk_rcg2_floor_ops, + }, +}; + + +static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] =3D { + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src =3D { + .cmd_rcgr =3D 0x2600c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_sdcc1_ice_core_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc1_ice_core_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_OPS_PARENT_ENABLE, + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] =3D { + F(400000, P_BI_TCXO, 12, 1, 4), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc2_apps_clk_src =3D { + .cmd_rcgr =3D 0x1400c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_4, + .freq_tbl =3D ftbl_gcc_sdcc2_apps_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc2_apps_clk_src", + .parent_data =3D gcc_parent_data_4, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_4), + .flags =3D CLK_OPS_PARENT_ENABLE, + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] =3D { + F(400000, P_BI_TCXO, 12, 1, 4), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc4_apps_clk_src =3D { + .cmd_rcgr =3D 0x1600c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_sdcc4_apps_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc4_apps_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] =3D { + F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_axi_clk_src =3D { + .cmd_rcgr =3D 0x77024, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_ufs_phy_axi_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_axi_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] =3D { + F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), + F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src =3D { + .cmd_rcgr =3D 0x7706c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_ufs_phy_ice_core_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_ice_core_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x770a0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_ufs_phy_phy_aux_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] =3D { + F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), + F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src =3D { + .cmd_rcgr =3D 0x77084, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_ufs_phy_unipro_core_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_unipro_core_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] =3D { + F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), + F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb30_prim_master_clk_src =3D { + .cmd_rcgr =3D 0xf020, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_usb30_prim_master_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb30_prim_master_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src =3D { + .cmd_rcgr =3D 0xf038, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_ufs_phy_phy_aux_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb30_prim_mock_utmi_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0xf064, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_5, + .freq_tbl =3D ftbl_gcc_ufs_phy_phy_aux_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb3_prim_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_5, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_5), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_aggre_ufs_phy_axi_clk =3D { + .halt_reg =3D 0x770cc, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x770cc, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x770cc, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_aggre_ufs_phy_axi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_usb3_prim_axi_clk =3D { + .halt_reg =3D 0xf080, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xf080, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_aggre_usb3_prim_axi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk =3D { + .halt_reg =3D 0x38004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x38004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(10), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_boot_rom_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camera_hf_axi_clk =3D { + .halt_reg =3D 0xb028, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb028, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camera_hf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camera_sf_axi_clk =3D { + .halt_reg =3D 0xb02c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb02c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camera_sf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk =3D { + .halt_reg =3D 0xf07c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xf07c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_cfg_noc_usb3_prim_axi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cpuss_gnoc_clk =3D { + .halt_reg =3D 0x48064, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(29), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_cpuss_gnoc_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cpuss_rbcpr_clk =3D { + .halt_reg =3D 0x48004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x48004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_cpuss_rbcpr_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ddrss_gpu_axi_clk =3D { + .halt_reg =3D 0x71154, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x71154, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ddrss_gpu_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_gpll0_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(20), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_disp_gpll0_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gpll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_hf_axi_clk =3D { + .halt_reg =3D 0xb030, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb030, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_disp_hf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_sf_axi_clk =3D { + .halt_reg =3D 0xb034, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb034, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_disp_sf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk =3D { + .halt_reg =3D 0x64000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x64000, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gp1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_gp1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk =3D { + .halt_reg =3D 0x65000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x65000, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gp2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_gp2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp3_clk =3D { + .halt_reg =3D 0x66000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x66000, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gp3_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_gp3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(15), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gpu_gpll0_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gpll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_div_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(16), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gpu_gpll0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gpll0_out_even.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_iref_clk =3D { + .halt_reg =3D 0x8c014, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8c014, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gpu_iref_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_memnoc_gfx_clk =3D { + .halt_reg =3D 0x7100c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7100c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gpu_memnoc_gfx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk =3D { + .halt_reg =3D 0x71018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x71018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gpu_snoc_dvm_gfx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_axi_clk =3D { + .halt_reg =3D 0x4d008, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4d008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_npu_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_bwmon2_axi_clk =3D { + .halt_reg =3D 0x7000c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7000c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_npu_bwmon2_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_bwmon_axi_clk =3D { + .halt_reg =3D 0x70008, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x70008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_npu_bwmon_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_dma_clk =3D { + .halt_reg =3D 0x4d00c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4d00c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_npu_dma_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_gpll0_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(18), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_npu_gpll0_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gpll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_gpll0_div_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(19), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_npu_gpll0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gpll0_out_even.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm2_clk =3D { + .halt_reg =3D 0x3300c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3300c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_pdm2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_pdm2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_ahb_clk =3D { + .halt_reg =3D 0x33004, + .halt_check =3D BRANCH_HALT, + .hwcg_reg =3D 0x33004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x33004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_pdm_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_xo4_clk =3D { + .halt_reg =3D 0x33008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x33008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_pdm_xo4_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_prng_ahb_clk =3D { + .halt_reg =3D 0x34004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(13), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_prng_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_camera_nrt_ahb_clk =3D { + .halt_reg =3D 0xb018, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xb018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xb018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qmip_camera_nrt_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_camera_rt_ahb_clk =3D { + .halt_reg =3D 0xb01c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xb01c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xb01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qmip_camera_rt_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_disp_ahb_clk =3D { + .halt_reg =3D 0xb020, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xb020, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xb020, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qmip_disp_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_rt_disp_ahb_clk =3D { + .halt_reg =3D 0xb07c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xb07c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xb07c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qmip_rt_disp_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_video_cvp_ahb_clk =3D { + .halt_reg =3D 0xb010, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xb010, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xb010, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qmip_video_cvp_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_video_vcodec_ahb_clk =3D { + .halt_reg =3D 0xb014, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xb014, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xb014, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qmip_video_vcodec_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_2x_clk =3D { + .halt_reg =3D 0x23008, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(9), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_core_2x_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_clk =3D { + .halt_reg =3D 0x23000, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(8), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_core_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s0_clk =3D { + .halt_reg =3D 0x1700c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(10), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_s0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s1_clk =3D { + .halt_reg =3D 0x1713c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(11), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_s1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s2_clk =3D { + .halt_reg =3D 0x1726c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(12), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_s2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s3_clk =3D { + .halt_reg =3D 0x1739c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(13), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_s3_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s4_clk =3D { + .halt_reg =3D 0x174cc, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(14), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_s4_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s5_clk =3D { + .halt_reg =3D 0x175fc, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(15), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_s5_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_core_2x_clk =3D { + .halt_reg =3D 0x23140, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(18), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_core_2x_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_core_clk =3D { + .halt_reg =3D 0x23138, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(19), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_core_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s0_clk =3D { + .halt_reg =3D 0x1800c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(22), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_s0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s1_clk =3D { + .halt_reg =3D 0x1813c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(23), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_s1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s2_clk =3D { + .halt_reg =3D 0x1826c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(24), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_s2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s3_clk =3D { + .halt_reg =3D 0x1839c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(25), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_s3_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s4_clk =3D { + .halt_reg =3D 0x184cc, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(26), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_s4_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s5_clk =3D { + .halt_reg =3D 0x185fc, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(27), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_s5_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk =3D { + .halt_reg =3D 0x17004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(6), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap_0_m_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk =3D { + .halt_reg =3D 0x17008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x17008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(7), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap_0_s_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk =3D { + .halt_reg =3D 0x18004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(20), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap_1_m_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk =3D { + .halt_reg =3D 0x18008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x18008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(21), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap_1_s_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ahb_clk =3D { + .halt_reg =3D 0x26004, + .halt_check =3D BRANCH_HALT, + .hwcg_reg =3D 0x26004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x26004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc1_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_apps_clk =3D { + .halt_reg =3D 0x26008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x26008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc1_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_sdcc1_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ice_core_clk =3D { + .halt_reg =3D 0x2603c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2603c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc1_ice_core_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_sdcc1_ice_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_ahb_clk =3D { + .halt_reg =3D 0x14008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x14008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc2_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_apps_clk =3D { + .halt_reg =3D 0x14004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x14004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc2_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_sdcc2_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc4_ahb_clk =3D { + .halt_reg =3D 0x16008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x16008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc4_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc4_apps_clk =3D { + .halt_reg =3D 0x16004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x16004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc4_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_sdcc4_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_1x_clkref_clk =3D { + .halt_reg =3D 0x8c000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8c000, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_1x_clkref_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_ahb_clk =3D { + .halt_reg =3D 0x77018, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x77018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x77018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_axi_clk =3D { + .halt_reg =3D 0x77010, + .halt_check =3D BRANCH_HALT, + .hwcg_reg =3D 0x77010, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x77010, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_axi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_ice_core_clk =3D { + .halt_reg =3D 0x77064, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x77064, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x77064, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_ice_core_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_ice_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_phy_aux_clk =3D { + .halt_reg =3D 0x7709c, + .halt_check =3D BRANCH_HALT, + .hwcg_reg =3D 0x7709c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7709c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk =3D { + .halt_reg =3D 0x77020, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x77020, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_rx_symbol_0_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk =3D { + .halt_reg =3D 0x770b8, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x770b8, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_rx_symbol_1_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk =3D { + .halt_reg =3D 0x7701c, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x7701c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_tx_symbol_0_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_unipro_core_clk =3D { + .halt_reg =3D 0x7705c, + .halt_check =3D BRANCH_HALT, + .hwcg_reg =3D 0x7705c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7705c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_unipro_core_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_master_clk =3D { + .halt_reg =3D 0xf010, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xf010, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb30_prim_master_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_mock_utmi_clk =3D { + .halt_reg =3D 0xf01c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xf01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb30_prim_mock_utmi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_sleep_clk =3D { + .halt_reg =3D 0xf018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xf018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb30_prim_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_clkref_clk =3D { + .halt_reg =3D 0x8c010, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8c010, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb3_prim_clkref_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_aux_clk =3D { + .halt_reg =3D 0xf054, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xf054, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb3_prim_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_com_aux_clk =3D { + .halt_reg =3D 0xf058, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xf058, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb3_prim_phy_com_aux_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_pipe_clk =3D { + .halt_reg =3D 0xf05c, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0xf05c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb3_prim_phy_pipe_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_axi_clk =3D { + .halt_reg =3D 0xb080, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb080, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_video_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc ufs_phy_gdsc =3D { + .gdscr =3D 0x77004, + .pd =3D { + .name =3D "ufs_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc usb30_prim_gdsc =3D { + .gdscr =3D 0xf004, + .pd =3D { + .name =3D "usb30_prim_gdsc", + }, + .pwrsts =3D PWRSTS_RET_ON, +}; + +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc =3D { + .gdscr =3D 0x7d050, + .pd =3D { + .name =3D "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D VOTABLE, +}; + +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc =3D { + .gdscr =3D 0x7d058, + .pd =3D { + .name =3D "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D VOTABLE, +}; + +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc =3D { + .gdscr =3D 0x7d054, + .pd =3D { + .name =3D "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D VOTABLE, +}; + +static struct clk_regmap *gcc_sm7250_clocks[] =3D { + [GCC_AGGRE_UFS_PHY_AXI_CLK] =3D &gcc_aggre_ufs_phy_axi_clk.clkr, + [GCC_AGGRE_USB3_PRIM_AXI_CLK] =3D &gcc_aggre_usb3_prim_axi_clk.clkr, + [GCC_BOOT_ROM_AHB_CLK] =3D &gcc_boot_rom_ahb_clk.clkr, + [GCC_CAMERA_HF_AXI_CLK] =3D &gcc_camera_hf_axi_clk.clkr, + [GCC_CAMERA_SF_AXI_CLK] =3D &gcc_camera_sf_axi_clk.clkr, + [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] =3D &gcc_cfg_noc_usb3_prim_axi_clk.clkr, + [GCC_CPUSS_AHB_CLK_SRC] =3D &gcc_cpuss_ahb_clk_src.clkr, + [GCC_CPUSS_GNOC_CLK] =3D &gcc_cpuss_gnoc_clk.clkr, + [GCC_CPUSS_RBCPR_CLK] =3D &gcc_cpuss_rbcpr_clk.clkr, + [GCC_DDRSS_GPU_AXI_CLK] =3D &gcc_ddrss_gpu_axi_clk.clkr, + [GCC_DISP_GPLL0_CLK_SRC] =3D &gcc_disp_gpll0_clk_src.clkr, + [GCC_DISP_HF_AXI_CLK] =3D &gcc_disp_hf_axi_clk.clkr, + [GCC_DISP_SF_AXI_CLK] =3D &gcc_disp_sf_axi_clk.clkr, + [GCC_GP1_CLK] =3D &gcc_gp1_clk.clkr, + [GCC_GP1_CLK_SRC] =3D &gcc_gp1_clk_src.clkr, + [GCC_GP2_CLK] =3D &gcc_gp2_clk.clkr, + [GCC_GP2_CLK_SRC] =3D &gcc_gp2_clk_src.clkr, + [GCC_GP3_CLK] =3D &gcc_gp3_clk.clkr, + [GCC_GP3_CLK_SRC] =3D &gcc_gp3_clk_src.clkr, + [GCC_GPU_GPLL0_CLK_SRC] =3D &gcc_gpu_gpll0_clk_src.clkr, + [GCC_GPU_GPLL0_DIV_CLK_SRC] =3D &gcc_gpu_gpll0_div_clk_src.clkr, + [GCC_GPU_IREF_CLK] =3D &gcc_gpu_iref_clk.clkr, + [GCC_GPU_MEMNOC_GFX_CLK] =3D &gcc_gpu_memnoc_gfx_clk.clkr, + [GCC_GPU_SNOC_DVM_GFX_CLK] =3D &gcc_gpu_snoc_dvm_gfx_clk.clkr, + [GCC_NPU_AXI_CLK] =3D &gcc_npu_axi_clk.clkr, + [GCC_NPU_BWMON2_AXI_CLK] =3D &gcc_npu_bwmon2_axi_clk.clkr, + [GCC_NPU_BWMON_AXI_CLK] =3D &gcc_npu_bwmon_axi_clk.clkr, + [GCC_NPU_DMA_CLK] =3D &gcc_npu_dma_clk.clkr, + [GCC_NPU_GPLL0_CLK_SRC] =3D &gcc_npu_gpll0_clk_src.clkr, + [GCC_NPU_GPLL0_DIV_CLK_SRC] =3D &gcc_npu_gpll0_div_clk_src.clkr, + [GCC_PDM2_CLK] =3D &gcc_pdm2_clk.clkr, + [GCC_PDM2_CLK_SRC] =3D &gcc_pdm2_clk_src.clkr, + [GCC_PDM_AHB_CLK] =3D &gcc_pdm_ahb_clk.clkr, + [GCC_PDM_XO4_CLK] =3D &gcc_pdm_xo4_clk.clkr, + [GCC_PRNG_AHB_CLK] =3D &gcc_prng_ahb_clk.clkr, + [GCC_QMIP_CAMERA_NRT_AHB_CLK] =3D &gcc_qmip_camera_nrt_ahb_clk.clkr, + [GCC_QMIP_CAMERA_RT_AHB_CLK] =3D &gcc_qmip_camera_rt_ahb_clk.clkr, + [GCC_QMIP_DISP_AHB_CLK] =3D &gcc_qmip_disp_ahb_clk.clkr, + [GCC_QMIP_RT_DISP_AHB_CLK] =3D &gcc_qmip_rt_disp_ahb_clk.clkr, + [GCC_QMIP_VIDEO_CVP_AHB_CLK] =3D &gcc_qmip_video_cvp_ahb_clk.clkr, + [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] =3D &gcc_qmip_video_vcodec_ahb_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_2X_CLK] =3D &gcc_qupv3_wrap0_core_2x_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_CLK] =3D &gcc_qupv3_wrap0_core_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK] =3D &gcc_qupv3_wrap0_s0_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK_SRC] =3D &gcc_qupv3_wrap0_s0_clk_src.clkr, + [GCC_QUPV3_WRAP0_S1_CLK] =3D &gcc_qupv3_wrap0_s1_clk.clkr, + [GCC_QUPV3_WRAP0_S1_CLK_SRC] =3D &gcc_qupv3_wrap0_s1_clk_src.clkr, + [GCC_QUPV3_WRAP0_S2_CLK] =3D &gcc_qupv3_wrap0_s2_clk.clkr, + [GCC_QUPV3_WRAP0_S2_CLK_SRC] =3D &gcc_qupv3_wrap0_s2_clk_src.clkr, + [GCC_QUPV3_WRAP0_S3_CLK] =3D &gcc_qupv3_wrap0_s3_clk.clkr, + [GCC_QUPV3_WRAP0_S3_CLK_SRC] =3D &gcc_qupv3_wrap0_s3_clk_src.clkr, + [GCC_QUPV3_WRAP0_S4_CLK] =3D &gcc_qupv3_wrap0_s4_clk.clkr, + [GCC_QUPV3_WRAP0_S4_CLK_SRC] =3D &gcc_qupv3_wrap0_s4_clk_src.clkr, + [GCC_QUPV3_WRAP0_S5_CLK] =3D &gcc_qupv3_wrap0_s5_clk.clkr, + [GCC_QUPV3_WRAP0_S5_CLK_SRC] =3D &gcc_qupv3_wrap0_s5_clk_src.clkr, + [GCC_QUPV3_WRAP1_CORE_2X_CLK] =3D &gcc_qupv3_wrap1_core_2x_clk.clkr, + [GCC_QUPV3_WRAP1_CORE_CLK] =3D &gcc_qupv3_wrap1_core_clk.clkr, + [GCC_QUPV3_WRAP1_S0_CLK] =3D &gcc_qupv3_wrap1_s0_clk.clkr, + [GCC_QUPV3_WRAP1_S0_CLK_SRC] =3D &gcc_qupv3_wrap1_s0_clk_src.clkr, + [GCC_QUPV3_WRAP1_S1_CLK] =3D &gcc_qupv3_wrap1_s1_clk.clkr, + [GCC_QUPV3_WRAP1_S1_CLK_SRC] =3D &gcc_qupv3_wrap1_s1_clk_src.clkr, + [GCC_QUPV3_WRAP1_S2_CLK] =3D &gcc_qupv3_wrap1_s2_clk.clkr, + [GCC_QUPV3_WRAP1_S2_CLK_SRC] =3D &gcc_qupv3_wrap1_s2_clk_src.clkr, + [GCC_QUPV3_WRAP1_S3_CLK] =3D &gcc_qupv3_wrap1_s3_clk.clkr, + [GCC_QUPV3_WRAP1_S3_CLK_SRC] =3D &gcc_qupv3_wrap1_s3_clk_src.clkr, + [GCC_QUPV3_WRAP1_S4_CLK] =3D &gcc_qupv3_wrap1_s4_clk.clkr, + [GCC_QUPV3_WRAP1_S4_CLK_SRC] =3D &gcc_qupv3_wrap1_s4_clk_src.clkr, + [GCC_QUPV3_WRAP1_S5_CLK] =3D &gcc_qupv3_wrap1_s5_clk.clkr, + [GCC_QUPV3_WRAP1_S5_CLK_SRC] =3D &gcc_qupv3_wrap1_s5_clk_src.clkr, + [GCC_QUPV3_WRAP_0_M_AHB_CLK] =3D &gcc_qupv3_wrap_0_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_0_S_AHB_CLK] =3D &gcc_qupv3_wrap_0_s_ahb_clk.clkr, + [GCC_QUPV3_WRAP_1_M_AHB_CLK] =3D &gcc_qupv3_wrap_1_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_1_S_AHB_CLK] =3D &gcc_qupv3_wrap_1_s_ahb_clk.clkr, + [GCC_SDCC1_AHB_CLK] =3D &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] =3D &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC1_APPS_CLK_SRC] =3D &gcc_sdcc1_apps_clk_src.clkr, + [GCC_SDCC1_ICE_CORE_CLK] =3D &gcc_sdcc1_ice_core_clk.clkr, + [GCC_SDCC1_ICE_CORE_CLK_SRC] =3D &gcc_sdcc1_ice_core_clk_src.clkr, + [GCC_SDCC2_AHB_CLK] =3D &gcc_sdcc2_ahb_clk.clkr, + [GCC_SDCC2_APPS_CLK] =3D &gcc_sdcc2_apps_clk.clkr, + [GCC_SDCC2_APPS_CLK_SRC] =3D &gcc_sdcc2_apps_clk_src.clkr, + [GCC_SDCC4_AHB_CLK] =3D &gcc_sdcc4_ahb_clk.clkr, + [GCC_SDCC4_APPS_CLK] =3D &gcc_sdcc4_apps_clk.clkr, + [GCC_SDCC4_APPS_CLK_SRC] =3D &gcc_sdcc4_apps_clk_src.clkr, + [GCC_UFS_1X_CLKREF_CLK] =3D &gcc_ufs_1x_clkref_clk.clkr, + [GCC_UFS_PHY_AHB_CLK] =3D &gcc_ufs_phy_ahb_clk.clkr, + [GCC_UFS_PHY_AXI_CLK] =3D &gcc_ufs_phy_axi_clk.clkr, + [GCC_UFS_PHY_AXI_CLK_SRC] =3D &gcc_ufs_phy_axi_clk_src.clkr, + [GCC_UFS_PHY_ICE_CORE_CLK] =3D &gcc_ufs_phy_ice_core_clk.clkr, + [GCC_UFS_PHY_ICE_CORE_CLK_SRC] =3D &gcc_ufs_phy_ice_core_clk_src.clkr, + [GCC_UFS_PHY_PHY_AUX_CLK] =3D &gcc_ufs_phy_phy_aux_clk.clkr, + [GCC_UFS_PHY_PHY_AUX_CLK_SRC] =3D &gcc_ufs_phy_phy_aux_clk_src.clkr, + [GCC_UFS_PHY_RX_SYMBOL_0_CLK] =3D &gcc_ufs_phy_rx_symbol_0_clk.clkr, + [GCC_UFS_PHY_RX_SYMBOL_1_CLK] =3D &gcc_ufs_phy_rx_symbol_1_clk.clkr, + [GCC_UFS_PHY_TX_SYMBOL_0_CLK] =3D &gcc_ufs_phy_tx_symbol_0_clk.clkr, + [GCC_UFS_PHY_UNIPRO_CORE_CLK] =3D &gcc_ufs_phy_unipro_core_clk.clkr, + [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =3D + &gcc_ufs_phy_unipro_core_clk_src.clkr, + [GCC_USB30_PRIM_MASTER_CLK] =3D &gcc_usb30_prim_master_clk.clkr, + [GCC_USB30_PRIM_MASTER_CLK_SRC] =3D &gcc_usb30_prim_master_clk_src.clkr, + [GCC_USB30_PRIM_MOCK_UTMI_CLK] =3D &gcc_usb30_prim_mock_utmi_clk.clkr, + [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =3D + &gcc_usb30_prim_mock_utmi_clk_src.clkr, + [GCC_USB30_PRIM_SLEEP_CLK] =3D &gcc_usb30_prim_sleep_clk.clkr, + [GCC_USB3_PRIM_CLKREF_CLK] =3D &gcc_usb3_prim_clkref_clk.clkr, + [GCC_USB3_PRIM_PHY_AUX_CLK] =3D &gcc_usb3_prim_phy_aux_clk.clkr, + [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] =3D &gcc_usb3_prim_phy_aux_clk_src.clkr, + [GCC_USB3_PRIM_PHY_COM_AUX_CLK] =3D &gcc_usb3_prim_phy_com_aux_clk.clkr, + [GCC_USB3_PRIM_PHY_PIPE_CLK] =3D &gcc_usb3_prim_phy_pipe_clk.clkr, + [GCC_VIDEO_AXI_CLK] =3D &gcc_video_axi_clk.clkr, + [GPLL0] =3D &gpll0.clkr, + [GPLL0_OUT_EVEN] =3D &gpll0_out_even.clkr, + [GPLL6] =3D &gpll6.clkr, + [GPLL9] =3D &gpll9.clkr, +}; + +static struct gdsc *gcc_sm7250_gdscs[] =3D { + [UFS_PHY_GDSC] =3D &ufs_phy_gdsc, + [USB30_PRIM_GDSC] =3D &usb30_prim_gdsc, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =3D + &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] =3D + &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc, + [HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] =3D + &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc, +}; + +static const struct qcom_reset_map gcc_sm7250_resets[] =3D { + [GCC_DPM_BCR] =3D { 0x46000 }, + [GCC_GPU_BCR] =3D { 0x71000 }, + [GCC_MMSS_BCR] =3D { 0xb000 }, + [GCC_NPU_BWMON_BCR] =3D { 0x70000 }, + [GCC_NPU_BCR] =3D { 0x4d000 }, + [GCC_PDM_BCR] =3D { 0x33000 }, + [GCC_PRNG_BCR] =3D { 0x34000 }, + [GCC_QUPV3_WRAPPER_0_BCR] =3D { 0x17000 }, + [GCC_QUPV3_WRAPPER_1_BCR] =3D { 0x18000 }, + [GCC_QUSB2PHY_PRIM_BCR] =3D { 0x12000 }, + [GCC_SDCC1_BCR] =3D { 0x26000 }, + [GCC_SDCC2_BCR] =3D { 0x14000 }, + [GCC_SDCC4_BCR] =3D { 0x16000 }, + [GCC_UFS_PHY_BCR] =3D { 0x77000 }, + [GCC_USB30_PRIM_BCR] =3D { 0xf000 }, + [GCC_USB3_DP_PHY_PRIM_BCR] =3D { 0x50008 }, + [GCC_USB3_PHY_PRIM_BCR] =3D { 0x50000 }, + [GCC_USB3PHY_PHY_PRIM_BCR] =3D { 0x50004 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] =3D { 0x6a000 }, +}; + +static const u32 gcc_sm7250_critical_cbcrs[] =3D { + 0x0b004, /* GCC_VIDEO_AHB_CLK */ + 0x0b008, /* GCC_CAMERA_AHB_CLK */ + 0x0b00c, /* GCC_DISP_AHB_CLK */ + 0x0b038, /* GCC_VIDEO_XO_CLK */ + 0x0b03c, /* GCC_CAMERA_XO_CLK */ + 0x0b040, /* GCC_DISP_XO_CLK */ + 0x4d004, /* GCC_NPU_CFG_AHB_CLK */ + 0x52000, /* GCC_SYS_NOC_CPUSS_AHB_CLK */ + 0x70004, /* GCC_NPU_BWMON_CFG_AHB_CLK */ + 0x71004, /* GCC_GPU_CFG_AHB_CLK */ +}; + +static const struct clk_rcg_dfs_data gcc_sm7250_dfs_clocks[] =3D { + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), +}; + +static const struct regmap_config gcc_sm7250_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x9c100, + .fast_io =3D true, +}; + +static void gcc_sm7250_clk_regs_configure(struct regmap *regmap) +{ + /* + * Disable the GPLL0 active input to NPU and GPU + * via MISC registers. + */ + regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); + regmap_update_bits(regmap, 0x71028, 0x3, 0x3); + + /* Critical clocks that has same register with + * different mask + */ + regmap_update_bits(regmap, 0x52000, BIT(21), BIT(21)); /* GCC_CPUSS_AHB_C= LK */ +} + +static const struct qcom_cc_driver_data gcc_sm7250_driver_data =3D { + .clk_cbcrs =3D gcc_sm7250_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(gcc_sm7250_critical_cbcrs), + .dfs_rcgs =3D gcc_sm7250_dfs_clocks, + .num_dfs_rcgs =3D ARRAY_SIZE(gcc_sm7250_dfs_clocks), + .clk_regs_configure =3D gcc_sm7250_clk_regs_configure, +}; + +static const struct qcom_cc_desc gcc_sm7250_desc =3D { + .config =3D &gcc_sm7250_regmap_config, + .clks =3D gcc_sm7250_clocks, + .num_clks =3D ARRAY_SIZE(gcc_sm7250_clocks), + .resets =3D gcc_sm7250_resets, + .num_resets =3D ARRAY_SIZE(gcc_sm7250_resets), + .gdscs =3D gcc_sm7250_gdscs, + .num_gdscs =3D ARRAY_SIZE(gcc_sm7250_gdscs), + .use_rpm =3D true, + .driver_data =3D &gcc_sm7250_driver_data, +}; + +static const struct of_device_id gcc_sm7250_match_table[] =3D { + { .compatible =3D "qcom,sm7250-gcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_sm7250_match_table); + +static int gcc_sm7250_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gcc_sm7250_desc); +} + +static struct platform_driver gcc_sm7250_driver =3D { + .probe =3D gcc_sm7250_probe, + .driver =3D { + .name =3D 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-0700 (PDT) From: Sreeshankar K To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, konradybcio@kernel.org, tglx@kernel.org, ulfh@kernel.org Cc: bmasney@redhat.com, radu@rendec.net, abel.vesa@oss.qualcomm.com, lpieralisi@kernel.org, quic_tdas@quicinc.com, danila@mainlining.org, davidwronek@gmail.com, mani@kernel.org, robimarko@gmail.com, linux@gurudas.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K , Krzysztof Kozlowski Subject: [PATCH v4 05/13] dt-bindings: clock: qcom,rpmhcc: Document RPMHCC compatible for SM7250 Date: Fri, 21 Aug 2026 15:40:22 +0000 Message-ID: <20260821154030.2514-6-sreeshankar0910@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821154030.2514-1-sreeshankar0910@gmail.com> References: <20260821154030.2514-1-sreeshankar0910@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document RPMHCC compatible for clock rpmh driver on Qualcomm SM7250 SoC. Signed-off-by: Sreeshankar K Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Doc= umentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index d344b3386..df9e37f90 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -38,6 +38,7 @@ properties: - qcom,sdx75-rpmh-clk - qcom,sm4450-rpmh-clk - qcom,sm6350-rpmh-clk + - qcom,sm7250-rpmh-clk - qcom,sm8150-rpmh-clk - qcom,sm8250-rpmh-clk - qcom,sm8350-rpmh-clk --=20 2.43.0 From nobody Mon Sep 28 12:33:39 2026 Received: from mail-pj1-f44.google.com (mail-pj1-f44.google.com [209.85.216.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71B6E426EAD for ; Fri, 21 Aug 2026 15:41:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 21 Aug 2026 08:41:54 -0700 (PDT) Received: from localhost.localdomain ([152.58.217.163]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1416ae5f1ffsm42903185c88.13.2026.08.21.08.41.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 08:41:54 -0700 (PDT) From: Sreeshankar K To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, konradybcio@kernel.org, tglx@kernel.org, ulfh@kernel.org Cc: bmasney@redhat.com, radu@rendec.net, abel.vesa@oss.qualcomm.com, lpieralisi@kernel.org, quic_tdas@quicinc.com, danila@mainlining.org, davidwronek@gmail.com, mani@kernel.org, robimarko@gmail.com, linux@gurudas.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K , Dmitry Baryshkov Subject: [PATCH v4 06/13] clk: qcom: rpmh: Add SM7250 rpmh clocks Date: Fri, 21 Aug 2026 15:40:23 +0000 Message-ID: <20260821154030.2514-7-sreeshankar0910@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821154030.2514-1-sreeshankar0910@gmail.com> References: <20260821154030.2514-1-sreeshankar0910@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the RPMH clocks present in SM7250 SoC. Signed-off-by: Sreeshankar K Reviewed-by: Dmitry Baryshkov Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/clk-rpmh.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 6367b2a5a..f4cafa274 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -1011,6 +1011,29 @@ static const struct clk_rpmh_desc clk_rpmh_hawi =3D { .num_clks =3D ARRAY_SIZE(hawi_rpmh_clocks), }; =20 +static struct clk_hw *sm7250_rpmh_clocks[] =3D { + [RPMH_CXO_CLK] =3D &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] =3D &clk_rpmh_bi_tcxo_div2_ao.hw, + [RPMH_LN_BB_CLK2] =3D &clk_rpmh_ln_bb_clk2_a2.hw, + [RPMH_LN_BB_CLK2_A] =3D &clk_rpmh_ln_bb_clk2_a2_ao.hw, + [RPMH_LN_BB_CLK3] =3D &clk_rpmh_ln_bb_clk3_a2.hw, + [RPMH_LN_BB_CLK3_A] =3D &clk_rpmh_ln_bb_clk3_a2_ao.hw, + [RPMH_RF_CLK1] =3D &clk_rpmh_rf_clk1_d.hw, + [RPMH_RF_CLK1_A] =3D &clk_rpmh_rf_clk1_d_ao.hw, + [RPMH_RF_CLK2] =3D &clk_rpmh_rf_clk2_d.hw, + [RPMH_RF_CLK2_A] =3D &clk_rpmh_rf_clk2_d_ao.hw, + [RPMH_RF_CLK3] =3D &clk_rpmh_rf_clk3_d.hw, + [RPMH_RF_CLK3_A] =3D &clk_rpmh_rf_clk3_d_ao.hw, + [RPMH_RF_CLK4] =3D &clk_rpmh_rf_clk4_d.hw, + [RPMH_RF_CLK4_A] =3D &clk_rpmh_rf_clk4_d_ao.hw, + [RPMH_IPA_CLK] =3D &clk_rpmh_ipa.hw, +}; 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Fri, 21 Aug 2026 08:42:04 -0700 (PDT) Received: from localhost.localdomain ([152.58.217.163]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1416ae5f1ffsm42903185c88.13.2026.08.21.08.41.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 08:42:04 -0700 (PDT) From: Sreeshankar K To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, konradybcio@kernel.org, tglx@kernel.org, ulfh@kernel.org Cc: bmasney@redhat.com, radu@rendec.net, abel.vesa@oss.qualcomm.com, lpieralisi@kernel.org, quic_tdas@quicinc.com, danila@mainlining.org, davidwronek@gmail.com, mani@kernel.org, robimarko@gmail.com, linux@gurudas.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K Subject: [PATCH v4 07/13] dt-bindings: power: qcom,rpmhpd: Document RPMh power domain for SM7250 Date: Fri, 21 Aug 2026 15:40:24 +0000 Message-ID: <20260821154030.2514-8-sreeshankar0910@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821154030.2514-1-sreeshankar0910@gmail.com> References: <20260821154030.2514-1-sreeshankar0910@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the RPMh power domain for SM7250 SoC. Signed-off-by: Sreeshankar K --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Docu= mentation/devicetree/bindings/power/qcom,rpmpd.yaml index 0a45e1f55..e08441915 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -63,6 +63,7 @@ properties: - qcom,sm6350-rpmhpd - qcom,sm6375-rpmpd - qcom,sm7150-rpmhpd + - qcom,sm7250-rpmhpd - qcom,sm8150-rpmhpd - qcom,sm8250-rpmhpd - qcom,sm8350-rpmhpd --=20 2.43.0 From nobody Mon Sep 28 12:33:39 2026 Received: from mail-pj1-f53.google.com (mail-pj1-f53.google.com [209.85.216.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66F5836E47A for ; Fri, 21 Aug 2026 15:42:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.53 ARC-Seal: i=1; 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Fri, 21 Aug 2026 08:42:14 -0700 (PDT) Received: from localhost.localdomain ([152.58.217.163]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1416ae5f1ffsm42903185c88.13.2026.08.21.08.42.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 08:42:13 -0700 (PDT) From: Sreeshankar K To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, konradybcio@kernel.org, tglx@kernel.org, ulfh@kernel.org Cc: bmasney@redhat.com, radu@rendec.net, abel.vesa@oss.qualcomm.com, lpieralisi@kernel.org, quic_tdas@quicinc.com, danila@mainlining.org, davidwronek@gmail.com, mani@kernel.org, robimarko@gmail.com, linux@gurudas.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K Subject: [PATCH v4 08/13] pmdomain: qcom: rpmhpd: Add RMPh power domains for SM7250 Date: Fri, 21 Aug 2026 15:40:25 +0000 Message-ID: <20260821154030.2514-9-sreeshankar0910@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821154030.2514-1-sreeshankar0910@gmail.com> References: <20260821154030.2514-1-sreeshankar0910@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add RMPh power domains for SM7250 SoC. Signed-off-by: Sreeshankar K Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio --- drivers/pmdomain/qcom/rpmhpd.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/pmdomain/qcom/rpmhpd.c b/drivers/pmdomain/qcom/rpmhpd.c index 96e4bd2f5..70d0ff5cc 100644 --- a/drivers/pmdomain/qcom/rpmhpd.c +++ b/drivers/pmdomain/qcom/rpmhpd.c @@ -490,6 +490,24 @@ static const struct rpmhpd_desc sm7150_desc =3D { .num_pds =3D ARRAY_SIZE(sm7150_rpmhpds), }; =20 +/* SM7250 RPMH powerdomains */ +static struct rpmhpd *sm7250_rpmhpds[] =3D { + [RPMHPD_CX] =3D &cx_w_mx_parent, + [RPMHPD_CX_AO] =3D &cx_ao_w_mx_parent, + [RPMHPD_EBI] =3D &ebi, + [RPMHPD_GFX] =3D &gfx, + [RPMHPD_LCX] =3D &lcx, + [RPMHPD_LMX] =3D &lmx, + [RPMHPD_MSS] =3D &mss, + [RPMHPD_MX] =3D &mx, + [RPMHPD_MX_AO] =3D &mx_ao, +}; + +static const struct rpmhpd_desc sm7250_desc =3D { + .rpmhpds =3D sm7250_rpmhpds, + .num_pds =3D ARRAY_SIZE(sm7250_rpmhpds), +}; + /* SM8150 RPMH powerdomains */ static struct rpmhpd *sm8150_rpmhpds[] =3D { [SM8150_CX] =3D &cx_w_mx_parent, @@ -910,6 +928,7 @@ static const struct of_device_id rpmhpd_match_table[] = =3D { { .compatible =3D "qcom,sm4450-rpmhpd", .data =3D &sm4450_desc }, { .compatible =3D "qcom,sm6350-rpmhpd", .data =3D &sm6350_desc }, { .compatible =3D "qcom,sm7150-rpmhpd", .data =3D &sm7150_desc }, + { .compatible =3D "qcom,sm7250-rpmhpd", .data =3D &sm7250_desc }, { .compatible =3D "qcom,sm8150-rpmhpd", .data =3D &sm8150_desc }, { .compatible =3D "qcom,sm8250-rpmhpd", .data =3D &sm8250_desc }, { .compatible =3D "qcom,sm8350-rpmhpd", .data =3D &sm8350_desc }, --=20 2.43.0 From nobody Mon Sep 28 12:33:39 2026 Received: from mail-pg1-f173.google.com (mail-pg1-f173.google.com [209.85.215.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0ACA83750DB for ; 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charset="utf-8" Document Kryo 475 CPUs found in Qualcomm SM7250 SoC. Signed-off-by: Sreeshankar K --- Documentation/devicetree/bindings/arm/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentatio= n/devicetree/bindings/arm/cpus.yaml index 5be89c584..2a90af67c 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -212,6 +212,7 @@ properties: - qcom,kryo465 - qcom,kryo468 - qcom,kryo470 + - qcom,kryo475 - qcom,kryo485 - qcom,kryo560 - qcom,kryo570 --=20 2.43.0 From nobody Mon Sep 28 12:33:39 2026 Received: from mail-pj1-f53.google.com (mail-pj1-f53.google.com [209.85.216.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1FEEE36EAAC for ; Fri, 21 Aug 2026 15:42:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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charset="utf-8" Document the SCM compatible for Qualcomm SM7250 SoC. Signed-off-by: Sreeshankar K Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Doc= umentation/devicetree/bindings/firmware/qcom,scm.yaml index 037d4ad8f..0cbdb3b2f 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -74,6 +74,7 @@ properties: - qcom,scm-sm6350 - qcom,scm-sm6375 - qcom,scm-sm7150 + - qcom,scm-sm7250 - qcom,scm-sm8150 - qcom,scm-sm8250 - qcom,scm-sm8350 --=20 2.43.0 From nobody Mon Sep 28 12:33:39 2026 Received: from mail-pg1-f181.google.com (mail-pg1-f181.google.com [209.85.215.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1F8438F95B for ; Fri, 21 Aug 2026 15:42:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 21 Aug 2026 08:42:44 -0700 (PDT) Received: from localhost.localdomain ([152.58.217.163]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1416ae5f1ffsm42903185c88.13.2026.08.21.08.42.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 08:42:44 -0700 (PDT) From: Sreeshankar K To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, konradybcio@kernel.org, tglx@kernel.org, ulfh@kernel.org Cc: bmasney@redhat.com, radu@rendec.net, abel.vesa@oss.qualcomm.com, lpieralisi@kernel.org, quic_tdas@quicinc.com, danila@mainlining.org, davidwronek@gmail.com, mani@kernel.org, robimarko@gmail.com, linux@gurudas.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K Subject: [PATCH v4 11/13] dt-bindings: interrupt-controller: qcom,pdc: Document SM7250 PDC Date: Fri, 21 Aug 2026 15:40:28 +0000 Message-ID: <20260821154030.2514-12-sreeshankar0910@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821154030.2514-1-sreeshankar0910@gmail.com> References: <20260821154030.2514-1-sreeshankar0910@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the PDC block on the SM7250 SoC. Signed-off-by: Sreeshankar K --- .../devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pd= c.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.ya= ml index 8162a49d4..c30b88589 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -50,6 +50,7 @@ properties: - qcom,sdx75-pdc - qcom,sm4450-pdc - qcom,sm6350-pdc + - qcom,sm7250-pdc - qcom,sm8150-pdc - qcom,sm8250-pdc - qcom,sm8350-pdc --=20 2.43.0 From nobody Mon Sep 28 12:33:39 2026 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD84B38F95B for ; Fri, 21 Aug 2026 15:42:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 21 Aug 2026 08:42:54 -0700 (PDT) Received: from localhost.localdomain ([152.58.217.163]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1416ae5f1ffsm42903185c88.13.2026.08.21.08.42.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 08:42:54 -0700 (PDT) From: Sreeshankar K To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, konradybcio@kernel.org, tglx@kernel.org, ulfh@kernel.org Cc: bmasney@redhat.com, radu@rendec.net, abel.vesa@oss.qualcomm.com, lpieralisi@kernel.org, quic_tdas@quicinc.com, danila@mainlining.org, davidwronek@gmail.com, mani@kernel.org, robimarko@gmail.com, linux@gurudas.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K Subject: [PATCH v4 12/13] dt-bindings: cpufreq: qcom-hw: Document SM7250 cpufreq hardware Date: Fri, 21 Aug 2026 15:40:29 +0000 Message-ID: <20260821154030.2514-13-sreeshankar0910@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821154030.2514-1-sreeshankar0910@gmail.com> References: <20260821154030.2514-1-sreeshankar0910@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the cpufreq hardware on the SM7250 SoC. Signed-off-by: Sreeshankar K Acked-by: Viresh Kumar --- Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml= b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index 98eb36bff..2dc2c265c 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -29,6 +29,7 @@ properties: - qcom,sdm845-cpufreq-hw - qcom,sm6115-cpufreq-hw - qcom,sm6350-cpufreq-hw + - qcom,sm7250-cpufreq-hw - qcom,sm8150-cpufreq-hw - const: qcom,cpufreq-hw =20 --=20 2.43.0 From nobody Mon Sep 28 12:33:39 2026 Received: from mail-pg1-f179.google.com (mail-pg1-f179.google.com [209.85.215.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73FF4426405 for ; Fri, 21 Aug 2026 15:43:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 21 Aug 2026 08:43:04 -0700 (PDT) Received: from localhost.localdomain ([152.58.217.163]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1416ae5f1ffsm42903185c88.13.2026.08.21.08.42.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 08:43:04 -0700 (PDT) From: Sreeshankar K To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, konradybcio@kernel.org, tglx@kernel.org, ulfh@kernel.org Cc: bmasney@redhat.com, radu@rendec.net, abel.vesa@oss.qualcomm.com, lpieralisi@kernel.org, quic_tdas@quicinc.com, danila@mainlining.org, davidwronek@gmail.com, mani@kernel.org, robimarko@gmail.com, linux@gurudas.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K Subject: [PATCH v4 13/13] arm64: dts: qcom: Add SM7250 devicetree file Date: Fri, 21 Aug 2026 15:40:30 +0000 Message-ID: <20260821154030.2514-14-sreeshankar0910@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821154030.2514-1-sreeshankar0910@gmail.com> References: <20260821154030.2514-1-sreeshankar0910@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add base devicetree file for SM7250 SoC. This file adds the basic nodes like cpu, psci and other required configuration for booting up to the serial console. Signed-off-by: Sreeshankar K --- arch/arm64/boot/dts/qcom/sm7250.dtsi | 756 +++++++++++++++++++++++++++ 1 file changed, 756 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm7250.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm7250.dtsi b/arch/arm64/boot/dts/qco= m/sm7250.dtsi new file mode 100644 index 000000000..97de11578 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7250.dtsi @@ -0,0 +1,756 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026, Sreeshankar K + */ + +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + clocks { + xo_board: xo-board { + compatible =3D "fixed-clock"; + clock-frequency =3D <38400000>; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <32764>; + #clock-cells =3D <0>; + }; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo475"; + reg =3D <0x0 0x0>; + clocks =3D <&cpufreq_hw 0>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + next-level-cache =3D <&l2_0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + power-domains =3D <&cpu_pd0>; + power-domain-names =3D "psci"; + #cooling-cells =3D <2>; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x20000>; + cache-unified; + next-level-cache =3D <&l3_0>; + + l3_0: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-size =3D <0x200000>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo475"; + reg =3D <0x0 0x100>; + clocks =3D <&cpufreq_hw 0>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + next-level-cache =3D <&l2_100>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + power-domains =3D <&cpu_pd1>; + power-domain-names =3D "psci"; + #cooling-cells =3D <2>; + + l2_100: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x20000>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo475"; + reg =3D <0x0 0x200>; + clocks =3D <&cpufreq_hw 0>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + next-level-cache =3D <&l2_200>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + power-domains =3D <&cpu_pd2>; + power-domain-names =3D "psci"; + #cooling-cells =3D <2>; + + l2_200: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x20000>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo475"; + reg =3D <0x0 0x300>; + clocks =3D <&cpufreq_hw 0>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + next-level-cache =3D <&l2_300>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + power-domains =3D <&cpu_pd3>; + power-domain-names =3D "psci"; + #cooling-cells =3D <2>; + + l2_300: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x20000>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo475"; + reg =3D <0x0 0x400>; + clocks =3D <&cpufreq_hw 0>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + next-level-cache =3D <&l2_400>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + power-domains =3D <&cpu_pd4>; + power-domain-names =3D "psci"; + #cooling-cells =3D <2>; + + l2_400: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x20000>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo475"; + reg =3D <0x0 0x500>; + clocks =3D <&cpufreq_hw 0>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + next-level-cache =3D <&l2_500>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + power-domains =3D <&cpu_pd5>; + power-domain-names =3D "psci"; + #cooling-cells =3D <2>; + + l2_500: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x20000>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu6: cpu@600 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo475"; + reg =3D <0x0 0x600>; + clocks =3D <&cpufreq_hw 1>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1740>; + dynamic-power-coefficient =3D <341>; + next-level-cache =3D <&l2_600>; + qcom,freq-domain =3D <&cpufreq_hw 1>; + power-domains =3D <&cpu_pd6>; + power-domain-names =3D "psci"; + #cooling-cells =3D <2>; + + l2_600: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x40000>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu7: cpu@700 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo475"; + reg =3D <0x0 0x700>; + clocks =3D <&cpufreq_hw 2>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1740>; + dynamic-power-coefficient =3D <375>; + next-level-cache =3D <&l2_700>; + qcom,freq-domain =3D <&cpufreq_hw 2>; + power-domains =3D <&cpu_pd7>; + power-domain-names =3D "psci"; + #cooling-cells =3D <2>; + + l2_700: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + + core4 { + cpu =3D <&cpu4>; + }; + + core5 { + cpu =3D <&cpu5>; + }; + }; + + cluster1 { + core6 { + cpu =3D <&cpu6>; + }; + }; + + cluster2 { + core7 { + cpu =3D <&cpu7>; + }; + }; + }; + + domain-idle-states { + cluster_sleep_pc: cluster-sleep-0 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41000044>; + entry-latency-us =3D <2752>; + exit-latency-us =3D <3048>; + min-residency-us =3D <6118>; + }; + + cluster_sleep_cx: cluster-sleep-1 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41001244>; + entry-latency-us =3D <3638>; + exit-latency-us =3D <4562>; + min-residency-us =3D <8467>; + }; + + cluster_sleep_aoss: cluster-sleep-2 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x4100b244>; + entry-latency-us =3D <3263>; + exit-latency-us =3D <6562>; + min-residency-us =3D <9826>; + }; + }; + + idle-states { + entry-method =3D "psci"; + + little_cpu_sleep_0: cpu-sleep-0-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "little-power-collapse"; + arm,psci-suspend-param =3D <0x40000003>; + entry-latency-us =3D <549>; + exit-latency-us =3D <901>; + min-residency-us =3D <1774>; + local-timer-stop; + }; + + little_cpu_sleep_1: cpu-sleep-0-1 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "little-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <702>; + exit-latency-us =3D <915>; + min-residency-us =3D <4001>; + local-timer-stop; + }; + + big_cpu_sleep_0: cpu-sleep-1-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "big-power-collapse"; + arm,psci-suspend-param =3D <0x40000003>; + entry-latency-us =3D <523>; + exit-latency-us =3D <1244>; + min-residency-us =3D <2207>; + local-timer-stop; + }; + + big_cpu_sleep_1: cpu-sleep-1-1 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "big-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <526>; + exit-latency-us =3D <1854>; + min-residency-us =3D <5555>; + local-timer-stop; + }; + }; + }; + + firmware { + scm: scm { + compatible =3D "qcom,scm-sm7250", "qcom,scm"; + #reset-cells =3D <1>; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible =3D "arm,armv8-pmuv3"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; + }; + + cluster_pd: power-domain-cpu-cluster0 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_sleep_pc + &cluster_sleep_cx + &cluster_sleep_aoss>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + hyp_mem: hyp@80000000 { + reg =3D <0x0 0x80000000 0x0 0x600000>; + no-map; + }; + + xbl_aop_mem: xbl-aop@80700000 { + reg =3D <0x0 0x80700000 0x0 0x160000>; + no-map; + }; + + cmd_db: cmd-db@80860000 { + compatible =3D "qcom,cmd-db"; + reg =3D <0x0 0x80860000 0x0 0x20000>; + no-map; + }; + + xbl_uefi_mem: xbl-uefi@80880000 { + reg =3D <0 0x80880000 0 0x14000>; + no-map; + }; + + smem_mem: smem@80900000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x80900000 0x0 0x200000>; + no-map; + hwlocks =3D <&tcsr_mutex 3>; + }; + + removed_mem: removed@80b00000 { + reg =3D <0x0 0x80b00000 0x0 0x1300000>; + no-map; + }; + + camera_mem: camera@86000000 { + reg =3D <0x0 0x86000000 0x0 0x500000>; + no-map; + }; + + npu_mem: npu@86500000 { + reg =3D <0x0 0x86500000 0x0 0x500000>; + no-map; + }; + + video_mem: video@86a00000 { + reg =3D <0x0 0x86a00000 0x0 0x500000>; + no-map; + }; + + cdsp_mem: cdsp@87400000 { + reg =3D <0x0 0x87400000 0x0 0x1e00000>; + no-map; + }; + + adsp_mem: adsp@89200000 { + reg =3D <0x0 0x89200000 0x0 0x2800000>; + no-map; + }; + + wlan_fw_mem: wlan-fw@8ba00000 { + reg =3D <0x0 0x8ba00000 0x0 0x200000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@8bc00000 { + reg =3D <0x0 0x8bc00000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@8bc10000 { + reg =3D <0x0 0x8bc10000 0x0 0x5400>; + no-map; + }; + + gpu_mem: gpu@8bc15400 { + reg =3D <0x0 0x8bc15400 0x0 0x2000>; + no-map; + }; + + modem_wlan_mem: modem-wlan@8c000000 { + reg =3D <0x0 0x8c000000 0x0 0xf800000>; + no-map; + }; + + cdsp_sec_mem: cdsp-sec@9f400000 { + reg =3D <0x0 0x9f400000 0x0 0xc00000>; + no-map; + }; + }; + + soc: soc@0 { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0 0 0 0 0x10 0>; + dma-ranges =3D <0 0 0 0 0x10 0>; + compatible =3D "simple-bus"; + + gcc: clock-controller@100000 { + compatible =3D "qcom,sm7250-gcc"; + reg =3D <0x0 0x00100000 0x0 0x1f0000>; + clock-names =3D "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + qupv3_id_1: geniqup@9c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x009c0000 0x0 0x6000>; + clock-names =3D "m-ahb", "s-ahb"; + clocks =3D <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + uart2: serial@988000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0 0x00988000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts =3D ; + status =3D "disabled"; + }; + }; + + intc: interrupt-controller@17a00000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + #interrupt-cells =3D <3>; + interrupt-controller; + interrupts =3D ; + }; + + pdc: interrupt-controller@b220000 { + compatible =3D "qcom,sm7250-pdc", "qcom,pdc"; + reg =3D <0 0xb220000 0 0x30000>, <0 0x17c000f0 0 0x60>; + qcom,pdc-ranges =3D <0 480 42>, <42 612 28>, + <70 63 1>, <71 640 15>, <86 522 52>; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&intc>; + interrupt-controller; + }; + + spmi_bus: spmi@c440000 { + compatible =3D "qcom,spmi-pmic-arb"; + reg =3D <0x0 0x0c440000 0x0 0x0001100>, + <0x0 0x0c600000 0x0 0x2000000>, + <0x0 0x0e600000 0x0 0x0100000>, + <0x0 0x0e700000 0x0 0x00a0000>, + <0x0 0x0c40a000 0x0 0x0026000>; + reg-names =3D "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names =3D "periph_irq"; + interrupts-extended =3D <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee =3D <0>; + qcom,channel =3D <0>; + #address-cells =3D <2>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <4>; + }; + + apps_rsc: rsc@18200000 { + compatible =3D "qcom,rpmh-rsc"; + reg =3D <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names =3D "drv-0", "drv-1", "drv-2"; + interrupts =3D , + , + ; + label =3D "apps_rsc"; + qcom,tcs-offset =3D <0xd00>; + qcom,drv-id =3D <2>; + qcom,tcs-config =3D , , + , ; + power-domains =3D <&cluster_pd>; + + rpmhcc: clock-controller { + compatible =3D "qcom,sm7250-rpmh-clk"; + #clock-cells =3D <1>; + clock-names =3D "xo"; + clocks =3D <&xo_board>; + }; + + rpmhpd: power-controller { + compatible =3D "qcom,sm7250-rpmhpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level =3D ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level =3D ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level =3D ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level =3D ; + }; + }; + }; + + apps_bcm_voter: bcm-voter { + compatible =3D "qcom,bcm-voter"; + }; + }; + + cpufreq_hw: cpufreq@18323000 { + compatible =3D "qcom,sm7250-cpufreq-hw", "qcom,cpufreq-hw"; + reg =3D <0 0x18323000 0 0x1000>, + <0 0x18325800 0 0x1000>, + <0 0x18327800 0 0x1000>; + reg-names =3D "freq-domain0", "freq-domain1", + "freq-domain2"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; + #freq-domain-cells =3D <1>; + #clock-cells =3D <1>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x01f40000 0x0 0x40000>; + #hwlock-cells =3D <1>; + }; + + timer@17c20000 { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0x17c20000 0x0 0x1000>; + clock-frequency =3D <19200000>; + + frame@17c21000 { + frame-number =3D <0>; + interrupts =3D , + ; + reg =3D <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + }; + + frame@17c23000 { + frame-number =3D <1>; + interrupts =3D ; + reg =3D <0x17c23000 0x1000>; + status =3D "disabled"; + }; + + frame@17c25000 { + frame-number =3D <2>; + interrupts =3D ; + reg =3D <0x17c25000 0x1000>; + status =3D "disabled"; + }; + + frame@17c27000 { + frame-number =3D <3>; + interrupts =3D ; + reg =3D <0x17c27000 0x1000>; + status =3D "disabled"; + }; + + frame@17c29000 { + frame-number =3D <4>; + interrupts =3D ; + reg =3D <0x17c29000 0x1000>; + status =3D "disabled"; + }; + + frame@17c2b000 { + frame-number =3D <5>; + interrupts =3D ; + reg =3D <0x17c2b000 0x1000>; + status =3D "disabled"; + }; + + frame@17c2d000 { + frame-number =3D <6>; + interrupts =3D ; + reg =3D <0x17c2d000 0x1000>; + status =3D "disabled"; + }; + }; + + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; +}; --=20 2.43.0