From nobody Mon Sep 28 14:46:45 2026 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 119D935E55D for ; Fri, 21 Aug 2026 03:03:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787281414; cv=none; b=eiwJ5bizr+h2Lmx83ZcoJFIt4G8xeBBx3DE+c15LJjkLhpEJzHLwmT7LGFloqIJkUUeLKy1s60jRzFJXg6vkxIitkOY60HNWjbuz+gcogtlpuu6KLndgwzuISdGRA3EX09QO3r+97gDFsfu6R9n/ni8h6l0HjJyH5lGXoBdxC3c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787281414; c=relaxed/simple; bh=UIFM5M3YdbW6mYCh+6wGdniTiIWoponM/veuMwUGqD4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kZ1FFSgKCZUlXp/EcPqCtFacSwo/Wb31qp5jvDy8Gbaxdqfi89+fxjJJQuvFXSUoQXtSiLFTl25Nt9vF7PW4t6H6WYQVps+l72L2DDFZPk4Gor0mdKlNixJSxLwmsMEQG9OUshSWDjVaj+BMmYQ94rf+k8yErm4KKTD+RLgVQEQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=mswin.me; spf=none smtp.mailfrom=mswin.me; dkim=pass (2048-bit key) header.d=mswin-me.20251104.gappssmtp.com header.i=@mswin-me.20251104.gappssmtp.com header.b=bwz1mg5O; arc=none smtp.client-ip=209.85.218.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=mswin.me Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=mswin.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mswin-me.20251104.gappssmtp.com header.i=@mswin-me.20251104.gappssmtp.com header.b="bwz1mg5O" Received: by mail-ej1-f53.google.com with SMTP id a640c23a62f3a-c2055f5a993so60193266b.2 for ; Thu, 20 Aug 2026 20:03:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mswin-me.20251104.gappssmtp.com; s=20251104; t=1787281411; x=1787886211; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=M/djXBvzShY6dqn1dOwwRCbzxLVbePc2HPBHRPfCh3w=; b=bwz1mg5OIKujiLlokKFrYUsNon0ZCo0obMVZSe1X43vhCZ2ZMh8NMfFicTHN/UQAFE /d1LjeuOd0ytM6kyzzWeDrCRhqiPlZpgE6vGc31NS5tIXMT2gDkmKUb3xDR7vmQeDrNk QLvSndwAOwGv0AdRRTqkfzoiOt/LFmG3AI/fam1fXXcSJ3XhEcE4Wone8aCLvE8P51xA OeF3bjvsWfd0OztNzIRZB0ej5AULfCsdQ3vzWK1oE9f3iMFC9f2KyQhmaV6c72kpw9U8 S5cDG9zZJBwF7F6z02bDO1Crzr3yO1zJitA3iNYrDEzcqcuzPKghxMEZZrGu/bvwo0aB ZEhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787281411; x=1787886211; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=M/djXBvzShY6dqn1dOwwRCbzxLVbePc2HPBHRPfCh3w=; b=cj2mETNkqO1E6n27BY8Nq8sBMNCzssDECyj6jDIFaJW3mbrqcHI/JikinEvkU9zLyc qXzz+r1Jhza5eocoC3QCAa0fp85R9wdMXkAPB0TlAC0jmhsL6LqNQxjFRQn5CG3wZ8MN dwY6q4ypYxh6nHAuQ3SbRl1vAXJW0jlgu+0zP+rBk5CaWctwDSme65MJFpdpw1z1TYfM Lge4X34J2WJ5IOhMDpSAKpuGUMNrV//5Xn/WrndANk7T7f1wT6AhJlU/wUoZzrQGP91I N8DK3saxOa9WrF4LIpVShNHxKqBtIruFvMaFnfnWmHUjjIQ9ulQElclhC5d3c61jsrsv UdnA== X-Forwarded-Encrypted: i=1; AHgh+Rr7aBF/gdnJCK4/MwuxZPajc8vHrchC/UmqnZ3Sg8fmJyelf+z9VEOk0HdQeYoe1F4HT1UoqKQZfV1XIo4=@vger.kernel.org X-Gm-Message-State: AOJu0YxiwDwNHbFaqnel2KDYH6nh1RH67x4hbu4PyhuvsbHqbzfkLqap kV+VRORtfau+hPILWHN2zG8XVTOMM9XpqcBtNXRNtthVKvZuGHk7ponzwik1wFp2ddeJdocGZD6 RYuMgITOL6Q== X-Gm-Gg: AR+sD116jVWwIQ8ANEgC3YnygIRIkdm7SP1LslpYa1Z87AciqXTBwdA9W22hcUu+GKv EzxjcfNA4e4dDns+/WO0mgkBmuXvJK/xhoMnTpF9ft9xX8J1cNW01rPIc73t7CyvHzSZz3kctGQ JPOu6bxloWz23sX4/+ogDdXrF5i9L8E0KpV3ly++K5/rAtrgMVcbr03A1rg3GElOLqAP60LYOC6 sbd08dvkF1u9F4sj5HnQSpJnUmgyL6Ai3FtKzrAJ6fIL/PTdbvuapgoayE2tbs4qI/k0ptj/U4u 537JZspP1AuhyKW2Duw++dML1VDOKybBOkl3Hctj9pjERfuQkBtV3SICxId4G1Pb57mPlhwGLl+ T0kgzgxVJE/hOBbdOLLRyHeRFCcqW9c7uZTMrRa6ER4aX0N8FWg+9V2mj56eOTxS/NJkwr7srvG HN9mD8FWwhL7W+VBqqLvBxsmZKabiezJM/WaRyV/WRnSkKG83fuOXR6a0dl+MYf9KaHQ== X-Received: by 2002:a17:906:4787:b0:c24:6f60:3f7e with SMTP id a640c23a62f3a-c246f60404cmr227752166b.2.1787281411245; Thu, 20 Aug 2026 20:03:31 -0700 (PDT) Received: from zephyr.int.serkovo.ru ([85.17.200.167]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c24591df293sm274875866b.45.2026.08.20.20.03.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2026 20:03:30 -0700 (PDT) From: Roman Linev To: Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Roman Linev Subject: [PATCH 1/2] dt-bindings: thermal: qcom-tsens: add qcom,sm6125-tsens Date: Fri, 21 Aug 2026 06:03:24 +0300 Message-ID: <20260821030325.1823829-2-admin@mswin.me> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260821030325.1823829-1-admin@mswin.me> References: <20260821030325.1823829-1-admin@mswin.me> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SM6125 has a TSENS v2 block with 16 sensors. Its register and interrupt layout is identical to SM6115's, and it needs no calibration cells because v2 self-calibrates, so it is generic apart from the SoC-specific compatible. Document it in the v2 list, bound by the qcom,tsens-v2 fallback. Signed-off-by: Roman Linev Acked-by: Krzysztof Kozlowski Reviewed-by was given on the v1 content of 2/2; it is not carried onto --- Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Do= cumentation/devicetree/bindings/thermal/qcom-tsens.yaml index f0efaa834..cb808ce5c 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -78,6 +78,7 @@ properties: - qcom,sdm845-tsens - qcom,shikra-tsens - qcom,sm6115-tsens + - qcom,sm6125-tsens - qcom,sm6350-tsens - qcom,sm6375-tsens - qcom,sm8150-tsens --=20 2.55.0 From nobody Mon Sep 28 14:46:45 2026 Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A8193624C5 for ; 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Thu, 20 Aug 2026 20:03:33 -0700 (PDT) Received: from zephyr.int.serkovo.ru ([85.17.200.167]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c24591df293sm274875866b.45.2026.08.20.20.03.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2026 20:03:33 -0700 (PDT) From: Roman Linev To: Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Roman Linev Subject: [PATCH 2/2] arm64: dts: qcom: sm6125: add TSENS and thermal zones Date: Fri, 21 Aug 2026 06:03:25 +0300 Message-ID: <20260821030325.1823829-3-admin@mswin.me> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260821030325.1823829-1-admin@mswin.me> References: <20260821030325.1823829-1-admin@mswin.me> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SM6125 has a TSENS v2 controller with 16 sensors, at 0x04411000 (TM) and 0x04410000 (SROT), with SPI 275 as "uplow" and SPI 190 as "critical". The register and interrupt layout is identical to SM6115's, and being v2 the block self-calibrates, so it needs no qfprom nvmem cells and no new driver code: it binds through the existing qcom,tsens-v2 fallback. Add the controller and thermal zones for the 15 sensors that are used. The sensor-to-zone mapping comes from the downstream device tree for Xiaomi Mi A3 (laurel_sprout), cross-checked against mainline sm6115.dtsi, which agrees on sensors 2, 3, 4, 13, 14 and 15. Sensor 5 is not referenced downstream and is left out. No cooling devices are wired up: SM6125 has no GPU node upstream yet, so there is nothing to reference. The zones report temperature and carry passive and critical trips; cooling maps can be added alongside the consumers when those land. Tested on Xiaomi Mi A3 (sm6125): tsens0 binds at 4411000.thermal-sensor with no dmesg output, the thermal zone count goes from 5 to 20, and the 15 new die zones read 37.7-39.6 degrees Celsius at idle. Under a 660 s glmark2-es2-drm soak the hottest zone reached 52.2 degrees Celsius, well below its 85 degrees Celsius passive trip. Both SM6125 boards still build with no new dtc warnings. Signed-off-by: Roman Linev Acked-by: Krzysztof Kozlowski Reviewed-by was given on the v1 content of 2/2; it is not carried onto Reviewed-by: Abel Vesa --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 299 +++++++++++++++++++++++++++ 1 file changed, 299 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qco= m/sm6125.dtsi index 86de1560b..ed7fb5b75 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -719,6 +719,17 @@ spmi_bus: spmi@1c40000 { #interrupt-cells =3D <4>; }; =20 + tsens0: thermal-sensor@4411000 { + compatible =3D "qcom,sm6125-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x04411000 0x0 0x1ff>, /* TM */ + <0x0 0x04410000 0x0 0x8>; /* SROT */ + #qcom,sensors =3D <16>; + interrupts =3D , + ; + interrupt-names =3D "uplow", "critical"; + #thermal-sensor-cells =3D <1>; + }; + rpm_msg_ram: sram@45f0000 { compatible =3D "qcom,rpm-msg-ram"; reg =3D <0x0 0x045f0000 0x0 0x7000>; @@ -1634,6 +1645,294 @@ intc: interrupt-controller@f200000 { }; }; =20 + thermal-zones { + /* + * Sensor-to-zone mapping verified against the downstream + * laurel_sprout device tree (tsens@4410000, sensors 0..15) and + * cross-checked with mainline sm6115.dtsi, which agrees on + * sensors 2, 3, 4, 13, 14 and 15. Sensor 5 is unused by the + * downstream tree and is therefore left out. + * cpu4..cpu7 are the downstream cpu-1-{0..3} (cluster 1) sensors. + */ + aoss0-thermal { + thermal-sensors =3D <&tsens0 0>; + + trips { + trip-point0 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cdsp-thermal { + thermal-sensors =3D <&tsens0 1>; + + trips { + trip-point0 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + wlan-thermal { + thermal-sensors =3D <&tsens0 2>; + + trips { + trip-point0 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + camera-thermal { + thermal-sensors =3D <&tsens0 3>; + + trips { + trip-point0 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + video-thermal { + thermal-sensors =3D <&tsens0 4>; + + trips { + trip-point0 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpuss0-thermal { + thermal-sensors =3D <&tsens0 6>; + + trips { + trip-point0 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpuss1-thermal { + thermal-sensors =3D <&tsens0 7>; + + trips { + trip-point0 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpuss2-thermal { + thermal-sensors =3D <&tsens0 8>; + + trips { + trip-point0 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu4-thermal { + thermal-sensors =3D <&tsens0 9>; + + trips { + trip-point0 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu5-thermal { + thermal-sensors =3D <&tsens0 10>; + + trips { + trip-point0 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu6-thermal { + thermal-sensors =3D <&tsens0 11>; + + trips { + trip-point0 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu7-thermal { + thermal-sensors =3D <&tsens0 12>; + + trips { + trip-point0 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + modem0-thermal { + thermal-sensors =3D <&tsens0 13>; + + trips { + trip-point0 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + display-thermal { + thermal-sensors =3D <&tsens0 14>; + + trips { + trip-point0 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens0 15>; + + trips { + trip-point0 { + temperature =3D <85000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point2 { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + }; + timer { compatible =3D "arm,armv8-timer"; interrupts =3D , --=20 2.55.0