From nobody Mon Sep 28 14:47:00 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59A1D283142; Fri, 21 Aug 2026 00:18:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787271513; cv=none; b=dzYwUZv0PwjAc1/pVhXyLyJ/klLDWhh5Yc3iPA1JWIo20zdxx6ytm3Go3VpMhFFJ2QLkUEp2TuVtUiuP0s50qaP6ClJvQ0sjRBOn+w1+hkg0ML25jZ5HdaqMDEldg6R0KvJKX2N3vsA40xd7VOGf0kz53Bk6kRmbWvHrQ6OT4WE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787271513; c=relaxed/simple; bh=VEiYJraJEmJrQtYggUUXx1NjjLl3SB9Im8C7zQV6qBs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qWAtmB28WiptG8d5D1h1B7IocaUZRoPEfMjIcc+dLWIKDNXsxcBOVK17wE5S6Yjc8KPQL1w6RRTKi4Om9MgoTowoz8Vm0KsGtkHAYOgf0QO+ba2OqfkxrZ1hqP+hvuwNgDuGsCzzSG0rZ8x6oKrt1JDDhsjsQZprI3encNRpbj0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Q2chjRBR; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Q2chjRBR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1787271511; x=1818807511; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VEiYJraJEmJrQtYggUUXx1NjjLl3SB9Im8C7zQV6qBs=; b=Q2chjRBRKA8cDgl1xlmfeJno1mK1zjsBxa7bmkTtnLOW/hVsILjkXgSf LaXQmoz+YQdUrRugU3wZNYqHxVjI4GvyJGDYk4sSaYzOxbvnHldh6k+ur VsvBGZ7a8s+XstCFg9hXzekTgTVOQO6vXbwujp5VgUPFZO6dXgk4T7ij/ YGlxJOajFvcCAKtSOu6GoOHDZLNb3zLNAYplaxAOnFwhtqMC0BBHjzDRy rK1loClCsZn6QdMmlKn/1SeZ7/INgP5JbU+0uBslrJB9FyInkzR6K0J/Y tI2My1/0m71lWC1yGMY8GRFWiI8qrmvq/ojcFH83aZo+tCJ6oL1KBNpw7 w==; X-CSE-ConnectionGUID: yb1NsbGmTlWmQbCMY/w86Q== X-CSE-MsgGUID: plOO2VlLTDaPa2s19Qgbxg== X-IronPort-AV: E=McAfee;i="6800,10657,11881"; a="87839468" X-IronPort-AV: E=Sophos;i="6.25,234,1779174000"; d="scan'208";a="87839468" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Aug 2026 17:18:29 -0700 X-CSE-ConnectionGUID: pZNN/ESqTNOg2v/LZZnOyQ== X-CSE-MsgGUID: ouQOOyvkREubrq2aHA9Njw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,234,1779174000"; d="scan'208";a="261914967" Received: from rodrigoa-mobl1.amr.corp.intel.com (HELO tfalcon-desk.intel.com) ([10.124.221.152]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Aug 2026 17:18:29 -0700 From: Thomas Falcon To: Namhyung Kim Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Dapeng Mi Subject: [PATCH v5 1/6] perf mem: Fix size tracking for mem_lvl's in perf_script__meminfo_scnprintf() Date: Thu, 20 Aug 2026 19:18:14 -0500 Message-ID: <20260821001819.162277-2-thomas.falcon@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821001819.162277-1-thomas.falcon@intel.com> References: <20260821001819.162277-1-thomas.falcon@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When printing memory info in perf script, the entire size of the buffer is passed to perf_mem__lvl_scnprintf() instead of the remaining size. Pass the remaining buffer size instead. This issue was detected by sashiko during an internal code review. Assisted-by: Sashiko:gemini-3.1-pro-preview Fixes: fdefc3750e847 ("perf mem: Print memory operation type") Reviewed-by: Dapeng Mi Reviewed-by: Ian Rogers Signed-off-by: Thomas Falcon --- tools/perf/util/mem-events.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c index 0b49fce251fc..4e490f9cd348 100644 --- a/tools/perf/util/mem-events.c +++ b/tools/perf/util/mem-events.c @@ -610,7 +610,7 @@ int perf_script__meminfo_scnprintf(char *out, size_t sz= , const struct mem_info * i +=3D scnprintf(out, sz, "|OP "); i +=3D perf_mem__op_scnprintf(out + i, sz - i, mem_info); i +=3D scnprintf(out + i, sz - i, "|LVL "); - i +=3D perf_mem__lvl_scnprintf(out + i, sz, mem_info); + i +=3D perf_mem__lvl_scnprintf(out + i, sz - i, mem_info); i +=3D scnprintf(out + i, sz - i, "|SNP "); i +=3D perf_mem__snp_scnprintf(out + i, sz - i, mem_info); i +=3D scnprintf(out + i, sz - i, "|TLB "); --=20 2.55.0 From nobody Mon Sep 28 14:47:00 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B32B729B781; Fri, 21 Aug 2026 00:18:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787271513; cv=none; b=CbJ4nnNmtfhvVlREBWB2xii699sat0wl5cYmddDsjdrjvATry/zNLNmmcXXmQVyvNjKx3vfdJmrr3FniBevMIl6NTj/9vMO6z1pp+DGnRuOq7Nue8NPgrlZtcJXmAu9+/tjTcTTEkOL+nwtl+ARDtNHKj5xREhvuF1n2wf65n4w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787271513; c=relaxed/simple; bh=C+Uq7VRxQZa3b95gCFrSjIwxEqKlk+wdE+hcTVvkqjY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rhp9Mn9hXvF8h3Vfwq7gtTxW1NdHR3/8Nr56NObZY0sZYHceu59OVu3UzWw5Deh6EZrsEcjckk6rCX/T8bZaWoGyw5u9qRb96XiBoCx6SAlRvymYA/x2niSsGmCueWaNAdaapQ3Rmhh0hTlbn8E0u+ik69MOgf8xSNUwm5O4VPM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=mPaD0MB+; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="mPaD0MB+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1787271511; x=1818807511; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=C+Uq7VRxQZa3b95gCFrSjIwxEqKlk+wdE+hcTVvkqjY=; b=mPaD0MB+1nqXXW4q8eVJezcF9SE/y3DC9odHlhAYmVPP6iaMSkQXZ9VN Sv2HehSKaFK1HIOuThKn1Qol6oy5NRBSNaciEMHjAfeBjG3TykR9ed2FV +wgI5gDykwBCQ0AbjTXb9F3KLwhby1t3uZ+FsvQEAyO52RUHs/OJP7eKo oovUMCNZCWolSzNoLseyIGqJaGe7tNrlsi/vlMfD0qO7Hix6/tY377qcs kXeTK7SzWqkDUAGIvC94gUep3DtxczgTG222PuZFh/DgriYBz+gekVwXj NVLeiUnNpK5LEEElRqsrw2yYRTrMvjx+XjqQWUFwvgfNptBHQyDUNzEkr A==; X-CSE-ConnectionGUID: xngc7fUxS/et3uijBKx9GQ== X-CSE-MsgGUID: kC0+0yMkQ/i6OQzZwnv/2g== X-IronPort-AV: E=McAfee;i="6800,10657,11881"; a="87839477" X-IronPort-AV: E=Sophos;i="6.25,234,1779174000"; d="scan'208";a="87839477" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Aug 2026 17:18:30 -0700 X-CSE-ConnectionGUID: Lfp+q44/Q/C1CQ0hOA8sXw== X-CSE-MsgGUID: Nkc1cJSFRhu46t14zHTT6w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,234,1779174000"; d="scan'208";a="261914971" Received: from rodrigoa-mobl1.amr.corp.intel.com (HELO tfalcon-desk.intel.com) ([10.124.221.152]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Aug 2026 17:18:29 -0700 From: Thomas Falcon To: Namhyung Kim Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Dapeng Mi Subject: [PATCH v5 2/6] perf mem: Add support for printing PERF_MEM_LVLNUM_L0 Date: Thu, 20 Aug 2026 19:18:15 -0500 Message-ID: <20260821001819.162277-3-thomas.falcon@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821001819.162277-1-thomas.falcon@intel.com> References: <20260821001819.162277-1-thomas.falcon@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Dapeng Mi Add support for printing PERF_MEM_LVLNUM_L0 in perf mem report. The L0 cache is newly added a small piece of cache which is the closest, lowest-latency memory cache tied directly to the execution pipeline. The table "Table 9-4. Data Source Field Encodings for Panther Cove and Coyote Cove Microarchitectures" in the ISE doc chapter "9.2.1 Panther Cove and Coyote Cove Microarchitectures Memory Auxiliary Field Layout"[1] indicates the code "01H" means the "L0 Hit - Minimal latency core cache hit. This request was satisfied by the L0 data cache." [1]: https://www.intel.com/content/www/us/en/content-details/922690/intel-a= rchitecture-instruction-set-extensions-programming-reference.html Assisted-by: Sashiko:gemini-3.1-pro-preview Reviewed-by: Dapeng Mi Reviewed-by: Ian Rogers Signed-off-by: Dapeng Mi Signed-off-by: Thomas Falcon --- v3: Included more information about the L0 cache in the commit message. --- tools/perf/Documentation/perf-record.txt | 2 +- tools/perf/util/bpf-filter.l | 1 + tools/perf/util/mem-events.c | 5 +++++ tools/perf/util/mem-events.h | 1 + 4 files changed, 8 insertions(+), 1 deletion(-) diff --git a/tools/perf/Documentation/perf-record.txt b/tools/perf/Document= ation/perf-record.txt index 178f483140ed..b54032efe41c 100644 --- a/tools/perf/Documentation/perf-record.txt +++ b/tools/perf/Documentation/perf-record.txt @@ -212,7 +212,7 @@ OPTIONS The can be one of: (for any term) na, load, store, pfetch, exec (for mem_op) - l1, l2, l3, l4, cxl, io, any_cache, lfb, ram, pmem (for mem_lvl) + l0, l1, l2, l3, l4, cxl, io, any_cache, lfb, ram, pmem (for mem_lvl) na, none, hit, miss, hitm, fwd, peer (for mem_snoop) remote (for mem_remote) na, locked (for mem_locked) diff --git a/tools/perf/util/bpf-filter.l b/tools/perf/util/bpf-filter.l index 6aa65ade3385..1be9df6550fc 100644 --- a/tools/perf/util/bpf-filter.l +++ b/tools/perf/util/bpf-filter.l @@ -131,6 +131,7 @@ store { return constant(PERF_MEM_OP_STORE); } pfetch { return constant(PERF_MEM_OP_PFETCH); } exec { return constant(PERF_MEM_OP_EXEC); } =20 +l0 { return constant(PERF_MEM_LVLNUM_L0); } l1 { return constant(PERF_MEM_LVLNUM_L1); } l2 { return constant(PERF_MEM_LVLNUM_L2); } l3 { return constant(PERF_MEM_LVLNUM_L3); } diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c index 4e490f9cd348..4fd48fd20055 100644 --- a/tools/perf/util/mem-events.c +++ b/tools/perf/util/mem-events.c @@ -391,6 +391,7 @@ static const char * const mem_lvlnum[] =3D { [PERF_MEM_LVLNUM_L4] =3D "L4", [PERF_MEM_LVLNUM_L2_MHB] =3D "L2 MHB", [PERF_MEM_LVLNUM_MSC] =3D "Memory-side Cache", + [PERF_MEM_LVLNUM_L0] =3D "L0", [PERF_MEM_LVLNUM_UNC] =3D "Uncached", [PERF_MEM_LVLNUM_CXL] =3D "CXL", [PERF_MEM_LVLNUM_IO] =3D "I/O", @@ -831,6 +832,8 @@ int mem_stat_index(const enum mem_stat_type mst, const = u64 val) } case PERF_MEM_STAT_CACHE: switch (src.mem_lvl_num) { + case PERF_MEM_LVLNUM_L0: + return MEM_STAT_CACHE_L0; case PERF_MEM_LVLNUM_L1: return MEM_STAT_CACHE_L1; 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20 Aug 2026 17:18:31 -0700 X-CSE-ConnectionGUID: rYZqcdMKQjyRyLAJ5qk8wA== X-CSE-MsgGUID: Zjeoyjm7QJCXkpT3YyIbSg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,234,1779174000"; d="scan'208";a="261914975" Received: from rodrigoa-mobl1.amr.corp.intel.com (HELO tfalcon-desk.intel.com) ([10.124.221.152]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Aug 2026 17:18:30 -0700 From: Thomas Falcon To: Namhyung Kim Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Dapeng Mi Subject: [PATCH v5 3/6] perf header: Support memory ranges Date: Thu, 20 Aug 2026 19:18:16 -0500 Message-ID: <20260821001819.162277-4-thomas.falcon@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821001819.162277-1-thomas.falcon@intel.com> References: <20260821001819.162277-1-thomas.falcon@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Memory ranges were created to track different types of memory, such as persistent, high bandwidth, or CXL-attached, that may be present on a system for performance monitoring and resource control purposes. Memory range data are parsed from the ACPI MRRM table and exposed to userspace tools via sysfs [1]. Memory range data is read from: /sys/firmware/acpi/memory_ranges/rangeX With the following attributes: u64 base; u64 length; int node; u8 local_region_id; u8 remote_region_id; Read memory range data from sysfs if present and save it in the header of the perf data file under a new feature bit, HEADER_MEMORY_RANGES (35). Memory range data can be viewed with the --header or --header-only options of perf-report and perf-script. Example output: # memory ranges (nr 5): # range0: [0x0000000000000000-0x00000000bfffffff], node =3D 0, local_regio= n_id =3D 0, remote_region_id =3D 255 # range1: [0x0000000100000000-0x000000203fffffff], node =3D 0, local_regio= n_id =3D 0, remote_region_id =3D 255 # range2: [0x0000008000000000-0x0000027fffffffff], node =3D -2, local_regi= on_id =3D 1, remote_region_id =3D 255 # range3: [0x0000028000000000-0x0000047fffffffff], node =3D -2, local_regi= on_id =3D 1, remote_region_id =3D 255 # range4: [0x0000048000000000-0x000004ffffffffff], node =3D -2, local_regi= on_id =3D 1, remote_region_id =3D 255 [1]: https://lore.kernel.org/lkml/20250505173819.419271-1-tony.luck@intel.c= om/ Assisted-by: Sashiko:gemini-3.1-pro-preview Assisted-by: GitHub-Copilot:claude-opus-4-8 Reviewed-by: Ian Rogers Signed-off-by: Thomas Falcon --- v4: -- Fixed bounds checking for local and remote region IDs in memory_range__read(), which made region "255" invalid v3: -- Added missing ff->size check in process_memory_ranges() -- used open/openat to read memory range sysfs files in memory_range__read() -- Removed path name and file name buffers in memory_range__read(), instead pass path name from as a parameter from memory_range__parse() -- use calloc instead of zalloc in memory_range__parse() and process_memory_ranges() -- Removed redundant check for existance of memory range directory in memory_range__read() -- Included examples of memory range output in commit message v2: -- Added check for NULL return of sysfs__mountpoint() when parsing memory ranges in sysfs -- increased MAX_MEMORY_RANGES sanity check from 64 to 256 based on ACPI MRRM table implementation in Linux kernel -- added comment for MAX_MEMORY_RANGES to clarify that it is a sanity check for malformed perf.data files -- removed a line of code was removed from util/env.h but was added back in v1 due to bad rebase --- .../Documentation/perf.data-file-format.txt | 13 ++ tools/perf/builtin-inject.c | 1 + tools/perf/util/env.c | 1 + tools/perf/util/env.h | 10 + tools/perf/util/header.c | 203 ++++++++++++++++++ tools/perf/util/header.h | 1 + 6 files changed, 229 insertions(+) diff --git a/tools/perf/Documentation/perf.data-file-format.txt b/tools/per= f/Documentation/perf.data-file-format.txt index b90cba9168f8..1f8e7d8e9ae2 100644 --- a/tools/perf/Documentation/perf.data-file-format.txt +++ b/tools/perf/Documentation/perf.data-file-format.txt @@ -478,6 +478,19 @@ The size of the cacheline in bytes. Format: =20 unsigned int cln_size; =20 + HEADER_MEMORY_RANGES =3D 35, + +List of memory ranges. The format of the data is as below. + +u32 nr_memory_ranges; +struct memory_range { + u64 base; + u64 length; + int node; + u8 local_region_id; + u8 remote_region_id; +}; [nr_memory_ranges] + other bits are reserved and should be ignored for now HEADER_FEAT_BITS =3D 256, =20 diff --git a/tools/perf/builtin-inject.c b/tools/perf/builtin-inject.c index 70bbfad5653e..169617a884d3 100644 --- a/tools/perf/builtin-inject.c +++ b/tools/perf/builtin-inject.c @@ -2306,6 +2306,7 @@ static bool keep_feat(struct perf_inject *inject, int= feat) case HEADER_PMU_CAPS: case HEADER_CPU_DOMAIN_INFO: case HEADER_CLN_SIZE: + case HEADER_MEMORY_RANGES: return true; /* Information that can be updated */ case HEADER_BUILD_ID: diff --git a/tools/perf/util/env.c b/tools/perf/util/env.c index c0e2b9d5f0b2..50993b0dedc5 100644 --- a/tools/perf/util/env.c +++ b/tools/perf/util/env.c @@ -297,6 +297,7 @@ void perf_env__exit(struct perf_env *env) zfree(&env->pmu_caps[i].pmu_name); } zfree(&env->pmu_caps); + zfree(&env->memory_ranges); free_cpu_domain_info(env->cpu_domain, env->schedstat_version, env->nr_cpu= s_avail); } =20 diff --git a/tools/perf/util/env.h b/tools/perf/util/env.h index 7acca39b42ff..23d35425efe3 100644 --- a/tools/perf/util/env.h +++ b/tools/perf/util/env.h @@ -68,6 +68,14 @@ struct cpu_domain_map { struct domain_info **domains; }; =20 +struct memory_range { + u64 base; + u64 length; + int node; + u8 local_region_id; + u8 remote_region_id; +}; + struct perf_env { char *hostname; char *os_release; @@ -100,6 +108,7 @@ struct perf_env { int nr_cpu_pmu_caps; int nr_hybrid_nodes; int nr_pmus_with_caps; + int nr_memory_ranges; char *cmdline; const char **cmdline_argv; char *sibling_cores; @@ -122,6 +131,7 @@ struct perf_env { unsigned long long memory_bsize; struct hybrid_node *hybrid_nodes; struct pmu_caps *pmu_caps; + struct memory_range *memory_ranges; #ifdef HAVE_LIBBPF_SUPPORT /* * bpf_info_lock protects bpf rbtrees. This is needed because the diff --git a/tools/perf/util/header.c b/tools/perf/util/header.c index 7db7da090a1e..83416ce395d7 100644 --- a/tools/perf/util/header.c +++ b/tools/perf/util/header.c @@ -92,6 +92,7 @@ #define MAX_PMU_CAPS 512 #define MAX_PMU_MAPPINGS 4096 #define MAX_SCHED_DOMAINS 64 +#define MAX_MEMORY_RANGES 256 =20 /* * magic2 =3D "PERFILE2" @@ -1892,6 +1893,132 @@ static int write_cpu_domain_info(struct feat_fd *ff, return ret; } =20 +static int memory_range__read(struct memory_range *range, const char *path) +{ + char buf[32]; + ssize_t n; + int dfd, fd, tmp, ret =3D -1; + + dfd =3D open(path, O_RDONLY | O_DIRECTORY); + if (dfd < 0) + return -1; + +#define _R(name, dst, conv) \ + fd =3D openat(dfd, name, O_RDONLY); \ + if (fd < 0) \ + goto out; \ + n =3D read(fd, buf, sizeof(buf) - 1); \ + close(fd); \ + if (n <=3D 0) \ + goto out; \ + buf[n] =3D '\0'; \ + dst =3D conv(buf, NULL, 0); + + _R("base", range->base, strtoull); + _R("length", range->length, strtoull); + _R("node", range->node, strtol); + _R("local_region_id", tmp, strtol); + if (tmp < 0 || tmp > UINT8_MAX) + goto out; + range->local_region_id =3D tmp; + _R("remote_region_id", tmp, strtol); + if (tmp < 0 || tmp > UINT8_MAX) + goto out; + range->remote_region_id =3D tmp; +#undef _R + + ret =3D 0; +out: + close(dfd); + return ret; +} + +static int memory_range__parse(struct memory_range **ranges) +{ + const char *sysfs =3D sysfs__mountpoint(); + int i, err, nr_memory_ranges =3D 0; + char path[PATH_MAX]; + struct stat st; + + if (!sysfs) + return 0; + + scnprintf(path, PATH_MAX, "%s/firmware/acpi/memory_ranges", sysfs); + if (stat(path, &st)) + return 0; + + while (1) { + scnprintf(path, PATH_MAX, + "%s/firmware/acpi/memory_ranges/range%d", + sysfs, nr_memory_ranges); + if (stat(path, &st)) + break; + + nr_memory_ranges++; + } + + if (nr_memory_ranges =3D=3D 0) + return 0; + + *ranges =3D calloc(nr_memory_ranges, sizeof(struct memory_range)); + if (!(*ranges)) + return -ENOMEM; + + for (i =3D 0; i < nr_memory_ranges; i++) { + struct memory_range range; + + scnprintf(path, PATH_MAX, + "%s/firmware/acpi/memory_ranges/range%d", sysfs, i); + err =3D memory_range__read(&range, path); + if (err < 0) + goto out_error; + + (*ranges)[i] =3D range; + } + + return nr_memory_ranges; + +out_error: + zfree(ranges); + return -1; +} + +static int write_memory_ranges(struct feat_fd *ff, + struct evlist *evlist __maybe_unused) +{ + struct memory_range *ranges =3D NULL; + int nr_memory_ranges =3D 0, ret; + + nr_memory_ranges =3D memory_range__parse(&ranges); + if (nr_memory_ranges < 0) + return nr_memory_ranges; + + ret =3D do_write(ff, &nr_memory_ranges, sizeof(nr_memory_ranges)); + if (ret < 0) + goto out; + + for (int i =3D 0; i < nr_memory_ranges; i++) { + ret =3D do_write(ff, &ranges[i].base, sizeof(u64)); + if (ret < 0) + goto out; + ret =3D do_write(ff, &ranges[i].length, sizeof(u64)); + if (ret < 0) + goto out; + ret =3D do_write(ff, &ranges[i].node, sizeof(u32)); + if (ret < 0) + goto out; + ret =3D do_write(ff, &ranges[i].local_region_id, sizeof(u8)); + if (ret < 0) + goto out; + ret =3D do_write(ff, &ranges[i].remote_region_id, sizeof(u8)); + if (ret < 0) + goto out; + } +out: + zfree(&ranges); + return ret; +} + static void print_hostname(struct feat_fd *ff, FILE *fp) { fprintf(fp, "# hostname : %s\n", ff->ph->env.hostname); @@ -2629,6 +2756,23 @@ static void print_cpu_domain_info(struct feat_fd *ff= , FILE *fp) } } =20 +static void print_memory_ranges(struct feat_fd *ff, FILE *fp) +{ + struct memory_range *ranges =3D ff->ph->env.memory_ranges; + int nr_memory_ranges =3D ff->ph->env.nr_memory_ranges; + int i; + + fprintf(fp, "# memory ranges (nr %d):\n", nr_memory_ranges); + + for (i =3D 0; i < nr_memory_ranges; i++) { + fprintf(fp, "# range%u: [0x%016" PRIx64 "-0x%016" PRIx64, + i, ranges[i].base, ranges[i].base + ranges[i].length - 1); + fprintf(fp, "], node =3D %d, local_region_id =3D %d, remote_region_id = =3D %d\n", + ranges[i].node, ranges[i].local_region_id, + ranges[i].remote_region_id); + } +} + static int __event_process_build_id(struct perf_record_header_build_id *be= v, char *filename, struct perf_session *session) @@ -4202,6 +4346,64 @@ static int process_cpu_domain_info(struct feat_fd *f= f, void *data __maybe_unused return ret; } =20 +static int process_memory_ranges(struct feat_fd *ff, void *data __maybe_un= used) +{ + struct perf_env *env =3D &ff->ph->env; + struct memory_range *ranges, *r; + u32 nr_memory_ranges, i; + + if (do_read_u32(ff, &nr_memory_ranges)) + return -1; + + if (!nr_memory_ranges) { + pr_debug("memory ranges not available\n"); + return 0; + } + + /* According to version 1.1 of the ACPI MRRM table, the maximum + * number of memory regions can be at most 255. Do a sanity check + * here to guard against a malformed perf.data file. + */ + if (nr_memory_ranges >=3D MAX_MEMORY_RANGES) { + pr_err("Invalid memory_ranges: nr_memory_ranges (%u) > %u\n", + nr_memory_ranges, MAX_MEMORY_RANGES); + return -1; + } + + if (ff->size < sizeof(u32) + nr_memory_ranges * (2 * sizeof(u64) + sizeof= (u32) + 2 * sizeof(u8))) { + pr_err("Invalid HEADER_MEMORY_RANGES: section too small (%zu) for %u ran= ge entries\n", + ff->size, nr_memory_ranges); + return -1; + } + + ranges =3D calloc(nr_memory_ranges, sizeof(*ranges)); + if (!ranges) + return -1; + + for (i =3D 0; i < nr_memory_ranges; i++) { + r =3D &ranges[i]; + + if (do_read_u64(ff, &r->base)) + goto error; + if (do_read_u64(ff, &r->length)) + goto error; + if (do_read_u32(ff, (u32 *) &r->node)) + goto error; + if (__do_read(ff, &r->local_region_id, sizeof(u8))) + goto error; + if (__do_read(ff, &r->remote_region_id, sizeof(u8))) + goto error; + } + + env->memory_ranges =3D ranges; + env->nr_memory_ranges =3D nr_memory_ranges; + + return 0; +error: + zfree(&ranges); + return -1; +} + #define FEAT_OPR(n, func, __full_only) \ [HEADER_##n] =3D { \ .name =3D __stringify(n), \ @@ -4266,6 +4468,7 @@ const struct perf_header_feature_ops feat_ops[HEADER_= LAST_FEATURE] =3D { FEAT_OPR(CPU_DOMAIN_INFO, cpu_domain_info, true), FEAT_OPR(E_MACHINE, e_machine, false), FEAT_OPR(CLN_SIZE, cln_size, false), + FEAT_OPR(MEMORY_RANGES, memory_ranges, false), }; =20 struct header_print_data { diff --git a/tools/perf/util/header.h b/tools/perf/util/header.h index 5e03f884b7cc..765037762758 100644 --- a/tools/perf/util/header.h +++ b/tools/perf/util/header.h @@ -56,6 +56,7 @@ enum { HEADER_CPU_DOMAIN_INFO, HEADER_E_MACHINE, HEADER_CLN_SIZE, + HEADER_MEMORY_RANGES, HEADER_LAST_FEATURE, HEADER_FEAT_BITS =3D 256, }; --=20 2.55.0 From nobody Mon Sep 28 14:47:00 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 987F325EF87; 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charset="utf-8" From: Dapeng Mi Add memory region field to the cacheline list view to help users identify the memory region to which the cacheline belongs. The memory region field was included with the introduction of support for the Off-module Response facility (OMR) [1] in Intel's Diamond Rapids and Nova Lake architectures. An example of the new perf c2c output including the memory region field is shown below: Shared Data Cache Line Table (112 entries, sorted on Total HITMs) --------------- Cacheline -------------- Tot ------- Load Hitm= ------- Total Total Total Index Address Region Node PA cnt Hitm Total LclHitm = RmtHitm records Loads Stores 0 0xff1b7032a1e8c5c0 N/A 1 47 2.25% 50 44 = 6 1024 1023 1 1 0xff1b6ff3255bb880 N/A 0 11 1.62% 36 34 = 2 96 93 4 2 0xff1b70328e3b9880 N/A 1 13 1.49% 33 33 = 0 100 91 9 3 0xff1b70328b023800 N/A 1 1 1.40% 31 14 = 17 52 48 4 4 0xff1b70328e3b9c00 N/A 1 1 1.31% 29 27 = 2 67 33 34 5 0xff1b70328b0237c0 N/A 1 1 1.26% 28 10 = 18 154 150 4 6 0xff1b6ff3255bbc00 N/A 0 1 1.13% 25 25 = 0 48 25 23 7 0xff1b6ff3255bba40 N/A 0 1 0.99% 22 22 = 0 46 23 23 8 0xff3ab9ba50255c80 N/A N/A 0 0.77% 17 15 = 2 35 35 0 9 0xff3ab9ba503e3040 N/A N/A 0 0.77% 17 11 = 6 37 37 1 10 0xff1b703289e88f40 N/A 1 33 0.72% 16 9 = 7 69 63 6 11 0xff1b70328e3b9a40 N/A 1 1 0.68% 15 15 = 0 43 17 26 12 0xff1b7032c9fd6a40 N/A 1 15 0.68% 15 15 = 0 57 54 4 13 0xff1b7032a1e8c980 N/A 1 27 0.54% 12 11 = 1 761 761 0 14 0xff1b70727ffd57c0 N/A 1 7 0.54% 12 12 = 0 219 218 1 15 0xffffffffaefe2380 N/A 1 1 0.50% 11 8 = 3 14 14 0 Note: DMR simics does not support memory regions. Since the output is captured on SPR, the memory region field shows "N/A" for all cachelines. [1]: https://lore.kernel.org/all/20260114011750.350569-1-dapeng1.mi@linux.i= ntel.com/ Assisted-by: Sashiko:gemini-3.1-pro-preview Assisted-by: GitHub-Copilot:claude-opus-4-8 Reviewed-by: Ian Rogers Signed-off-by: Dapeng Mi Signed-off-by: Thomas Falcon --- v5: make the cacheline header span and ui_quirks() width fixup depend on memory-region availability (Namhyung Kim) v4: correctly handle output_str memory allocation failure v3: make memory region reporting conditional on feature bit --- tools/perf/builtin-c2c.c | 95 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 86 insertions(+), 9 deletions(-) diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c index bc16a57e0927..ce324fc59947 100644 --- a/tools/perf/builtin-c2c.c +++ b/tools/perf/builtin-c2c.c @@ -77,6 +77,7 @@ struct c2c_hist_entry { unsigned long *nodeset; struct c2c_stats *node_stats; unsigned int cacheline_idx; + unsigned int mem_region; =20 struct compute_stats cstats; =20 @@ -107,6 +108,7 @@ struct perf_c2c { =20 bool show_src; bool show_all; + bool show_mem_region; bool use_stdio; bool stats_only; bool symbol_full; @@ -283,6 +285,18 @@ static void c2c_he__set_node(struct c2c_hist_entry *c2= c_he, } } =20 +static void c2c_he__set_mem_region(struct c2c_hist_entry *c2c_he, + unsigned int mem_region) +{ + if (WARN_ONCE(mem_region > PERF_MEM_REGION_MEM7, + "WARNING: invalid memory region ID\n")) + return; + + /* Update mem_region only if it really accesses memory */ + if (mem_region >=3D PERF_MEM_REGION_MMIO) + c2c_he->mem_region =3D mem_region; +} + static void compute_stats(struct c2c_hist_entry *c2c_he, struct c2c_stats *stats, u64 weight) @@ -341,6 +355,7 @@ static int process_sample_event(const struct perf_tool = *tool __maybe_unused, struct addr_location al; struct mem_info *mi =3D NULL; struct callchain_cursor *cursor; + unsigned int mem_region; int ret; =20 addr_location__init(&al); @@ -368,6 +383,7 @@ static int process_sample_event(const struct perf_tool = *tool __maybe_unused, } =20 c2c_decode_stats(&stats, mi); + mem_region =3D mem_info__data_src(mi)->mem_region; =20 he =3D hists__add_entry_ops(&c2c_hists->hists, &c2c_entry_ops, &al, NULL, NULL, mi, NULL, @@ -384,6 +400,7 @@ static int process_sample_event(const struct perf_tool = *tool __maybe_unused, c2c_he__set_cpu(c2c_he, sample); c2c_he__set_node(c2c_he, sample); c2c_he__set_evsel(c2c_he, evsel); + c2c_he__set_mem_region(c2c_he, mem_region); =20 hists__inc_nr_samples(&c2c_hists->hists, he->filtered); =20 @@ -437,6 +454,7 @@ static int process_sample_event(const struct perf_tool = *tool __maybe_unused, c2c_he__set_cpu(c2c_he, sample); c2c_he__set_node(c2c_he, sample); c2c_he__set_evsel(c2c_he, evsel); + c2c_he__set_mem_region(c2c_he, mem_region); =20 hists__inc_nr_samples(&c2c_hists->hists, he->filtered); ret =3D hist_entry__append_callchain(he, sample); @@ -605,6 +623,30 @@ dcacheline_node_count(struct perf_hpp_fmt *fmt, struct= perf_hpp *hpp, return scnprintf(hpp->buf, hpp->size, "%*lu", width, c2c_he->paddr_cnt); } =20 +static int +dcacheline_node_mem_region(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + int width =3D c2c_width(fmt, hpp, he->hists); + struct c2c_hist_entry *c2c_he; + unsigned int mem_region; + char buf[20]; + + c2c_he =3D container_of(he, struct c2c_hist_entry, he); + mem_region =3D c2c_he->mem_region; + + if (mem_region =3D=3D PERF_MEM_REGION_NA) + scnprintf(buf, sizeof(buf), "N/A"); + /* mem_region could only be >=3D PERF_MEM_REGION_MMIO */ + else if (mem_region =3D=3D PERF_MEM_REGION_MMIO) + scnprintf(buf, sizeof(buf), "MMIO"); + else + scnprintf(buf, sizeof(buf), "0x%x", + mem_region - PERF_MEM_REGION_MEM0); + + return scnprintf(hpp->buf, hpp->size, "%*s", width, buf); +} + static int offset_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, struct hist_entry *he) { @@ -1442,6 +1484,14 @@ static struct c2c_dimension dim_dcacheline_node =3D { .width =3D 4, }; =20 +static struct c2c_dimension dim_dcacheline_mem_region =3D { + .header =3D HEADER_LOW("Region"), + .name =3D "dcacheline_mem_region", + .cmp =3D empty_cmp, + .entry =3D dcacheline_node_mem_region, + .width =3D 6, +}; + static struct c2c_dimension dim_dcacheline_count =3D { .header =3D HEADER_LOW("PA cnt"), .name =3D "dcacheline_count", @@ -1873,6 +1923,7 @@ static struct c2c_dimension dim_dcacheline_num_empty = =3D { =20 static struct c2c_dimension *dimensions[] =3D { &dim_dcacheline, + &dim_dcacheline_mem_region, &dim_dcacheline_node, &dim_dcacheline_count, &dim_offset, @@ -2942,8 +2993,11 @@ static int ui_quirks(void) /* Fix the zero line for dcacheline column. */ buf =3D fill_line(chk_double_cl ? "Double-Cacheline" : "Cacheline", dim_dcacheline.width + + (c2c.show_mem_region ? + dim_dcacheline_mem_region.width : 0) + dim_dcacheline_node.width + - dim_dcacheline_count.width + 4); + dim_dcacheline_count.width + + (c2c.show_mem_region ? 6 : 4)); if (!buf) return -ENOMEM; =20 @@ -3195,7 +3249,8 @@ static int perf_c2c__report(int argc, const char **ar= gv) OPT_END() }; int err =3D 0; - const char *output_str, *sort_str =3D NULL; + const char *sort_str =3D NULL; + char *output_str =3D NULL; struct perf_env *env; =20 annotation_options__init(); @@ -3360,9 +3415,16 @@ static int perf_c2c__report(int argc, const char **a= rgv) goto out_mem2node; } =20 - if (c2c.display !=3D DISPLAY_SNP_PEER) - output_str =3D "cl_idx," + c2c.show_mem_region =3D perf_header__has_feat(&session->header, + HEADER_MEMORY_RANGES); + if (c2c.show_mem_region) + dim_dcacheline.header.line[0].span =3D 3; + + if (c2c.display !=3D DISPLAY_SNP_PEER) { + if (asprintf(&output_str, + "cl_idx," "dcacheline," + "%s" "dcacheline_node," "dcacheline_count," "percent_costly_snoop," @@ -3374,10 +3436,17 @@ static int perf_c2c__report(int argc, const char **= argv) "ld_fbhit,ld_l1hit,ld_l2hit," "ld_lclhit,lcl_hitm," "ld_rmthit,rmt_hitm," - "dram_lcl,dram_rmt"; - else - output_str =3D "cl_idx," + "dram_lcl,dram_rmt", + c2c.show_mem_region ? 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Memory region is found in the mem_region field of the memory information data source. This field was included with the introduction of support for the Off-module Response facility (OMR) [1] in Intel's Diamond Rapids and Nova Lake Architectures. An example of perf-script output with the new memory region field is shown below: random 10e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Y= es|BLK N/A|Region N/A 7f32ae64a2ec random 2411a68201042 |OP LOAD|LVL RAM hit|SNP Hit|TLB L1 or L2 hit|LCK N= o|BLK N/A|Region Mem-1 561de7f8910a random 10e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Y= es|BLK N/A|Region N/A 7f32ae64a2d0 random 20e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Y= es|BLK Data|Region N/A 7f32ae64a2d0 random 20e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Y= es|BLK Data|Region N/A 7f32ae64a2d0 random 10e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Y= es|BLK N/A|Region N/A 7f32ae64a2ec random 10e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Y= es|BLK N/A|Region N/A 7f32ae64a2d0 random 10e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Y= es|BLK N/A|Region N/A 7f32ae64a2d0 random 2411a68201042 |OP LOAD|LVL RAM hit|SNP Hit|TLB L1 or L2 hit|LCK N= o|BLK N/A|Region Mem-1 561de7f8910a random 10e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Y= es|BLK N/A|Region N/A 7f32ae64a2ec random 10e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Y= es|BLK N/A|Region N/A 7f32ae64a2d0 [1]: https://lore.kernel.org/all/20260114011750.350569-1-dapeng1.mi@linux.i= ntel.com/ Assisted-by: Sashiko:gemini-3.1-pro-preview Assisted-by: GitHub-Copilot:claude-opus-4-8 Reviewed-by: Ian Rogers Signed-off-by: Dapeng Mi Signed-off-by: Thomas Falcon --- v4: Drop the global show-region flag; pass perf_session to perf_script__meminfo_scnprintf() and gate the Region field on the feature bit, with a pipe-mode fallback v3: make memory region reporting conditional on feature bit --- tools/perf/builtin-script.c | 13 +-- tools/perf/util/mem-events.c | 86 ++++++++++++++++++- tools/perf/util/mem-events.h | 4 +- .../scripting-engines/trace-event-python.c | 5 +- 4 files changed, 98 insertions(+), 10 deletions(-) diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c index ad8ca08ceb5f..c7454155038d 100644 --- a/tools/perf/builtin-script.c +++ b/tools/perf/builtin-script.c @@ -2078,11 +2078,12 @@ static int evlist__max_name_len(struct evlist *evli= st) return max; } =20 -static int data_src__fprintf(u64 data_src, FILE *fp) +static int data_src__fprintf(struct perf_session *session, + u64 data_src, FILE *fp) { struct mem_info *mi =3D mem_info__new(); - char decode[100]; - char out[100]; + char decode[200]; + char out[200]; static int maxlen; int len; =20 @@ -2090,10 +2091,10 @@ static int data_src__fprintf(u64 data_src, FILE *fp) return -ENOMEM; =20 mem_info__data_src(mi)->val =3D data_src; - perf_script__meminfo_scnprintf(decode, 100, mi); + perf_script__meminfo_scnprintf(decode, 200, mi, session); mem_info__put(mi); =20 - len =3D scnprintf(out, 100, "%16" PRIx64 " %s", data_src, decode); + len =3D scnprintf(out, 200, "%16" PRIx64 " %s", data_src, decode); if (maxlen < len) maxlen =3D len; =20 @@ -2487,7 +2488,7 @@ static void process_event(struct perf_script *script, perf_sample__fprintf_addr(sample, thread, evsel, fp); =20 if (PRINT_FIELD(DATA_SRC)) - data_src__fprintf(sample->data_src, fp); + data_src__fprintf(evsel__session(evsel), sample->data_src, fp); =20 if (PRINT_FIELD(WEIGHT)) fprintf(fp, "%16" PRIu64, sample->weight); diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c index 4fd48fd20055..8ce4996cad8d 100644 --- a/tools/perf/util/mem-events.c +++ b/tools/perf/util/mem-events.c @@ -604,8 +604,77 @@ int perf_mem__blk_scnprintf(char *out, size_t sz, cons= t struct mem_info *mem_inf return l; } =20 -int perf_script__meminfo_scnprintf(char *out, size_t sz, const struct mem_= info *mem_info) +static int perf_mem__region_scnprintf(char *out, size_t sz, const struct m= em_info *mem_info) { + size_t l =3D 0; + u64 mem =3D PERF_MEM_REGION_NA; + + sz -=3D 1; /* -1 for null termination */ + out[0] =3D '\0'; + + if (mem_info) + mem =3D mem_info__const_data_src(mem_info)->mem_region; + + switch (mem) { + case PERF_MEM_REGION_NA: + case PERF_MEM_REGION_RSVD: + l +=3D scnprintf(out + l, sz - l, "N/A"); + break; + case PERF_MEM_REGION_L_SHARE: + l +=3D scnprintf(out + l, sz - l, "Local-shared-cache"); + break; + case PERF_MEM_REGION_L_NON_SHARE: + l +=3D scnprintf(out + l, sz - l, "Local-non-shared-cache"); + break; + case PERF_MEM_REGION_O_IO: + l +=3D scnprintf(out + l, sz - l, "Other-IO"); + break; + case PERF_MEM_REGION_O_SHARE: + l +=3D scnprintf(out + l, sz - l, "Other-shared-cache"); + break; + case PERF_MEM_REGION_O_NON_SHARE: + l +=3D scnprintf(out + l, sz - l, "Other-non-shared-cache"); + break; + case PERF_MEM_REGION_MMIO: + l +=3D scnprintf(out + l, sz - l, "MMIO"); + break; + case PERF_MEM_REGION_MEM0: + l +=3D scnprintf(out + l, sz - l, "Mem-0"); + break; + case PERF_MEM_REGION_MEM1: + l +=3D scnprintf(out + l, sz - l, "Mem-1"); + break; + case PERF_MEM_REGION_MEM2: + l +=3D scnprintf(out + l, sz - l, "Mem-2"); + break; + case PERF_MEM_REGION_MEM3: + l +=3D scnprintf(out + l, sz - l, "Mem-3"); + break; + case PERF_MEM_REGION_MEM4: + l +=3D scnprintf(out + l, sz - l, "Mem-4"); + break; + case PERF_MEM_REGION_MEM5: + l +=3D scnprintf(out + l, sz - l, "Mem-5"); + break; + case PERF_MEM_REGION_MEM6: + l +=3D scnprintf(out + l, sz - l, "Mem-6"); + break; + case PERF_MEM_REGION_MEM7: + l +=3D scnprintf(out + l, sz - l, "Mem-7"); + break; + default: + l +=3D scnprintf(out + l, sz - l, "N/A"); + break; + } + + return l; +} + +int perf_script__meminfo_scnprintf(char *out, size_t sz, + const struct mem_info *mem_info, + struct perf_session *session) +{ + struct perf_env *env; int i =3D 0; =20 i +=3D scnprintf(out, sz, "|OP "); @@ -620,6 +689,21 @@ int perf_script__meminfo_scnprintf(char *out, size_t s= z, const struct mem_info * i +=3D perf_mem__lck_scnprintf(out + i, sz - i, mem_info); i +=3D scnprintf(out + i, sz - i, "|BLK "); i +=3D perf_mem__blk_scnprintf(out + i, sz - i, mem_info); + if (session) { + /* + * In case the feature bits are not available, as in + * pipe mode, fallback to checking for the existence of + * memory ranges + */ + env =3D perf_session__env(session); + if ((env && session->data->is_pipe && env->nr_memory_ranges) || + perf_header__has_feat(&session->header, + HEADER_MEMORY_RANGES)) { + i +=3D scnprintf(out + i, sz - i, "|Region "); + i +=3D perf_mem__region_scnprintf(out + i, sz - i, + mem_info); + } + } =20 return i; } diff --git a/tools/perf/util/mem-events.h b/tools/perf/util/mem-events.h index daa22748f9fe..4ebb8109fc3c 100644 --- a/tools/perf/util/mem-events.h +++ b/tools/perf/util/mem-events.h @@ -4,6 +4,7 @@ =20 #include #include +#include "session.h" =20 struct perf_mem_event { bool supported; @@ -47,7 +48,8 @@ int perf_mem__snp_scnprintf(char *out, size_t sz, const s= truct mem_info *mem_inf int perf_mem__lck_scnprintf(char *out, size_t sz, const struct mem_info *m= em_info); int perf_mem__blk_scnprintf(char *out, size_t sz, const struct mem_info *m= em_info); =20 -int perf_script__meminfo_scnprintf(char *bf, size_t size, const struct mem= _info *mem_info); +int perf_script__meminfo_scnprintf(char *bf, size_t size, const struct mem= _info *mem_info, + struct perf_session *session); =20 struct c2c_stats { u32 nr_entries; diff --git a/tools/perf/util/scripting-engines/trace-event-python.c b/tools= /perf/util/scripting-engines/trace-event-python.c index 8f832ae316ca..e359fe529586 100644 --- a/tools/perf/util/scripting-engines/trace-event-python.c +++ b/tools/perf/util/scripting-engines/trace-event-python.c @@ -694,8 +694,9 @@ static void set_sample_read_in_dict(PyObject *dict_samp= le, struct perf_sample *s static void set_sample_datasrc_in_dict(PyObject *dict, struct perf_sample *sample) { + struct perf_session *session =3D evsel__session(sample->evsel); struct mem_info *mi =3D mem_info__new(); - char decode[100]; + char decode[200]; =20 if (!mi) Py_FatalError("couldn't create mem-info"); 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d="scan'208";a="261915000" Received: from rodrigoa-mobl1.amr.corp.intel.com (HELO tfalcon-desk.intel.com) ([10.124.221.152]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Aug 2026 17:18:33 -0700 From: Thomas Falcon To: Namhyung Kim Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Dapeng Mi Subject: [PATCH v5 6/6] perf c2c: print memory region data with stdio output Date: Thu, 20 Aug 2026 19:18:19 -0500 Message-ID: <20260821001819.162277-7-thomas.falcon@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260821001819.162277-1-thomas.falcon@intel.com> References: <20260821001819.162277-1-thomas.falcon@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Print memory range data in perf-c2c subcommand. Only available in stdio mode currently. If memory ranges are not supported or present, print nothing. Example output of perf c2c report --stdio: =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Memory Ranges =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Range 0: [0x0000000000000000-0x00000000bfffffff] Node 0, local region id 0,= remote region id 255 Range 1: [0x0000000100000000-0x000000203fffffff] Node 0, local region id 0,= remote region id 255 Range 2: [0x0000008000000000-0x0000027fffffffff] Node -2, local region id 1= , remote region id 255 Range 3: [0x0000028000000000-0x0000047fffffffff] Node -2, local region id 1= , remote region id 255 Range 4: [0x0000048000000000-0x000004ffffffffff] Node -2, local region id 1= , remote region id 255 Assisted-by: Sashiko:gemini-3.1-pro-preview Reviewed-by: Ian Rogers Signed-off-by: Thomas Falcon --- v3: Included examples of memory range output in commit message --- tools/perf/builtin-c2c.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c index ce324fc59947..4cac63e843c9 100644 --- a/tools/perf/builtin-c2c.c +++ b/tools/perf/builtin-c2c.c @@ -2680,6 +2680,34 @@ static void print_c2c_info(FILE *out, struct perf_se= ssion *session) fprintf(out, " Cacheline data grouping : %s\n", c2c.cl_sort); } =20 + +static void print_memory_ranges_info(FILE *out, struct perf_session *sessi= on) +{ + struct perf_env *env =3D perf_session__env(session); + int nr_ranges =3D 0; + + if (!perf_header__has_feat(&session->header, HEADER_MEMORY_RANGES)) + return; + nr_ranges =3D env->nr_memory_ranges; + if (nr_ranges =3D=3D 0) { + pr_debug("No memory ranges found, skipping\n"); + return; + } + + fprintf(out, "\n"); + fprintf(out, "=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D\n"); + fprintf(out, " Memory Ranges \n"); + fprintf(out, "=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D\n"); + + for (int i =3D 0; i < nr_ranges; i++) { + struct memory_range *r =3D &env->memory_ranges[i]; + + fprintf(out, "Range %d: [0x%016" PRIx64 "-0x%016" PRIx64 "] Node %d, loc= al region id %u, remote region id %u\n", + i, r->base, r->base + r->length - 1, r->node, + r->local_region_id, r->remote_region_id); + } +} + static void perf_c2c__hists_fprintf(FILE *out, struct perf_session *sessio= n) { setup_pager(); @@ -2693,6 +2721,8 @@ static void perf_c2c__hists_fprintf(FILE *out, struct= perf_session *session) if (c2c.stats_only) return; =20 + print_memory_ranges_info(out, session); + fprintf(out, "\n"); fprintf(out, "=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D\n"); fprintf(out, " Shared Data Cache Line Table \n"); --=20 2.55.0