From nobody Mon Sep 28 12:33:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1E6F3793B4; Fri, 21 Aug 2026 15:45:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787327147; cv=none; b=T/Ak9UTo+j6lT+V6KpgobO6KmJ7yOMOZ5gCSVv5QgIVK+OABCR3gpEPrgDK+dFANARC2hvFA9PIWG/YxoGl+QEvRl+HXe2zXTlhlb9RBQuHq5A6taFJOAoProZRopPfneA26WnpcMBGikLw9506M5z9YSkos8OWNbAIkZfJfmyk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787327147; c=relaxed/simple; bh=+ixko2Bt0RcawsuOfq9EeeMloylw3ayN6yWX9GXtlRI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KfXEZ8yE8gBicX2Np+MWLaMbAWePOEdt6lVP0K4WTh+AeF+vg9GrzDkG3rQyA9R2OUKLoqAmtucn/wFZdpj5DxB5darJBPrTvh9v6PTGI7hthvoY4vJiQWGzaFVE6NZoAUvd0d4FtxXoi07N2oAQ9js/l5n9sjUFztFDOfPKkMU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dsg9dIcl; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dsg9dIcl" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8FF1BC2BCF4; Fri, 21 Aug 2026 15:45:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787327146; bh=+ixko2Bt0RcawsuOfq9EeeMloylw3ayN6yWX9GXtlRI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=dsg9dIclTvdZX2VEI3Zx4breRowsGScDS9Zr+W0bSyJK2HKzoVlH2yvzHeGlID3aQ JMzwlMT0VEvpIuqsiKLcMbZvcW5lN292PfcN25ltMRnff2naQboIvRo/YeoMnxBwZa zqGsRQDaTSg8rD+QEw+bYqO+aStcza2gqjGq1A4VN4KT6b7vaoud3dDG0pYWnjt0Vl JCF+8yiui9IggyZ/eUbNmIZ7lsipqLqmLodjjbynNwttNqdh21Q2LW0DTC7AxHBatA lXZ3NntI+K0bP1BadXUoivEYj6nAUXME3wsTMy7ZmflVNofvRmW5Eas3RUuX/iofzA Akp3rEwfn4B1A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6ED1AC5DF7D; Fri, 21 Aug 2026 15:45:46 +0000 (UTC) From: Sven Peter Date: Fri, 21 Aug 2026 17:44:54 +0200 Subject: [PATCH v2 1/3] dt-bindings: reset: Add Apple SoC CIO reset Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260821-b4-cio-reset-v2-1-2d045f80a424@kernel.org> References: <20260821-b4-cio-reset-v2-0-2d045f80a424@kernel.org> In-Reply-To: <20260821-b4-cio-reset-v2-0-2d045f80a424@kernel.org> To: Sven Peter , Janne Grunau , Neal Gompa , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: Joshua Peisach , asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Conor Dooley X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4541; i=sven@kernel.org; h=from:subject:message-id; bh=+ixko2Bt0RcawsuOfq9EeeMloylw3ayN6yWX9GXtlRI=; b=owGbwMvMwCXmIlirolUq95LxtFoSQ1ZH0bKdNpa/NnYFXzwkcf7KcrnH86OqN98KO9jP7P532 9PXkbd3d5SyMIhxMciKKbJs329v+uThG8Glmy69h5nDygQyhIGLUwAmwsfIyDDLZrNhekGTYeF1 DvPtq/3v+PMrpRqcE+Tqznsb1XJPM4OR4drV/qsXw3ma/a49PBD0+6kSz0uVqaYZE0pmXLqXzyy exgMA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 The CIO (USB4/Thunderbolt) blocks on Apple Silicon SoCs have a reset inside the power manager that has to be deasserted before their co-processor can be booted. On t8103 each port comes with a dedicated register page, represented as a standalone node. On t600x a single register shared by all ports of a die is located in the middle of the PMGR MMIO region instead, represented as a sub-node of the PMGR syscon. Reviewed-by: Conor Dooley Signed-off-by: Sven Peter Reviewed-by: Janne Grunau --- .../devicetree/bindings/arm/apple/apple,pmgr.yaml | 12 +++++ .../bindings/reset/apple,t8103-cio-reset.yaml | 61 ++++++++++++++++++= ++++ MAINTAINERS | 1 + 3 files changed, 74 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml b/= Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml index c67b67ba065a..49b4bec36461 100644 --- a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml +++ b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml @@ -59,6 +59,12 @@ patternProperties: type: object $ref: /schemas/power/apple,pmgr-pwrstate.yaml# =20 + "reset-controller@[0-9a-f]+$": + description: + Reset controller for the CIO (USB4/Thunderbolt) blocks + type: object + $ref: /schemas/reset/apple,t8103-cio-reset.yaml# + required: - compatible - reg @@ -103,6 +109,12 @@ examples: label =3D "uart0"; power-domains =3D <&ps_uart_p>; }; + + reset-controller@13034 { + compatible =3D "apple,t6000-cio-reset"; + reg =3D <0x13034 0x4>; + #reset-cells =3D <1>; + }; }; =20 power-management@23d280000 { diff --git a/Documentation/devicetree/bindings/reset/apple,t8103-cio-reset.= yaml b/Documentation/devicetree/bindings/reset/apple,t8103-cio-reset.yaml new file mode 100644 index 000000000000..6f602669d242 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/apple,t8103-cio-reset.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/apple,t8103-cio-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple SoC CIO (USB4/Thunderbolt) block reset controller + +maintainers: + - Sven Peter + +description: | + The CIO (Converged I/O) blocks on Apple Silicon SoCs have a reset + inside the power manager (PMGR) that has to be deasserted before + their co-processor can be booted. On t8103 each port comes with a + dedicated register page, represented as a standalone node. On t600x a + single register shared by all ports of a die with one request bit per + port is used instead. Since this register is located in the middle of + the PMGR MMIO region it is represented as a sub-node of the PMGR + syscon with reg used as an offset into it. + + In both cases the reset id is the CIO port index on the die. + +properties: + compatible: + oneOf: + - enum: + - apple,t8103-cio-reset + - apple,t6000-cio-reset + - items: + - const: apple,t8112-cio-reset + - const: apple,t8103-cio-reset + - items: + - const: apple,t6020-cio-reset + - const: apple,t6000-cio-reset + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#reset-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + reset-controller@23b784000 { + compatible =3D "apple,t8103-cio-reset"; + reg =3D <0x2 0x3b784000 0x0 0x8000>; + #reset-cells =3D <1>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 8014b9f8253e..e1ec54f4d80e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2606,6 +2606,7 @@ F: Documentation/devicetree/bindings/pinctrl/apple,pi= nctrl.yaml F: Documentation/devicetree/bindings/power/apple* F: Documentation/devicetree/bindings/power/reset/apple,smc-reboot.yaml F: Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml +F: Documentation/devicetree/bindings/reset/apple,t8103-cio-reset.yaml F: Documentation/devicetree/bindings/rtc/apple,smc-rtc.yaml F: Documentation/devicetree/bindings/spi/apple,spi.yaml F: Documentation/devicetree/bindings/spmi/apple,spmi.yaml --=20 2.55.0 From nobody Mon Sep 28 12:33:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1D5D377AB0; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fLfb3qRt" Received: by smtp.kernel.org (Postfix) with ESMTPS id 9F7F1C2BCB3; Fri, 21 Aug 2026 15:45:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787327146; bh=MGx0GYT9TUvqftU0PVYwjLEeXdmQzZyN+kKeemKuO5g=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=fLfb3qRtBhYIJT0foY+6S/g7gTfYbNMdlgGXQQp24WVbIZOO0Xw3FyvjDIaqfRKBr zDUOYUOJFhG97lKBfpsEPDQG8FSlizBKXAZj/qTqU8TVOVeBtc5T2cckWj0o3Trzg8 ABwkDWgdTilUfiFc/AaIIFbUXLXSnWnHr91BxL5qPSvHIOaqS25U+mo6JoX7DjrPHC aGdwFBIneKiMhAR6RXTmzbNpRWwjOSZiofzh0csYOqOXoSyknIxYH3Cdu1R0ySwqo0 /z8RKeu/hTSVRJxwxUh3L1lpCISQx9tgQumQnF43Emj8mQVKxu6Y4VaaykVCdC837/ jB3k2VHAQHhTw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 813E6C5DF97; Fri, 21 Aug 2026 15:45:46 +0000 (UTC) From: Sven Peter Date: Fri, 21 Aug 2026 17:44:55 +0200 Subject: [PATCH v2 2/3] reset: Add Apple SoC CIO reset driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260821-b4-cio-reset-v2-2-2d045f80a424@kernel.org> References: <20260821-b4-cio-reset-v2-0-2d045f80a424@kernel.org> In-Reply-To: <20260821-b4-cio-reset-v2-0-2d045f80a424@kernel.org> To: Sven Peter , Janne Grunau , Neal Gompa , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: Joshua Peisach , asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8719; i=sven@kernel.org; h=from:subject:message-id; bh=MGx0GYT9TUvqftU0PVYwjLEeXdmQzZyN+kKeemKuO5g=; b=owGbwMvMwCXmIlirolUq95LxtFoSQ1ZH0XKd85te7FARn3G18uD0xf4NDE0n7LSPKvs8Clzv9 n8ZR/rSjlIWBjEuBlkxRZbt++1Nnzx8I7h006X3MHNYmUCGMHBxCsBElpkzMmywU3ywLOpNLaPk h4ms3UoF+3VfNGidinQWmcf2r3/OBHFGhk+BdRvnPo+c8aLvx5QfMZwO62/+MRHU1Pj9/+0d89a JJzkA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 Add a driver for the reset of the CIO (USB4/Thunderbolt) blocks on Apple Silicon SoCs which has to be deasserted before their co-processor can be booted. On t8103 each port comes with a dedicated register page while t600x uses a single register with one request bit per port shared by all ports of a die inside the PMGR MMIO region. Signed-off-by: Sven Peter Reviewed-by: Janne Grunau --- MAINTAINERS | 1 + drivers/reset/Kconfig | 10 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-apple-cio.c | 200 ++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 212 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e1ec54f4d80e..a1f6fdb9436c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2636,6 +2636,7 @@ F: drivers/pinctrl/pinctrl-apple-gpio.c F: drivers/power/reset/macsmc-reboot.c F: drivers/power/supply/macsmc-power.c F: drivers/pwm/pwm-apple.c +F: drivers/reset/reset-apple-cio.c F: drivers/rtc/rtc-macsmc.c F: drivers/soc/apple/* F: drivers/spi/spi-apple.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index d009eb0849a3..1e83cb5c68ce 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -22,6 +22,16 @@ config RESET_A10SR This option enables support for the external reset functions for peripheral PHYs on the Altera Arria10 System Resource Chip. =20 +config RESET_APPLE_CIO + tristate "Apple SoC CIO block reset driver" + depends on ARCH_APPLE || COMPILE_TEST + select MFD_SYSCON + help + This enables the reset driver for the CIO (USB4/Thunderbolt) blocks + found on Apple Silicon SoCs. It is required to start the blocks + before the USB4/Thunderbolt host routers inside them can be brought + up by the thunderbolt driver. + config RESET_ASPEED tristate "ASPEED Reset Driver" depends on ARCH_ASPEED || COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 3e52569bd276..6554649bc139 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -7,6 +7,7 @@ obj-y +=3D starfive/ obj-y +=3D sti/ obj-y +=3D tegra/ obj-$(CONFIG_RESET_A10SR) +=3D reset-a10sr.o +obj-$(CONFIG_RESET_APPLE_CIO) +=3D reset-apple-cio.o obj-$(CONFIG_RESET_ASPEED) +=3D reset-aspeed.o obj-$(CONFIG_RESET_ATH79) +=3D reset-ath79.o obj-$(CONFIG_RESET_AXS10X) +=3D reset-axs10x.o diff --git a/drivers/reset/reset-apple-cio.c b/drivers/reset/reset-apple-ci= o.c new file mode 100644 index 000000000000..5727c608f82f --- /dev/null +++ b/drivers/reset/reset-apple-cio.c @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Apple SoC CIO (USB4/Thunderbolt) block reset driver + * + * Copyright The Asahi Linux Contributors + * + * The CIO blocks have a reset inside the power manager (PMGR) that + * has to be deasserted before their co-processor can be booted. On + * t8103 each port comes with a dedicated register page while t600x + * uses a single register shared by all ports of a die inside the PMGR + * MMIO region. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define APPLE_CIO_RESET_POLL_US 100 +#define APPLE_CIO_RESET_TIMEOUT_US 100000 + +#define T8103_CIO_CTRL_STRIDE 0x4000 +#define T8103_CIO_CTRL_INIT_REQ BIT(0) +#define T8103_CIO_CTRL_INIT_DONE BIT(2) + +#define T6000_CIO_CTRL_INIT_REQ(port) BIT(port) +#define T6000_CIO_CTRL_INIT_BUSY(port) BIT(16 + (port)) + +struct apple_cio_reset; + +struct apple_cio_reset_variant { + unsigned int nr_resets; + bool pmgr_child; + int (*deassert)(struct apple_cio_reset *priv, unsigned long id); +}; + +struct apple_cio_reset { + struct reset_controller_dev rcdev; + const struct apple_cio_reset_variant *variant; + struct regmap *regmap; + u32 offset; + struct mutex lock; /* serializes access to the shared t600x register */ +}; + +static int t8103_cio_deassert(struct apple_cio_reset *priv, unsigned long = id) +{ + u32 offset =3D priv->offset + id * T8103_CIO_CTRL_STRIDE; + u32 val; + int ret; + + /* + * After writing BIT(0) the reset is deasserted and the CIO block comes u= p. + * Once the sequence is done BIT(0) is cleared automatically and then BIT= (2) + * is set. There's no way to assert the reset again other than cutting th= e power + * to the entire CIO block. Writing the bit again has no effect. + */ + ret =3D regmap_write(priv->regmap, offset, T8103_CIO_CTRL_INIT_REQ); + if (ret) + return ret; + + return regmap_read_poll_timeout(priv->regmap, offset, val, + val =3D=3D T8103_CIO_CTRL_INIT_DONE, + APPLE_CIO_RESET_POLL_US, + APPLE_CIO_RESET_TIMEOUT_US); +} + +static int t6000_cio_deassert(struct apple_cio_reset *priv, unsigned long = id) +{ + u32 val; + int ret; + + /* + * Note that even the mutex is likely paranoid and not actually required + * here: The way this controller works is that setting bit N immediately + * results in bit 16+n being set. Once the reset is fully released both + * bits are cleared again but macOS specifically waits for the upper one + * to clear before continuing. + * Manually clearing bits is ignored and has no effect, the only way to + * put the block into reset again is shut down its power domains. + * Thus, there's no need to either RMW here or wait before polling. + */ + guard(mutex)(&priv->lock); + + ret =3D regmap_write(priv->regmap, priv->offset, T6000_CIO_CTRL_INIT_REQ(= id)); + if (ret) + return ret; + + return regmap_read_poll_timeout(priv->regmap, priv->offset, val, + !(val & T6000_CIO_CTRL_INIT_BUSY(id)), + APPLE_CIO_RESET_POLL_US, + APPLE_CIO_RESET_TIMEOUT_US); +} + +static const struct apple_cio_reset_variant apple_t8103_cio_reset =3D { + .nr_resets =3D 2, + .deassert =3D t8103_cio_deassert, +}; + +static const struct apple_cio_reset_variant apple_t6000_cio_reset =3D { + .nr_resets =3D 4, + .pmgr_child =3D true, + .deassert =3D t6000_cio_deassert, +}; + +static int apple_cio_reset_deassert(struct reset_controller_dev *rcdev, un= signed long id) +{ + struct apple_cio_reset *priv =3D + container_of(rcdev, struct apple_cio_reset, rcdev); + + return priv->variant->deassert(priv, id); +} + +static const struct reset_control_ops apple_cio_reset_ops =3D { + .deassert =3D apple_cio_reset_deassert, +}; + +static const struct regmap_config apple_cio_reset_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, +}; + +static int apple_cio_reset_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct apple_cio_reset *priv; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->variant =3D of_device_get_match_data(dev); + if (!priv->variant) + return -ENODEV; + + ret =3D devm_mutex_init(dev, &priv->lock); + if (ret) + return ret; + + if (priv->variant->pmgr_child) { + priv->regmap =3D syscon_node_to_regmap(dev->of_node->parent); + if (IS_ERR(priv->regmap)) + return dev_err_probe(dev, PTR_ERR(priv->regmap), + "Failed to get parent regmap\n"); + + ret =3D of_property_read_u32(dev->of_node, "reg", &priv->offset); + if (ret) + return dev_err_probe(dev, ret, "Failed to read reg offset\n"); + } else { + void __iomem *base; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + priv->regmap =3D devm_regmap_init_mmio(dev, base, + &apple_cio_reset_regmap_config); + if (IS_ERR(priv->regmap)) + return dev_err_probe(dev, PTR_ERR(priv->regmap), + "Failed to init MMIO regmap\n"); + } + + priv->rcdev.owner =3D THIS_MODULE; + priv->rcdev.ops =3D &apple_cio_reset_ops; + priv->rcdev.of_node =3D dev->of_node; + priv->rcdev.nr_resets =3D priv->variant->nr_resets; + + return devm_reset_controller_register(dev, &priv->rcdev); +} + +static const struct of_device_id apple_cio_reset_match[] =3D { + { + .compatible =3D "apple,t8103-cio-reset", + .data =3D &apple_t8103_cio_reset, + }, + { + .compatible =3D "apple,t6000-cio-reset", + .data =3D &apple_t6000_cio_reset, + }, + {}, +}; +MODULE_DEVICE_TABLE(of, apple_cio_reset_match); + +static struct platform_driver apple_cio_reset_driver =3D { + .driver =3D { + .name =3D "apple-cio-reset", + .of_match_table =3D apple_cio_reset_match, + }, + .probe =3D apple_cio_reset_probe, +}; +module_platform_driver(apple_cio_reset_driver); + +MODULE_AUTHOR("Sven Peter "); +MODULE_DESCRIPTION("Apple SoC CIO block reset driver"); +MODULE_LICENSE("Dual MIT/GPL"); --=20 2.55.0 From nobody Mon Sep 28 12:33:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2950379C47; Fri, 21 Aug 2026 15:45:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787327147; cv=none; b=OZdCRJ7GfTvwz5K8HKiUbmHx7pHVgeG86tILrXW7OOVqmjpbK60CA91ncB/lBgKJH7bRmTKSGmYUVanielxyYTyHAPNbx/Qt9KbPADtoYz5zvgcOz8TLbHFbUGUqzbrOaJ/REGHMFYAR6Y7CnEGVfAryF2y5svqrxbkMcFpbDTw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787327147; c=relaxed/simple; bh=10ZqKWSpLGh0HzriAEqbDWXJva1apqllME3fu+dUFeM=; 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Fri, 21 Aug 2026 15:45:46 +0000 (UTC) From: Sven Peter Date: Fri, 21 Aug 2026 17:44:56 +0200 Subject: [PATCH v2 3/3] arm64: dts: apple: Add CIO reset controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260821-b4-cio-reset-v2-3-2d045f80a424@kernel.org> References: <20260821-b4-cio-reset-v2-0-2d045f80a424@kernel.org> In-Reply-To: <20260821-b4-cio-reset-v2-0-2d045f80a424@kernel.org> To: Sven Peter , Janne Grunau , Neal Gompa , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: Joshua Peisach , asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3435; i=sven@kernel.org; h=from:subject:message-id; bh=10ZqKWSpLGh0HzriAEqbDWXJva1apqllME3fu+dUFeM=; b=owGbwMvMwCXmIlirolUq95LxtFoSQ1ZH0YqvZ5x3yM7nvbH9yAOjhxUmXx3nrCkSyPyzYo3nQ Y4UBXb1jlIWBjEuBlkxRZbt++1Nnzx8I7h006X3MHNYmUCGMHBxCsBEChcw/HfIC13CpbHhUOoH l4nunX8anJJTBS3C13ts7Sk5uFHzbBjDXwmeyyJyv7SMv9hWz4stP3CrOYGnYnGV86F/NxZ2fzl yiwEA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 Add the reset controllers used to start the CIO (USB4/Thunderbolt) blocks on t8103 and t600x. On t8103 each port comes with a dedicated register page represented as a standalone node. On t600x a single register shared by all ports of a die is located in the middle of the PMGR MMIO region and represented as a sub-node of its syscon. Signed-off-by: Sven Peter Reviewed-by: Janne Grunau --- arch/arm64/boot/dts/apple/t600x-dieX.dtsi | 8 +++++++- arch/arm64/boot/dts/apple/t602x-dieX.dtsi | 8 +++++++- arch/arm64/boot/dts/apple/t8103.dtsi | 6 ++++++ arch/arm64/boot/dts/apple/t8112.dtsi | 6 ++++++ 4 files changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/apple/t600x-dieX.dtsi b/arch/arm64/boot/dt= s/apple/t600x-dieX.dtsi index 9676d5127039..5e163d756a7f 100644 --- a/arch/arm64/boot/dts/apple/t600x-dieX.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-dieX.dtsi @@ -28,7 +28,13 @@ DIE_NODE(pmgr): power-management@28e080000 { compatible =3D "apple,t6000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; #address-cells =3D <1>; #size-cells =3D <1>; - reg =3D <0x2 0x8e080000 0 0x4000>; + reg =3D <0x2 0x8e080000 0 0x1c000>; + + DIE_NODE(cio_reset): reset-controller@1a034 { + compatible =3D "apple,t6000-cio-reset"; + reg =3D <0x1a034 0x4>; + #reset-cells =3D <1>; + }; }; =20 DIE_NODE(pmgr_east): power-management@28e580000 { diff --git a/arch/arm64/boot/dts/apple/t602x-dieX.dtsi b/arch/arm64/boot/dt= s/apple/t602x-dieX.dtsi index ae3d535c5acb..fd4d572a04e7 100644 --- a/arch/arm64/boot/dts/apple/t602x-dieX.dtsi +++ b/arch/arm64/boot/dts/apple/t602x-dieX.dtsi @@ -27,7 +27,13 @@ DIE_NODE(pmgr): power-management@28e080000 { compatible =3D "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple= -mfd"; #address-cells =3D <1>; #size-cells =3D <1>; - reg =3D <0x2 0x8e080000 0 0x8000>; + reg =3D <0x2 0x8e080000 0 0xc000>; + + DIE_NODE(cio_reset): reset-controller@a02c { + compatible =3D "apple,t6020-cio-reset", "apple,t6000-cio-reset"; + reg =3D <0xa02c 0x4>; + #reset-cells =3D <1>; + }; }; =20 DIE_NODE(pmgr_south): power-management@28e680000 { diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/app= le/t8103.dtsi index da774096b667..83f6f1003424 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -730,6 +730,12 @@ pmgr: power-management@23b700000 { reg =3D <0x2 0x3b700000 0 0x14000>; }; =20 + cio_reset: reset-controller@23b784000 { + compatible =3D "apple,t8103-cio-reset"; + reg =3D <0x2 0x3b784000 0x0 0x8000>; + #reset-cells =3D <1>; + }; + pinctrl_ap: pinctrl@23c100000 { compatible =3D "apple,t8103-pinctrl", "apple,pinctrl"; reg =3D <0x2 0x3c100000 0x0 0x100000>; diff --git a/arch/arm64/boot/dts/apple/t8112.dtsi b/arch/arm64/boot/dts/app= le/t8112.dtsi index 85c47422d4e8..963030373a23 100644 --- a/arch/arm64/boot/dts/apple/t8112.dtsi +++ b/arch/arm64/boot/dts/apple/t8112.dtsi @@ -737,6 +737,12 @@ pmgr: power-management@23b700000 { /* child nodes are added in t8103-pmgr.dtsi */ }; =20 + cio_reset: reset-controller@23b790000 { + compatible =3D "apple,t8112-cio-reset", "apple,t8103-cio-reset"; + reg =3D <0x2 0x3b790000 0x0 0x8000>; + #reset-cells =3D <1>; + }; + pinctrl_ap: pinctrl@23c100000 { compatible =3D "apple,t8112-pinctrl", "apple,pinctrl"; reg =3D <0x2 0x3c100000 0x0 0x100000>; --=20 2.55.0