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charset="utf-8" struct iommufd_sw_msi_maps uses a fixed 64-bit bitmap, limiting each group and hardware page table to 64 software MSI mappings. RISC-V interrupt remapping needs a mapping for every possible CPU, so this limit is insufficient. Make the bitmap grow on demand and treat IDs beyond its current size as absent. Cap it at 16K entries to bound allocation size while leaving ample room for expected software MSI users. Signed-off-by: Andrew Jones --- drivers/iommu/iommufd/device.c | 3 +- drivers/iommu/iommufd/driver.c | 38 +++++++++++++++-------- drivers/iommu/iommufd/hw_pagetable.c | 1 + drivers/iommu/iommufd/iommufd_private.h | 41 +++++++++++++++++++++++-- 4 files changed, 67 insertions(+), 16 deletions(-) diff --git a/drivers/iommu/iommufd/device.c b/drivers/iommu/iommufd/device.c index d488c23fd353..868f1e591208 100644 --- a/drivers/iommu/iommufd/device.c +++ b/drivers/iommu/iommufd/device.c @@ -34,6 +34,7 @@ static void iommufd_group_release(struct kref *kref) NULL, GFP_KERNEL); iommu_group_put(igroup->group); mutex_destroy(&igroup->lock); + kfree(igroup->required_sw_msi.bitmap); kfree(igroup); } =20 @@ -384,7 +385,7 @@ static int iommufd_group_setup_msi(struct iommufd_group= *igroup, int rc; =20 if (cur->sw_msi_start !=3D igroup->sw_msi_start || - !test_bit(cur->id, igroup->required_sw_msi.bitmap)) + !iommufd_sw_msi_maps_test_bit(&igroup->required_sw_msi, cur->id)) continue; =20 rc =3D iommufd_sw_msi_install(ictx, hwpt_paging, cur); diff --git a/drivers/iommu/iommufd/driver.c b/drivers/iommu/iommufd/driver.c index 3b8067976eac..9b9316ae4266 100644 --- a/drivers/iommu/iommufd/driver.c +++ b/drivers/iommu/iommufd/driver.c @@ -196,13 +196,15 @@ iommufd_sw_msi_get_map(struct iommufd_ctx *ictx, phys= _addr_t msi_addr, list_for_each_entry(cur, &ictx->sw_msi_list, sw_msi_item) { if (cur->sw_msi_start !=3D sw_msi_start) continue; + if (cur->pgoff =3D=3D UINT_MAX) + return ERR_PTR(-EOVERFLOW); max_pgoff =3D max(max_pgoff, cur->pgoff + 1); if (cur->msi_addr =3D=3D msi_addr) return cur; } =20 - if (ictx->sw_msi_id >=3D - BITS_PER_BYTE * sizeof_field(struct iommufd_sw_msi_maps, bitmap)) + if (ictx->sw_msi_id > IOMMUFD_SW_MSI_MAX_ID || + max_pgoff > (ULONG_MAX - sw_msi_start) / PAGE_SIZE) return ERR_PTR(-EOVERFLOW); =20 cur =3D kzalloc_obj(*cur); @@ -222,21 +224,26 @@ int iommufd_sw_msi_install(struct iommufd_ctx *ictx, struct iommufd_sw_msi_map *msi_map) { unsigned long iova; + int rc; =20 lockdep_assert_held(&ictx->sw_msi_lock); =20 + if (iommufd_sw_msi_maps_test_bit(&hwpt_paging->present_sw_msi, + msi_map->id)) + return 0; + iova =3D msi_map->sw_msi_start + msi_map->pgoff * PAGE_SIZE; - if (!test_bit(msi_map->id, hwpt_paging->present_sw_msi.bitmap)) { - int rc; - - rc =3D iommu_map(hwpt_paging->common.domain, iova, - msi_map->msi_addr, PAGE_SIZE, - IOMMU_WRITE | IOMMU_READ | IOMMU_MMIO, - GFP_KERNEL_ACCOUNT); - if (rc) - return rc; - __set_bit(msi_map->id, hwpt_paging->present_sw_msi.bitmap); - } + rc =3D iommufd_sw_msi_maps_ensure(&hwpt_paging->present_sw_msi, msi_map->= id); + if (rc) + return rc; + + rc =3D iommu_map(hwpt_paging->common.domain, iova, + msi_map->msi_addr, PAGE_SIZE, + IOMMU_WRITE | IOMMU_READ | IOMMU_MMIO, + GFP_KERNEL_ACCOUNT); + if (rc) + return rc; + __set_bit(msi_map->id, hwpt_paging->present_sw_msi.bitmap); return 0; } EXPORT_SYMBOL_NS_GPL(iommufd_sw_msi_install, "IOMMUFD_INTERNAL"); @@ -290,6 +297,11 @@ int iommufd_sw_msi(struct iommu_domain *domain, struct= msi_desc *desc, if (IS_ERR(msi_map)) return PTR_ERR(msi_map); =20 + rc =3D iommufd_sw_msi_maps_ensure(&handle->idev->igroup->required_sw_msi, + msi_map->id); + if (rc) + return rc; + rc =3D iommufd_sw_msi_install(ictx, hwpt_paging, msi_map); if (rc) return rc; diff --git a/drivers/iommu/iommufd/hw_pagetable.c b/drivers/iommu/iommufd/h= w_pagetable.c index 623cc608ca0c..54873de43eb0 100644 --- a/drivers/iommu/iommufd/hw_pagetable.c +++ b/drivers/iommu/iommufd/hw_pagetable.c @@ -32,6 +32,7 @@ void iommufd_hwpt_paging_destroy(struct iommufd_object *o= bj) } =20 __iommufd_hwpt_destroy(&hwpt_paging->common); + kfree(hwpt_paging->present_sw_msi.bitmap); refcount_dec(&hwpt_paging->ioas->obj.users); } =20 diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommuf= d/iommufd_private.h index 43fbc5bed8de..9ca5f9f92cdf 100644 --- a/drivers/iommu/iommufd/iommufd_private.h +++ b/drivers/iommu/iommufd/iommufd_private.h @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -29,11 +30,47 @@ struct iommufd_sw_msi_map { unsigned int id; }; =20 -/* Bitmap of struct iommufd_sw_msi_map::id */ +/* Bitmap of struct iommufd_sw_msi_map::id; starts empty, grows on demand.= */ struct iommufd_sw_msi_maps { - DECLARE_BITMAP(bitmap, 64); + unsigned long *bitmap; + unsigned int nbits; }; =20 +/* Large enough for foreseeable SW MSI users while bounding bitmap growth.= */ +#define IOMMUFD_SW_MSI_MAX_ID (16U * 1024 - 1) + +/* Grow bitmap to accommodate id. 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charset="utf-8" Add a descriptor-free counterpart to iommufd_sw_msi(). The existing function is tied to a struct msi_desc and stores the result in the descriptor. This variant returns the IOVA directly so callers can pre-map MSI targets before any descriptor has been allocated. Signed-off-by: Andrew Jones --- drivers/iommu/iommu-priv.h | 11 +++++++ drivers/iommu/iommufd/driver.c | 60 +++++++++++++++++++++++++--------- 2 files changed, 56 insertions(+), 15 deletions(-) diff --git a/drivers/iommu/iommu-priv.h b/drivers/iommu/iommu-priv.h index aaffad5854fc..f60373cd2f70 100644 --- a/drivers/iommu/iommu-priv.h +++ b/drivers/iommu/iommu-priv.h @@ -55,12 +55,23 @@ int iommu_replace_group_handle(struct iommu_group *grou= p, #if IS_ENABLED(CONFIG_IOMMUFD_DRIVER_CORE) && IS_ENABLED(CONFIG_IRQ_MSI_IO= MMU) int iommufd_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, phys_addr_t msi_addr); +int iommufd_sw_map_msi(struct iommu_domain *domain, struct device *dev, + phys_addr_t msi_addr, size_t required_size, + dma_addr_t *msi_iova, unsigned int *msi_shift); #else /* !CONFIG_IOMMUFD_DRIVER_CORE || !CONFIG_IRQ_MSI_IOMMU */ static inline int iommufd_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, phys_addr_t msi_addr) { return -EOPNOTSUPP; } + +static inline int iommufd_sw_map_msi(struct iommu_domain *domain, + struct device *dev, phys_addr_t msi_addr, + size_t required_size, dma_addr_t *msi_iova, + unsigned int *msi_shift) +{ + return -EOPNOTSUPP; +} #endif /* CONFIG_IOMMUFD_DRIVER_CORE && CONFIG_IRQ_MSI_IOMMU */ =20 int iommu_replace_device_pasid(struct iommu_domain *domain, diff --git a/drivers/iommu/iommufd/driver.c b/drivers/iommu/iommufd/driver.c index 9b9316ae4266..69b3dbcbee3b 100644 --- a/drivers/iommu/iommufd/driver.c +++ b/drivers/iommu/iommufd/driver.c @@ -249,15 +249,23 @@ int iommufd_sw_msi_install(struct iommufd_ctx *ictx, EXPORT_SYMBOL_NS_GPL(iommufd_sw_msi_install, "IOMMUFD_INTERNAL"); =20 /* - * Called by the irq code if the platform translates the MSI address throu= gh the - * IOMMU. msi_addr is the physical address of the MSI page. iommufd will - * allocate a fd global iova for the physical page that is the same on all - * domains and devices. + * Descriptor-free counterpart to iommufd_sw_msi(). Maps an MSI physical p= age + * into the domain and returns the IOVA. Used for pre-mapping MSI targets = before + * any MSI descriptor has been set (e.g. IMSIC doorbell pages). The IOVA is + * global to the iommufd file descriptor: every domain and device using the + * same MSI parameters gets the same IOVA. + * + * msi_addr is the exact byte offset of the MSI doorbell; the caller must = have + * verified it is contained within an MMIO region safe to map at PAGE_SIZE= . If + * required_size is non-zero it must equal PAGE_SIZE. @msi_iova and @msi_s= hift + * must be non-NULL. + * + * The caller must hold @dev's iommu group mutex. */ -int iommufd_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, - phys_addr_t msi_addr) +int iommufd_sw_map_msi(struct iommu_domain *domain, struct device *dev, + phys_addr_t msi_addr, size_t required_size, + dma_addr_t *msi_iova, unsigned int *msi_shift) { - struct device *dev =3D msi_desc_to_dev(desc); struct iommufd_hwpt_paging *hwpt_paging; struct iommu_attach_handle *raw_handle; struct iommufd_attach_handle *handle; @@ -266,6 +274,12 @@ int iommufd_sw_msi(struct iommu_domain *domain, struct= msi_desc *desc, unsigned long iova; int rc; =20 + *msi_iova =3D 0; + *msi_shift =3D 0; + + if (required_size && required_size !=3D PAGE_SIZE) + return -EOPNOTSUPP; + /* * It is safe to call iommu_attach_handle_get() here because the iommu * core code invokes this under the group mutex which also prevents any @@ -286,13 +300,7 @@ int iommufd_sw_msi(struct iommu_domain *domain, struct= msi_desc *desc, =20 ictx =3D handle->idev->ictx; guard(mutex)(&ictx->sw_msi_lock); - /* - * The input msi_addr is the exact byte offset of the MSI doorbell, we - * assume the caller has checked that it is contained with a MMIO region - * that is secure to map at PAGE_SIZE. - */ - msi_map =3D iommufd_sw_msi_get_map(handle->idev->ictx, - msi_addr & PAGE_MASK, + msi_map =3D iommufd_sw_msi_get_map(ictx, msi_addr & PAGE_MASK, handle->idev->igroup->sw_msi_start); if (IS_ERR(msi_map)) return PTR_ERR(msi_map); @@ -308,7 +316,29 @@ int iommufd_sw_msi(struct iommu_domain *domain, struct= msi_desc *desc, __set_bit(msi_map->id, handle->idev->igroup->required_sw_msi.bitmap); =20 iova =3D msi_map->sw_msi_start + msi_map->pgoff * PAGE_SIZE; - msi_desc_set_iommu_msi_iova(desc, iova, PAGE_SHIFT); + *msi_iova =3D iova; + *msi_shift =3D PAGE_SHIFT; + return 0; +} +EXPORT_SYMBOL_NS_GPL(iommufd_sw_map_msi, "IOMMUFD"); + +/* + * Called by the irq layer when the platform translates MSI addresses thro= ugh + * the IOMMU. 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charset="utf-8" Add a descriptor-free counterpart to iommu_dma_sw_msi(). The existing function is tied to a struct msi_desc and stores the result in the descriptor. This variant returns the IOVA directly so callers can pre-map MSI targets before any descriptor has been allocated. Callers may pass a required mapping size so MSI doorbells that must not share a larger IOMMU leaf, such as RISC-V IMSIC files, can fail before a mapping is installed. Signed-off-by: Andrew Jones --- drivers/iommu/dma-iommu.c | 48 ++++++++++++++++++++++++++++++++------- drivers/iommu/dma-iommu.h | 12 ++++++++++ 2 files changed, 52 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 9a07eb39336e..3ce9f4878d92 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -2247,24 +2247,56 @@ static struct iommu_dma_msi_page *iommu_dma_get_msi= _page(struct device *dev, return NULL; } =20 -int iommu_dma_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, - phys_addr_t msi_addr) +/* + * Descriptor-free counterpart to iommu_dma_sw_msi(). Maps an MSI physical + * page into the domain and returns the IOVA and mapping granule. Used for + * pre-mapping MSI targets before any MSI descriptor has been set. + * + * The caller must pass a device attached to @domain and hold @dev's IOMMU + * group mutex. If @required_size is non-zero then it must exactly match t= he + * domain's MSI mapping granule. @msi_iova and @msi_shift must be non-NULL. + */ +int iommu_dma_sw_map_msi(struct iommu_domain *domain, + struct device *dev, phys_addr_t msi_addr, + size_t required_size, dma_addr_t *msi_iova, + unsigned int *msi_shift) { - struct device *dev =3D msi_desc_to_dev(desc); const struct iommu_dma_msi_page *msi_page; + size_t size; =20 - if (!has_msi_cookie(domain)) { - msi_desc_set_iommu_msi_iova(desc, 0, 0); + *msi_iova =3D 0; + *msi_shift =3D 0; + + if (!has_msi_cookie(domain)) return 0; - } + + size =3D cookie_msi_granule(domain); + if (required_size && size !=3D required_size) + return -EOPNOTSUPP; =20 iommu_group_mutex_assert(dev); msi_page =3D iommu_dma_get_msi_page(dev, msi_addr, domain); if (!msi_page) return -ENOMEM; =20 - msi_desc_set_iommu_msi_iova(desc, msi_page->iova, - ilog2(cookie_msi_granule(domain))); + *msi_iova =3D msi_page->iova; + *msi_shift =3D ilog2(size); + return 0; +} + +int iommu_dma_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, + phys_addr_t msi_addr) +{ + struct device *dev =3D msi_desc_to_dev(desc); + dma_addr_t msi_iova; + unsigned int msi_shift; + int ret; + + ret =3D iommu_dma_sw_map_msi(domain, dev, msi_addr, 0, &msi_iova, &msi_sh= ift); + if (ret) + return ret; + + msi_desc_set_iommu_msi_iova(desc, msi_iova, msi_shift); return 0; } =20 diff --git a/drivers/iommu/dma-iommu.h b/drivers/iommu/dma-iommu.h index 040d00252563..3e1adeafdcac 100644 --- a/drivers/iommu/dma-iommu.h +++ b/drivers/iommu/dma-iommu.h @@ -19,6 +19,10 @@ int iommu_dma_init_fq(struct iommu_domain *domain); =20 void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list= ); =20 +int iommu_dma_sw_map_msi(struct iommu_domain *domain, + struct device *dev, phys_addr_t msi_addr, + size_t required_size, dma_addr_t *msi_iova, + unsigned int *msi_shift); int iommu_dma_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, phys_addr_t msi_addr); =20 @@ -53,6 +57,14 @@ static inline void iommu_dma_get_resv_regions(struct dev= ice *dev, struct list_he { } =20 +static inline int iommu_dma_sw_map_msi(struct iommu_domain *domain, + struct device *dev, phys_addr_t msi_addr, + size_t required_size, dma_addr_t *msi_iova, + unsigned int *msi_shift) +{ + return -ENODEV; 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charset="utf-8" Interrupt-remapping drivers may need to map MSI targets before any MSI descriptor exists and retain their own PA-to-IOVA lookup table. Add iommu_dma_map_msi() to return the IOVA and mapping granule for both DMA-IOMMU and iommufd domains. Allow callers to require an exact mapping size. This prevents doorbells such as RISC-V IMSIC files from sharing a larger IOMMU leaf. Building a table requires the domain to remain stable across every mapping. The IOMMU group mutex provides that serialization, but its structure is private to the core. Expose lock helpers and a scoped guard so external callers can hold it for the complete operation. Signed-off-by: Andrew Jones --- drivers/iommu/dma-iommu.c | 22 +------ drivers/iommu/dma-iommu.h | 8 --- drivers/iommu/iommu-priv.h | 8 --- drivers/iommu/iommu.c | 104 ++++++++++++++++++++++++++++----- drivers/iommu/iommufd/driver.c | 31 ++-------- include/linux/iommu.h | 31 ++++++++++ 6 files changed, 127 insertions(+), 77 deletions(-) diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 3ce9f4878d92..39ee5f0b1da9 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -2248,9 +2248,9 @@ static struct iommu_dma_msi_page *iommu_dma_get_msi_p= age(struct device *dev, } =20 /* - * Descriptor-free counterpart to iommu_dma_sw_msi(). Maps an MSI physical - * page into the domain and returns the IOVA and mapping granule. Used for - * pre-mapping MSI targets before any MSI descriptor has been set. + * Maps an MSI physical page into the domain and returns the IOVA and + * mapping granule. Used for pre-mapping MSI targets before any MSI + * descriptor has been set. * * The caller must pass a device attached to @domain and hold @dev's IOMMU * group mutex. If @required_size is non-zero then it must exactly match t= he @@ -2284,22 +2284,6 @@ int iommu_dma_sw_map_msi(struct iommu_domain *domain, return 0; } =20 -int iommu_dma_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, - phys_addr_t msi_addr) -{ - struct device *dev =3D msi_desc_to_dev(desc); - dma_addr_t msi_iova; - unsigned int msi_shift; - int ret; - - ret =3D iommu_dma_sw_map_msi(domain, dev, msi_addr, 0, &msi_iova, &msi_sh= ift); - if (ret) - return ret; - - msi_desc_set_iommu_msi_iova(desc, msi_iova, msi_shift); - return 0; -} - static int iommu_dma_init(void) { if (is_kdump_kernel()) diff --git a/drivers/iommu/dma-iommu.h b/drivers/iommu/dma-iommu.h index 3e1adeafdcac..7d707157aebb 100644 --- a/drivers/iommu/dma-iommu.h +++ b/drivers/iommu/dma-iommu.h @@ -23,8 +23,6 @@ int iommu_dma_sw_map_msi(struct iommu_domain *domain, struct device *dev, phys_addr_t msi_addr, size_t required_size, dma_addr_t *msi_iova, unsigned int *msi_shift); -int iommu_dma_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, - phys_addr_t msi_addr); =20 extern bool iommu_dma_forcedac; =20 @@ -65,11 +63,5 @@ static inline int iommu_dma_sw_map_msi(struct iommu_doma= in *domain, return -ENODEV; } =20 -static inline int iommu_dma_sw_msi(struct iommu_domain *domain, - struct msi_desc *desc, phys_addr_t msi_addr) -{ - return -ENODEV; -} - #endif /* CONFIG_IOMMU_DMA */ #endif /* __DMA_IOMMU_H */ diff --git a/drivers/iommu/iommu-priv.h b/drivers/iommu/iommu-priv.h index f60373cd2f70..109aca07470b 100644 --- a/drivers/iommu/iommu-priv.h +++ b/drivers/iommu/iommu-priv.h @@ -53,18 +53,10 @@ int iommu_replace_group_handle(struct iommu_group *grou= p, struct iommu_attach_handle *handle); =20 #if IS_ENABLED(CONFIG_IOMMUFD_DRIVER_CORE) && IS_ENABLED(CONFIG_IRQ_MSI_IO= MMU) -int iommufd_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, - phys_addr_t msi_addr); int iommufd_sw_map_msi(struct iommu_domain *domain, struct device *dev, phys_addr_t msi_addr, size_t required_size, dma_addr_t *msi_iova, unsigned int *msi_shift); #else /* !CONFIG_IOMMUFD_DRIVER_CORE || !CONFIG_IRQ_MSI_IOMMU */ -static inline int iommufd_sw_msi(struct iommu_domain *domain, - struct msi_desc *desc, phys_addr_t msi_addr) -{ - return -EOPNOTSUPP; -} - static inline int iommufd_sw_map_msi(struct iommu_domain *domain, struct device *dev, phys_addr_t msi_addr, size_t required_size, dma_addr_t *msi_iova, diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index a3dea7353500..84b60d0f8c23 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -1364,15 +1364,46 @@ void iommu_group_remove_device(struct device *dev) } EXPORT_SYMBOL_GPL(iommu_group_remove_device); =20 -#if IS_ENABLED(CONFIG_LOCKDEP) && IS_ENABLED(CONFIG_IOMMU_API) +#if IS_ENABLED(CONFIG_IOMMU_API) +/* + * iommu_group_mutex_lock(), iommu_group_mutex_unlock(), and + * iommu_group_mutex_assert() must be called after device group param is + * set. + */ + +/** + * iommu_group_mutex_lock - Lock the iommu group mutex for a device + * @dev: the device whose group mutex should be locked + * + * Callers that need to invoke a function documented as requiring the + * device's iommu group mutex (e.g. iommu_dma_map_msi()) from outside + * drivers/iommu/ use this instead of reaching into struct iommu_group, + * which is private to the core. Must be paired with + * iommu_group_mutex_unlock(). + */ +void iommu_group_mutex_lock(struct device *dev) +{ + mutex_lock(&dev->iommu_group->mutex); +} +EXPORT_SYMBOL_GPL(iommu_group_mutex_lock); + +/** + * iommu_group_mutex_unlock - Unlock the iommu group mutex for a device + * @dev: the device whose group mutex should be unlocked + */ +void iommu_group_mutex_unlock(struct device *dev) +{ + mutex_unlock(&dev->iommu_group->mutex); +} +EXPORT_SYMBOL_GPL(iommu_group_mutex_unlock); + +#if IS_ENABLED(CONFIG_LOCKDEP) /** * iommu_group_mutex_assert - Check device group mutex lock * @dev: the device that has group param set * * This function is called by an iommu driver to check whether it holds * group mutex lock for the given device or not. - * - * Note that this function must be called after device group param is set. */ void iommu_group_mutex_assert(struct device *dev) { @@ -1381,7 +1412,8 @@ void iommu_group_mutex_assert(struct device *dev) lockdep_assert_held(&group->mutex); } EXPORT_SYMBOL_GPL(iommu_group_mutex_assert); -#endif +#endif /* CONFIG_LOCKDEP */ +#endif /* CONFIG_IOMMU_API */ =20 static struct device *iommu_group_first_dev(struct iommu_group *group) { @@ -4223,6 +4255,52 @@ void pci_dev_reset_iommu_done(struct pci_dev *pdev) EXPORT_SYMBOL_GPL(pci_dev_reset_iommu_done); =20 #if IS_ENABLED(CONFIG_IRQ_MSI_IOMMU) +/** + * iommu_dma_map_msi() - Map an MSI page in an IOMMU domain + * @domain: IOMMU domain to map into + * @dev: Device used to allocate the IOVA + * @msi_addr: MSI target address to be mapped + * @required_size: Required mapping size, or 0 to accept any size + * @msi_iova: IOVA for @msi_addr, or 0 for passthrough + * @msi_shift: Mapping granule shift, or 0 for passthrough + * + * The caller must hold @dev's iommu group mutex, e.g. via + * iommu_group_mutex_lock()/iommu_group_mutex_unlock(). This function does + * not take the mutex itself because callers building a table of mappings + * (e.g. one IOVA per possible CPU's IMSIC page) call it in a loop; locking + * inside would mean re-acquiring the mutex on every iteration and would n= ot + * stop the domain from changing between iterations, leaving the table + * inconsistent. The caller locks once around the whole loop instead. + * + * Return: 0 on success or negative error code if the mapping failed. + */ +int iommu_dma_map_msi(struct iommu_domain *domain, + struct device *dev, phys_addr_t msi_addr, + size_t required_size, dma_addr_t *msi_iova, + unsigned int *msi_shift) +{ + *msi_iova =3D 0; + *msi_shift =3D 0; + + if (!domain) + return -EINVAL; + + if (domain->type =3D=3D IOMMU_DOMAIN_IDENTITY) + return 0; + + switch (domain->cookie_type) { + case IOMMU_COOKIE_DMA_MSI: + case IOMMU_COOKIE_DMA_IOVA: + return iommu_dma_sw_map_msi(domain, dev, msi_addr, + required_size, msi_iova, msi_shift); + case IOMMU_COOKIE_IOMMUFD: + return iommufd_sw_map_msi(domain, dev, msi_addr, + required_size, msi_iova, msi_shift); + default: + return -EOPNOTSUPP; + } +} + /** * iommu_dma_prepare_msi() - Map the MSI page in the IOMMU domain * @desc: MSI descriptor, will store the MSI page @@ -4238,6 +4316,8 @@ int iommu_dma_prepare_msi(struct msi_desc *desc, phys= _addr_t msi_addr) { struct device *dev =3D msi_desc_to_dev(desc); struct iommu_group *group =3D dev->iommu_group; + dma_addr_t msi_iova; + unsigned int msi_shift; int ret =3D 0; =20 if (!group) @@ -4246,18 +4326,10 @@ int iommu_dma_prepare_msi(struct msi_desc *desc, ph= ys_addr_t msi_addr) mutex_lock(&group->mutex); /* An IDENTITY domain must pass through */ if (group->domain && group->domain->type !=3D IOMMU_DOMAIN_IDENTITY) { - switch (group->domain->cookie_type) { - case IOMMU_COOKIE_DMA_MSI: - case IOMMU_COOKIE_DMA_IOVA: - ret =3D iommu_dma_sw_msi(group->domain, desc, msi_addr); - break; - case IOMMU_COOKIE_IOMMUFD: - ret =3D iommufd_sw_msi(group->domain, desc, msi_addr); - break; - default: - ret =3D -EOPNOTSUPP; - break; - } + ret =3D iommu_dma_map_msi(group->domain, dev, msi_addr, 0, + &msi_iova, &msi_shift); + if (!ret) + msi_desc_set_iommu_msi_iova(desc, msi_iova, msi_shift); } mutex_unlock(&group->mutex); return ret; diff --git a/drivers/iommu/iommufd/driver.c b/drivers/iommu/iommufd/driver.c index 69b3dbcbee3b..b39796bc7251 100644 --- a/drivers/iommu/iommufd/driver.c +++ b/drivers/iommu/iommufd/driver.c @@ -249,11 +249,11 @@ int iommufd_sw_msi_install(struct iommufd_ctx *ictx, EXPORT_SYMBOL_NS_GPL(iommufd_sw_msi_install, "IOMMUFD_INTERNAL"); =20 /* - * Descriptor-free counterpart to iommufd_sw_msi(). Maps an MSI physical p= age - * into the domain and returns the IOVA. Used for pre-mapping MSI targets = before - * any MSI descriptor has been set (e.g. IMSIC doorbell pages). The IOVA is - * global to the iommufd file descriptor: every domain and device using the - * same MSI parameters gets the same IOVA. + * Maps an MSI physical page into the domain and returns the IOVA. Used for + * pre-mapping MSI targets before any MSI descriptor has been set (e.g. + * IMSIC doorbell pages). The IOVA is global to the iommufd file + * descriptor: every domain and device using the same MSI parameters gets + * the same IOVA. * * msi_addr is the exact byte offset of the MSI doorbell; the caller must = have * verified it is contained within an MMIO region safe to map at PAGE_SIZE= . If @@ -321,27 +321,6 @@ int iommufd_sw_map_msi(struct iommu_domain *domain, st= ruct device *dev, return 0; } EXPORT_SYMBOL_NS_GPL(iommufd_sw_map_msi, "IOMMUFD"); - -/* - * Called by the irq layer when the platform translates MSI addresses thro= ugh - * the IOMMU. Wraps iommufd_sw_map_msi() and stores the result in the desc= riptor. - */ -int iommufd_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, - phys_addr_t msi_addr) -{ - dma_addr_t msi_iova; - unsigned int msi_shift; - int rc; - - rc =3D iommufd_sw_map_msi(domain, msi_desc_to_dev(desc), msi_addr, - 0, &msi_iova, &msi_shift); - if (rc) - return rc; - - msi_desc_set_iommu_msi_iova(desc, msi_iova, msi_shift); - return 0; -} -EXPORT_SYMBOL_NS_GPL(iommufd_sw_msi, "IOMMUFD"); #endif =20 MODULE_DESCRIPTION("iommufd code shared with builtin modules"); diff --git a/include/linux/iommu.h b/include/linux/iommu.h index ac43b8b93f14..868b14b63e77 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -8,6 +8,7 @@ #define __LINUX_IOMMU_H =20 #include +#include #include #include #include @@ -1561,8 +1562,22 @@ static inline void pci_dev_reset_iommu_done(struct p= ci_dev *pdev) =20 #ifdef CONFIG_IRQ_MSI_IOMMU #ifdef CONFIG_IOMMU_API +int iommu_dma_map_msi(struct iommu_domain *domain, + struct device *dev, phys_addr_t msi_addr, + size_t required_size, dma_addr_t *msi_iova, + unsigned int *msi_shift); int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr); #else +static inline int iommu_dma_map_msi(struct iommu_domain *domain, + struct device *dev, phys_addr_t msi_addr, + size_t required_size, dma_addr_t *msi_iova, + unsigned int *msi_shift) +{ + *msi_iova =3D 0; + *msi_shift =3D 0; + return 0; +} + static inline int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr) { @@ -1571,6 +1586,22 @@ static inline int iommu_dma_prepare_msi(struct msi_d= esc *desc, #endif /* CONFIG_IOMMU_API */ #endif /* CONFIG_IRQ_MSI_IOMMU */ =20 +#if IS_ENABLED(CONFIG_IOMMU_API) +void iommu_group_mutex_lock(struct device *dev); +void iommu_group_mutex_unlock(struct device *dev); +#else +static inline void iommu_group_mutex_lock(struct device *dev) { } +static inline void iommu_group_mutex_unlock(struct device *dev) { } +#endif + +/* + * scoped_guard(iommu_group, dev) { ... } locks dev's iommu group mutex for + * the scope of the block. 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charset="utf-8" Interrupt-remapping drivers may need to prepare software MSI mappings for an incoming domain from their attach_dev() callback. At that point the device is not yet attached to the supplied domain and, for an iommufd replacement, the current attach handle still describes the old domain. Document that iommu_dma_map_msi() supports this use. Clarify the DMA backend only requires a compatible device and that the iommufd backend intentionally combines context from the current handle with the explicitly supplied destination HWPT. Signed-off-by: Andrew Jones --- drivers/iommu/dma-iommu.c | 7 ++++--- drivers/iommu/iommu.c | 5 +++++ drivers/iommu/iommufd/driver.c | 8 +++++--- 3 files changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 39ee5f0b1da9..030948a7e6b9 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -2252,9 +2252,10 @@ static struct iommu_dma_msi_page *iommu_dma_get_msi_= page(struct device *dev, * mapping granule. Used for pre-mapping MSI targets before any MSI * descriptor has been set. * - * The caller must pass a device attached to @domain and hold @dev's IOMMU - * group mutex. If @required_size is non-zero then it must exactly match t= he - * domain's MSI mapping granule. @msi_iova and @msi_shift must be non-NULL. + * The caller must pass a device compatible with @domain and hold @dev's I= OMMU + * group mutex. @domain may be the incoming domain of an attach_dev() call= back. + * If @required_size is non-zero then it must exactly match the domain's M= SI + * mapping granule. @msi_iova and @msi_shift must be non-NULL. */ int iommu_dma_sw_map_msi(struct iommu_domain *domain, struct device *dev, phys_addr_t msi_addr, diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 84b60d0f8c23..389d67c4bda3 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -4272,6 +4272,11 @@ EXPORT_SYMBOL_GPL(pci_dev_reset_iommu_done); * stop the domain from changing between iterations, leaving the table * inconsistent. The caller locks once around the whole loop instead. * + * @domain may be the incoming domain of an attach_dev() callback. In that + * case, @dev need not be attached to @domain yet, but it must be compatib= le + * with @domain and the caller must keep the current group attachment stab= le + * until the callback completes. + * * Return: 0 on success or negative error code if the mapping failed. */ int iommu_dma_map_msi(struct iommu_domain *domain, diff --git a/drivers/iommu/iommufd/driver.c b/drivers/iommu/iommufd/driver.c index b39796bc7251..358cc6d87941 100644 --- a/drivers/iommu/iommufd/driver.c +++ b/drivers/iommu/iommufd/driver.c @@ -281,9 +281,11 @@ int iommufd_sw_map_msi(struct iommu_domain *domain, st= ruct device *dev, return -EOPNOTSUPP; =20 /* - * It is safe to call iommu_attach_handle_get() here because the iommu - * core code invokes this under the group mutex which also prevents any - * change of the attach handle for the duration of this function. + * During a domain replacement this returns the current handle, not the + * handle for @domain. That is intentional: the current handle supplies + * the stable iommufd context and group MSI window, while @domain selects + * the HWPT where the mapping is installed. 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charset="utf-8" Add a bus token for MSI domains that remap interrupts, needed by the upcoming RISC-V IOMMU interrupt-remapping domain to distinguish itself from NEXUS domains. The token is generic because remapping itself is the only property that needs to be conveyed -- there is nothing RISC-V-specific about it. Such a domain implements init_dev_msi_info() via msi_parent_init_dev_msi_info(), which leaves 'domain' pointing at the NEXUS domain while 'real_parent' points at the remap domain itself. Accept that combination in msi_lib_init_dev_msi_info(); no other msi-lib changes are needed. Signed-off-by: Andrew Jones Reviewed-by: Nutty Liu --- drivers/irqchip/irq-msi-lib.c | 8 ++++---- include/linux/irqdomain_defs.h | 1 + 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-msi-lib.c b/drivers/irqchip/irq-msi-lib.c index 45e0ed3134ce..9027dfbab15e 100644 --- a/drivers/irqchip/irq-msi-lib.c +++ b/drivers/irqchip/irq-msi-lib.c @@ -36,14 +36,14 @@ bool msi_lib_init_dev_msi_info(struct device *dev, stru= ct irq_domain *domain, return false; =20 /* - * MSI parent domain specific settings. For now there is only the - * root parent domain, e.g. NEXUS, acting as a MSI parent, but it is - * possible to stack MSI parents. See x86 vector -> irq remapping + * MSI parent domain specific settings. There may be only the root + * parent domain, e.g. NEXUS, acting as a MSI parent, or there may + * be stacked MSI parents, typically used for remapping. */ if (domain->bus_token =3D=3D pops->bus_select_token) { if (WARN_ON_ONCE(domain !=3D real_parent)) return false; - } else { + } else if (real_parent->bus_token !=3D DOMAIN_BUS_MSI_REMAP) { WARN_ON_ONCE(1); return false; } diff --git a/include/linux/irqdomain_defs.h b/include/linux/irqdomain_defs.h index 3a03bdfeeee9..954cf585b3c4 100644 --- a/include/linux/irqdomain_defs.h +++ b/include/linux/irqdomain_defs.h @@ -26,6 +26,7 @@ enum irq_domain_bus_token { DOMAIN_BUS_AMDVI, DOMAIN_BUS_DEVICE_MSI, DOMAIN_BUS_WIRED_TO_MSI, + DOMAIN_BUS_MSI_REMAP, }; =20 #endif /* _LINUX_IRQDOMAIN_DEFS_H */ --=20 2.43.0 From nobody Mon Sep 28 14:47:12 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E22D525F988 for ; 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charset="utf-8" imsic_irq_set_affinity() currently writes a newly composed MSI message directly to the device. This bypasses intermediate irqdomains, so an IOMMU remapping domain cannot translate the target after an affinity change. Compose affinity updates from the top of the hierarchy instead. This allows each intermediate domain to update the message and any descriptor state before the device is programmed. Non-atomic moves temporarily use the old address with the new interrupt ID before switching to the new vector. Preserve that transition by composing the temporary message before publishing the new vector, then compose the final message after publishing it, but before the old vector is retired. Signed-off-by: Andrew Jones --- drivers/irqchip/irq-riscv-imsic-platform.c | 27 ++++++++-------------- 1 file changed, 10 insertions(+), 17 deletions(-) diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/i= rq-riscv-imsic-platform.c index 643c8e459611..5634641dc223 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -90,19 +90,12 @@ static void imsic_irq_compose_msg(struct irq_data *d, s= truct msi_msg *msg) } =20 #ifdef CONFIG_SMP -static void imsic_msi_update_msg(struct irq_data *d, struct imsic_vector *= vec) -{ - struct msi_msg msg =3D { }; - - imsic_irq_compose_vector_msg(vec, &msg); - irq_data_get_irq_chip(d)->irq_write_msi_msg(d, &msg); -} - static int imsic_irq_set_affinity(struct irq_data *d, const struct cpumask= *mask_val, bool force) { + struct irq_data *top =3D irq_get_irq_data(d->irq); struct imsic_vector *old_vec, *new_vec; - struct imsic_vector tmp_vec; + struct msi_msg msg =3D { }; =20 /* * Requirements for the downstream irqdomains (or devices): @@ -153,20 +146,20 @@ static int imsic_irq_set_affinity(struct irq_data *d,= const struct cpumask *mask */ if (!irq_can_move_in_process_context(d) && new_vec->local_id !=3D old_vec->local_id) { - /* Setup temporary vector */ - tmp_vec.cpu =3D old_vec->cpu; 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charset="utf-8" Create a per-device MSI parent domain as a hook for interrupt remapping. Keep the remapping tables with the attached paging domain because MSI IOVA mappings are part of its page tables. Initially, the new domain only forwards operations to its parent. Later commits add MSI target mappings for paging domains, while non-paging domains continue to use physical IMSIC addresses. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/Makefile | 2 +- drivers/iommu/riscv/iommu-ir.c | 118 ++++++++++++++++++++++++++++ drivers/iommu/riscv/iommu.c | 46 ++++++----- drivers/iommu/riscv/iommu.h | 27 +++++++ include/linux/irqchip/riscv-imsic.h | 7 ++ 5 files changed, 181 insertions(+), 19 deletions(-) create mode 100644 drivers/iommu/riscv/iommu-ir.c diff --git a/drivers/iommu/riscv/Makefile b/drivers/iommu/riscv/Makefile index b5929f9f23e6..9c83f877d50f 100644 --- a/drivers/iommu/riscv/Makefile +++ b/drivers/iommu/riscv/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y +=3D iommu.o iommu-platform.o +obj-y +=3D iommu.o iommu-ir.o iommu-platform.o obj-$(CONFIG_RISCV_IOMMU_PCI) +=3D iommu-pci.o diff --git a/drivers/iommu/riscv/iommu-ir.c b/drivers/iommu/riscv/iommu-ir.c new file mode 100644 index 000000000000..0aab0efeb70e --- /dev/null +++ b/drivers/iommu/riscv/iommu-ir.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * IOMMU Interrupt Remapping + * + * Copyright (c) 2026 Qualcomm Technologies, Inc. + */ +#include +#include +#include + +#include "iommu.h" + +static struct irq_chip riscv_iommu_ir_irq_chip =3D { + .name =3D "IOMMU-IR", + .irq_ack =3D irq_chip_ack_parent, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_set_affinity =3D irq_chip_set_affinity_parent, +}; + +static int riscv_iommu_ir_irq_domain_alloc_irqs(struct irq_domain *irqdoma= in, + unsigned int irq_base, unsigned int nr_irqs, + void *arg) +{ + int ret; + + ret =3D irq_domain_alloc_irqs_parent(irqdomain, irq_base, nr_irqs, arg); + if (ret) + return ret; + + for (unsigned int i =3D 0; i < nr_irqs; i++) { + struct irq_data *data =3D irq_domain_get_irq_data(irqdomain, irq_base + = i); + + data->chip =3D &riscv_iommu_ir_irq_chip; + } + + return 0; +} + +static const struct irq_domain_ops riscv_iommu_ir_irq_domain_ops =3D { + .alloc =3D riscv_iommu_ir_irq_domain_alloc_irqs, + .free =3D irq_domain_free_irqs_parent, +}; + +static const struct msi_parent_ops riscv_iommu_ir_msi_parent_ops =3D { + .prefix =3D "IR-", + .supported_flags =3D MSI_GENERIC_FLAGS_MASK | + MSI_FLAG_PCI_MSIX, + .required_flags =3D MSI_FLAG_USE_DEF_DOM_OPS | + MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_PCI_MSI_MASK_PARENT, + .chip_flags =3D MSI_CHIP_FLAG_SET_ACK, + .init_dev_msi_info =3D msi_parent_init_dev_msi_info, +}; + +struct irq_domain *riscv_iommu_ir_irq_domain_create(struct device *dev, + struct riscv_iommu_info *info) +{ + struct irq_domain *irqparent =3D dev_get_msi_domain(dev); + char *fwname __free(kfree) =3D NULL; + struct irq_domain *irqdomain; + struct fwnode_handle *fn; + + if (!irqparent) + return NULL; + + fwname =3D kasprintf(GFP_KERNEL, "IOMMU-IR-%s", dev_name(dev)); + if (!fwname) + return ERR_PTR(-ENOMEM); + + fn =3D irq_domain_alloc_named_fwnode(fwname); + if (!fn) + return ERR_PTR(-ENOMEM); + + irqdomain =3D irq_domain_create_hierarchy(irqparent, 0, 0, fn, + &riscv_iommu_ir_irq_domain_ops, info); + if (!irqdomain) { + irq_domain_free_fwnode(fn); + return ERR_PTR(-ENOMEM); + } + + /* + * The RISC-V IOMMU doesn't validate MSI data, so we can't set + * IRQ_DOMAIN_FLAG_ISOLATED_MSI. This means VFIO requires its + * allow_unsafe_interrupts module parameter. + */ + irqdomain->flags |=3D IRQ_DOMAIN_FLAG_MSI_PARENT; + irqdomain->msi_parent_ops =3D &riscv_iommu_ir_msi_parent_ops; + irq_domain_update_bus_token(irqdomain, DOMAIN_BUS_MSI_REMAP); + + dev_set_msi_domain(dev, irqdomain); + + return irqdomain; +} + +void riscv_iommu_ir_irq_domain_remove(struct device *dev, struct riscv_iom= mu_info *info) +{ + struct fwnode_handle *fn; + + if (!info->irqdomain) + return; + + dev_set_msi_domain(dev, info->irqdomain->parent); + fn =3D info->irqdomain->fwnode; + irq_domain_remove(info->irqdomain); + info->irqdomain =3D NULL; + irq_domain_free_fwnode(fn); +} + +int riscv_iommu_ir_attach_paging_domain(struct iommu_domain *iommu_domain,= struct device *dev, + struct iommu_domain *old) +{ + return 0; +} + +void riscv_iommu_ir_free_paging_domain(struct iommu_domain *iommu_domain) +{ +} diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index cec3ddd7ab10..bfe606a0cb9a 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -19,9 +19,9 @@ #include #include #include +#include #include #include -#include =20 #include "../iommu-pages.h" #include "iommu-bits.h" @@ -810,26 +810,9 @@ static int riscv_iommu_iodir_set_mode(struct riscv_iom= mu_device *iommu, return 0; } =20 -/* This struct contains protection domain specific IOMMU driver data. */ -struct riscv_iommu_domain { - union { - struct iommu_domain domain; - struct pt_iommu_riscv_64 riscvpt; - }; - struct list_head bonds; - spinlock_t lock; /* protect bonds list updates. */ - int pscid; -}; -PT_IOMMU_CHECK_DOMAIN(struct riscv_iommu_domain, riscvpt.iommu, domain); - #define iommu_domain_to_riscv(iommu_domain) \ container_of(iommu_domain, struct riscv_iommu_domain, domain) =20 -/* Private IOMMU data for managed devices, dev_iommu_priv_* */ -struct riscv_iommu_info { - struct riscv_iommu_domain *domain; -}; - /* * Linkage between an iommu_domain and attached devices. * @@ -1258,6 +1241,8 @@ static void riscv_iommu_free_paging_domain(struct iom= mu_domain *iommu_domain) =20 WARN_ON(!list_empty(&domain->bonds)); =20 + riscv_iommu_ir_free_paging_domain(iommu_domain); + if ((int)domain->pscid > 0) ida_free(&riscv_iommu_pscids, domain->pscid); =20 @@ -1289,6 +1274,7 @@ static int riscv_iommu_attach_paging_domain(struct io= mmu_domain *iommu_domain, struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); struct pt_iommu_riscv_64_hw_info pt_info; u64 fsc, ta; + int ret; =20 pt_iommu_riscv_64_hw_info(&domain->riscvpt, &pt_info); =20 @@ -1303,6 +1289,12 @@ static int riscv_iommu_attach_paging_domain(struct i= ommu_domain *iommu_domain, if (riscv_iommu_bond_link(domain, dev)) return -ENOMEM; =20 + ret =3D riscv_iommu_ir_attach_paging_domain(iommu_domain, dev, old); + if (ret) { + riscv_iommu_bond_unlink(domain, dev); + return ret; + } + riscv_iommu_iodir_update(iommu, dev, fsc, ta); riscv_iommu_bond_unlink(info->domain, dev); info->domain =3D domain; @@ -1430,6 +1422,7 @@ static int riscv_iommu_of_xlate(struct device *dev, c= onst struct of_phandle_args static struct iommu_device *riscv_iommu_probe_device(struct device *dev) { struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(dev); + struct irq_domain *irqdomain =3D NULL; struct riscv_iommu_device *iommu; struct riscv_iommu_info *info; struct riscv_iommu_dc *dc; @@ -1453,6 +1446,21 @@ static struct iommu_device *riscv_iommu_probe_device= (struct device *dev) info =3D kzalloc_obj(*info); if (!info) return ERR_PTR(-ENOMEM); + + if (imsic_enabled()) { + irqdomain =3D riscv_iommu_ir_irq_domain_create(dev, info); + if (IS_ERR(irqdomain)) { + kfree(info); + return ERR_CAST(irqdomain); + } + } + + /* + * irqdomain is NULL when it's not necessary; either there aren't + * any IMSICs or no MSI domain has been set up for the device. + */ + info->irqdomain =3D irqdomain; + /* * Allocate and pre-configure device context entries in * the device directory. Do not mark the context valid yet. @@ -1461,6 +1469,7 @@ static struct iommu_device *riscv_iommu_probe_device(= struct device *dev) for (i =3D 0; i < fwspec->num_ids; i++) { dc =3D riscv_iommu_get_dc(iommu, fwspec->ids[i]); if (!dc) { + riscv_iommu_ir_irq_domain_remove(dev, info); kfree(info); return ERR_PTR(-ENODEV); } @@ -1478,6 +1487,7 @@ static void riscv_iommu_release_device(struct device = *dev) { struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); =20 + riscv_iommu_ir_irq_domain_remove(dev, info); kfree_rcu_mightsleep(info); } =20 diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index 46df79dd5495..5d83537911b6 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -14,9 +14,29 @@ #include #include #include +#include +#include =20 #include "iommu-bits.h" =20 +/* This struct contains protection domain specific IOMMU driver data. */ +struct riscv_iommu_domain { + union { + struct iommu_domain domain; + struct pt_iommu_riscv_64 riscvpt; + }; + struct list_head bonds; + spinlock_t lock; /* protect bonds list updates. */ + int pscid; +}; +PT_IOMMU_CHECK_DOMAIN(struct riscv_iommu_domain, riscvpt.iommu, domain); + +/* Private IOMMU data for managed devices, dev_iommu_priv_* */ +struct riscv_iommu_info { + struct riscv_iommu_domain *domain; + struct irq_domain *irqdomain; +}; + struct riscv_iommu_device; =20 struct riscv_iommu_queue { @@ -66,6 +86,13 @@ int riscv_iommu_init(struct riscv_iommu_device *iommu); void riscv_iommu_remove(struct riscv_iommu_device *iommu); void riscv_iommu_disable(struct riscv_iommu_device *iommu); =20 +struct irq_domain *riscv_iommu_ir_irq_domain_create(struct device *dev, + struct riscv_iommu_info *info); +void riscv_iommu_ir_irq_domain_remove(struct device *dev, struct riscv_iom= mu_info *info); +int riscv_iommu_ir_attach_paging_domain(struct iommu_domain *iommu_domain,= struct device *dev, + struct iommu_domain *old); +void riscv_iommu_ir_free_paging_domain(struct iommu_domain *iommu_domain); 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charset="utf-8" Platform devices receive their MSI domain when they are created. On RISC-V, the IMSIC is itself a platform device, so consumer devices may be created before the IMSIC driver registers its MSI domain. fw_devlink delays consumer driver probing but does not refresh dev->msi.domain, leaving it NULL when the IOMMU probe_device callback runs. Refresh the OF or ACPI platform MSI domain before creating the per-device interrupt-remapping domain. Leave PCI devices alone because PCI establishes their MSI domain during device setup. This mirrors the workaround currently used by other RISC-V platform MSI consumers. A proposed driver-core change would perform the refresh from platform_dma_configure(), but until that is merged the local refresh avoids silently skipping interrupt-remapping setup. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu-ir.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/riscv/iommu-ir.c b/drivers/iommu/riscv/iommu-ir.c index 0aab0efeb70e..3e08249015cd 100644 --- a/drivers/iommu/riscv/iommu-ir.c +++ b/drivers/iommu/riscv/iommu-ir.c @@ -4,8 +4,11 @@ * * Copyright (c) 2026 Qualcomm Technologies, Inc. */ +#include #include #include +#include +#include #include =20 #include "iommu.h" @@ -53,14 +56,35 @@ static const struct msi_parent_ops riscv_iommu_ir_msi_p= arent_ops =3D { .init_dev_msi_info =3D msi_parent_init_dev_msi_info, }; =20 +static void riscv_iommu_ir_refresh_msi_domain(struct device *dev) +{ + struct fwnode_handle *fwnode =3D dev_fwnode(dev); + struct irq_domain *irqdomain; + + if (dev_get_msi_domain(dev) || !dev_is_platform(dev)) + return; + + if (is_of_node(fwnode)) { + of_msi_configure(dev, to_of_node(fwnode)); + } else if (is_acpi_device_node(fwnode)) { + fwnode =3D imsic_acpi_get_fwnode(dev); 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charset="utf-8" An upcoming compose_msi_msg() implementation reads info->domain from potentially atomic context, concurrent with domain switches. Apply RCU in preparation. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu.c | 26 ++++++++++++++++---------- drivers/iommu/riscv/iommu.h | 3 ++- 2 files changed, 18 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index bfe606a0cb9a..4e14c8412abc 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -865,17 +865,21 @@ static int riscv_iommu_bond_link(struct riscv_iommu_d= omain *domain, return 0; } =20 -static void riscv_iommu_bond_unlink(struct riscv_iommu_domain *domain, +static void riscv_iommu_bond_unlink(struct iommu_domain *iommu_domain, struct device *dev) { - struct riscv_iommu_device *iommu =3D dev_to_iommu(dev); + struct riscv_iommu_domain *domain; + struct riscv_iommu_device *iommu; struct riscv_iommu_bond *bond, *found =3D NULL; struct riscv_iommu_command cmd; int count =3D 0; =20 - if (!domain) + if (!iommu_domain || !(iommu_domain->type & __IOMMU_DOMAIN_PAGING)) return; =20 + domain =3D iommu_domain_to_riscv(iommu_domain); + iommu =3D dev_to_iommu(dev); + spin_lock(&domain->lock); list_for_each_entry(bond, &domain->bonds, list) { if (found && count) @@ -1241,6 +1245,8 @@ static void riscv_iommu_free_paging_domain(struct iom= mu_domain *iommu_domain) =20 WARN_ON(!list_empty(&domain->bonds)); =20 + synchronize_rcu(); + riscv_iommu_ir_free_paging_domain(iommu_domain); =20 if ((int)domain->pscid > 0) @@ -1291,13 +1297,13 @@ static int riscv_iommu_attach_paging_domain(struct = iommu_domain *iommu_domain, =20 ret =3D riscv_iommu_ir_attach_paging_domain(iommu_domain, dev, old); if (ret) { - riscv_iommu_bond_unlink(domain, dev); + riscv_iommu_bond_unlink(iommu_domain, dev); return ret; } =20 riscv_iommu_iodir_update(iommu, dev, fsc, ta); - riscv_iommu_bond_unlink(info->domain, dev); - info->domain =3D domain; + riscv_iommu_bond_unlink(old, dev); + rcu_assign_pointer(info->domain, domain); =20 return 0; } @@ -1373,8 +1379,8 @@ static int riscv_iommu_attach_blocking_domain(struct = iommu_domain *iommu_domain, =20 /* Make device context invalid, translation requests will fault w/ #258 */ riscv_iommu_iodir_update(iommu, dev, RISCV_IOMMU_FSC_BARE, 0); - riscv_iommu_bond_unlink(info->domain, dev); - info->domain =3D NULL; + riscv_iommu_bond_unlink(old, dev); + rcu_assign_pointer(info->domain, NULL); =20 return 0; } @@ -1394,8 +1400,8 @@ static int riscv_iommu_attach_identity_domain(struct = iommu_domain *iommu_domain, struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); =20 riscv_iommu_iodir_update(iommu, dev, RISCV_IOMMU_FSC_BARE, RISCV_IOMMU_PC= _TA_V); - riscv_iommu_bond_unlink(info->domain, dev); - info->domain =3D NULL; + riscv_iommu_bond_unlink(old, dev); + rcu_assign_pointer(info->domain, NULL); =20 return 0; } diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index 5d83537911b6..ded18aec8010 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -15,6 +15,7 @@ #include #include #include +#include #include =20 #include "iommu-bits.h" @@ -33,7 +34,7 @@ PT_IOMMU_CHECK_DOMAIN(struct riscv_iommu_domain, riscvpt.= iommu, domain); =20 /* Private IOMMU data for managed devices, dev_iommu_priv_* */ struct riscv_iommu_info { - struct riscv_iommu_domain *domain; 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charset="utf-8" iommufd requires an IOMMU_RESV_SW_MSI region to allocate stable IOVAs for MSI targets. Advertise such a region when the device uses an IMSIC MSI hierarchy so interrupt remapping can map IMSIC pages instead of falling back to physical addresses. Reserve one page per possible CPU, sufficient for each supervisor IMSIC page. Place the window at 128 MiB, matching the established ARM SMMU MSI IOVA convention rather than introducing an architecture-specific choice. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu-ir.c | 16 ++++++++++++++++ drivers/iommu/riscv/iommu.c | 8 ++++++++ drivers/iommu/riscv/iommu.h | 5 +++++ 3 files changed, 29 insertions(+) diff --git a/drivers/iommu/riscv/iommu-ir.c b/drivers/iommu/riscv/iommu-ir.c index 3e08249015cd..de5e22ecbd63 100644 --- a/drivers/iommu/riscv/iommu-ir.c +++ b/drivers/iommu/riscv/iommu-ir.c @@ -140,3 +140,19 @@ int riscv_iommu_ir_attach_paging_domain(struct iommu_d= omain *iommu_domain, struc void riscv_iommu_ir_free_paging_domain(struct iommu_domain *iommu_domain) { } + +void riscv_iommu_ir_get_resv_regions(struct device *dev, struct list_head = *head) +{ + struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); + struct iommu_resv_region *region; + + if (!info || !info->irqdomain) + return; + + region =3D iommu_alloc_resv_region(RISCV_IOMMU_MSI_IOVA_BASE, + (size_t)num_possible_cpus() * PAGE_SIZE, + IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO, + IOMMU_RESV_SW_MSI, GFP_KERNEL); + if (region) + list_add_tail(®ion->list, head); +} diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 4e14c8412abc..049ca1852d7b 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -23,6 +23,7 @@ #include #include =20 +#include "../dma-iommu.h" #include "../iommu-pages.h" #include "iommu-bits.h" #include "iommu.h" @@ -1497,6 +1498,12 @@ static void riscv_iommu_release_device(struct device= *dev) kfree_rcu_mightsleep(info); } =20 +static void riscv_iommu_get_resv_regions(struct device *dev, struct list_h= ead *head) +{ + riscv_iommu_ir_get_resv_regions(dev, head); + iommu_dma_get_resv_regions(dev, head); +} + static const struct iommu_ops riscv_iommu_ops =3D { .of_xlate =3D riscv_iommu_of_xlate, .identity_domain =3D &riscv_iommu_identity_domain, @@ -1506,6 +1513,7 @@ static const struct iommu_ops riscv_iommu_ops =3D { .device_group =3D riscv_iommu_device_group, .probe_device =3D riscv_iommu_probe_device, .release_device =3D riscv_iommu_release_device, + .get_resv_regions =3D riscv_iommu_get_resv_regions, }; =20 static int riscv_iommu_init_check(struct riscv_iommu_device *iommu) diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index ded18aec8010..16b3c9c4cf8c 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -16,10 +16,14 @@ #include #include #include +#include #include =20 #include "iommu-bits.h" =20 +/* IOVA base for the SW MSI reservation; same convention as ARM SMMU. */ +#define RISCV_IOMMU_MSI_IOVA_BASE SZ_128M + /* This struct contains protection domain specific IOMMU driver data. */ struct riscv_iommu_domain { union { @@ -93,6 +97,7 @@ void riscv_iommu_ir_irq_domain_remove(struct device *dev,= struct riscv_iommu_inf int riscv_iommu_ir_attach_paging_domain(struct iommu_domain *iommu_domain,= struct device *dev, struct iommu_domain *old); void riscv_iommu_ir_free_paging_domain(struct iommu_domain *iommu_domain); +void riscv_iommu_ir_get_resv_regions(struct device *dev, struct list_head = *head); =20 #define riscv_iommu_readl(iommu, addr) \ readl_relaxed((iommu)->reg + (addr)) --=20 2.43.0 From nobody Mon Sep 28 14:47:12 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52F2A48987C for ; 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charset="utf-8" IMSIC target addresses change with interrupt affinity, which may be updated in atomic context. Therefore, an interrupt-remapping domain cannot create mappings on demand while composing an MSI message. Pre-map the supervisor IMSIC page for each possible CPU when a paging domain first allocates remapped interrupts. Also prepare the mappings when attaching a paging domain to a device with allocated interrupts, so an incoming domain is ready before the hardware switches to it. Reject passthrough mapping results because interrupt remapping requires the IMSIC page IOVA and its fixed page shift. Store the resulting IOVAs in a domain-local table so message composition only requires a lookup. Use the IMSIC group and hart fields as the table index, matching the RISC-V IOMMU MSI address extraction scheme. These topology fields do not necessarily produce dense CPU indices, so size the table for their full encoded range and leave unused entries empty. Create the per-device interrupt-remapping domain during IOMMU probe, but publish it from probe_finalize() after the IOMMU core has assigned the device to its group. This ensures the allocation callback can safely lock the group. Select IRQ_MSI_IOMMU for the generic MSI mapping API. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/Kconfig | 1 + drivers/iommu/riscv/iommu-ir.c | 133 ++++++++++++++++++++++++++++++++- drivers/iommu/riscv/iommu.c | 12 ++- drivers/iommu/riscv/iommu.h | 7 ++ 4 files changed, 147 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/riscv/Kconfig b/drivers/iommu/riscv/Kconfig index b86e5ab94183..f557b55c2c14 100644 --- a/drivers/iommu/riscv/Kconfig +++ b/drivers/iommu/riscv/Kconfig @@ -10,6 +10,7 @@ config RISCV_IOMMU select GENERIC_PT select IOMMU_PT select IOMMU_PT_RISCV64 + select IRQ_MSI_IOMMU help Support for implementations of the RISC-V IOMMU architecture that complements the RISC-V MMU capabilities, providing similar address diff --git a/drivers/iommu/riscv/iommu-ir.c b/drivers/iommu/riscv/iommu-ir.c index de5e22ecbd63..4dc104c6d4b1 100644 --- a/drivers/iommu/riscv/iommu-ir.c +++ b/drivers/iommu/riscv/iommu-ir.c @@ -6,13 +6,108 @@ */ #include #include +#include #include #include #include #include +#include =20 #include "iommu.h" =20 +/* + * Compute the MSI index for an MSI physical address using the + * IOMMU "extract" function (RISC-V IOMMU spec section 2.3.3). + */ +static size_t riscv_iommu_ir_extract_msi_idx(phys_addr_t pa) +{ + const struct imsic_global_config *global =3D imsic_get_global_config(); + phys_addr_t mask, addr =3D pa >> 12; + size_t idx; + + mask =3D BIT(global->hart_index_bits + global->guest_index_bits) - 1; + idx =3D addr & mask; + + if (global->group_index_bits) { + phys_addr_t group_mask =3D BIT(global->group_index_bits) - 1; + phys_addr_t group_shift =3D global->group_index_shift - 12; + phys_addr_t group =3D (addr >> group_shift) & group_mask; + + idx |=3D group << fls64(mask); + } + + return idx; +} + +static size_t riscv_iommu_ir_msi_iova_idx(phys_addr_t pa) +{ + const struct imsic_global_config *global =3D imsic_get_global_config(); + + /* msi_iova[] is only used for the host imsics */ + return riscv_iommu_ir_extract_msi_idx(pa) >> global->guest_index_bits; +} + +static size_t riscv_iommu_ir_msi_iova_count(void) +{ + const struct imsic_global_config *global =3D imsic_get_global_config(); + + return BIT(global->group_index_bits + global->hart_index_bits); +} + +static int riscv_iommu_ir_build_msi_iova(struct riscv_iommu_domain *domain= , struct device *dev) +{ + const struct imsic_global_config *global =3D imsic_get_global_config(); + struct iommu_domain *d =3D &domain->domain; + dma_addr_t *msi_iova; + unsigned int cpu; + int ret; + + guard(mutex)(&domain->mutex); + + if (domain->msi_iova) + return 0; + + switch (d->cookie_type) { + case IOMMU_COOKIE_DMA_IOVA: + case IOMMU_COOKIE_DMA_MSI: + case IOMMU_COOKIE_IOMMUFD: + break; + default: + return 0; + } + + msi_iova =3D vcalloc(riscv_iommu_ir_msi_iova_count(), sizeof(*msi_iova)); + if (!msi_iova) + return -ENOMEM; + + for_each_possible_cpu(cpu) { + const struct imsic_local_config *local =3D per_cpu_ptr(global->local, cp= u); + phys_addr_t pa =3D local->msi_pa; + unsigned int shift; + size_t idx; + + if (!pa) + continue; + + idx =3D riscv_iommu_ir_msi_iova_idx(pa); + ret =3D iommu_dma_map_msi(d, dev, pa, IMSIC_MMIO_PAGE_SZ, &msi_iova[idx]= , &shift); + if (ret) + goto err_free; + if (shift !=3D IMSIC_MMIO_PAGE_SHIFT) { + ret =3D -EBUSY; + goto err_free; + } + } + + domain->msi_iova =3D msi_iova; + + return 0; + +err_free: + vfree(msi_iova); + return ret; +} + static struct irq_chip riscv_iommu_ir_irq_chip =3D { .name =3D "IOMMU-IR", .irq_ack =3D irq_chip_ack_parent, @@ -25,8 +120,24 @@ static int riscv_iommu_ir_irq_domain_alloc_irqs(struct = irq_domain *irqdomain, unsigned int irq_base, unsigned int nr_irqs, void *arg) { + struct riscv_iommu_info *info =3D irqdomain->host_data; int ret; =20 + /* + * MSI IOVAs are domain-local, just like DMA IOVAs. The device must be + * quiesced, including MSI teardown, before switching away from or freeing + * the domain. iommu_dma_map_msi() requires the group mutex to be held; + * take it around the domain lookup too so info->domain can't change + * out from under the build. + */ + scoped_guard(iommu_group, info->dev) { + struct riscv_iommu_domain *domain =3D rcu_dereference_protected(info->do= main, true); + + ret =3D domain ? riscv_iommu_ir_build_msi_iova(domain, info->dev) : 0; + } + if (ret) + return ret; + ret =3D irq_domain_alloc_irqs_parent(irqdomain, irq_base, nr_irqs, arg); if (ret) return ret; @@ -112,11 +223,22 @@ struct irq_domain *riscv_iommu_ir_irq_domain_create(s= truct device *dev, irqdomain->msi_parent_ops =3D &riscv_iommu_ir_msi_parent_ops; irq_domain_update_bus_token(irqdomain, DOMAIN_BUS_MSI_REMAP); =20 - dev_set_msi_domain(dev, irqdomain); - + /* + * Publication is deferred to riscv_iommu_ir_irq_domain_publish(), + * called from probe_finalize() after the IOMMU core assigns + * dev->iommu_group, because the allocation callback locks the group. + */ return irqdomain; } =20 +void riscv_iommu_ir_irq_domain_publish(struct device *dev) +{ + struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); + + if (info->irqdomain) + dev_set_msi_domain(dev, info->irqdomain); +} + void riscv_iommu_ir_irq_domain_remove(struct device *dev, struct riscv_iom= mu_info *info) { struct fwnode_handle *fn; @@ -124,7 +246,8 @@ void riscv_iommu_ir_irq_domain_remove(struct device *de= v, struct riscv_iommu_inf if (!info->irqdomain) return; =20 - dev_set_msi_domain(dev, info->irqdomain->parent); + if (dev_get_msi_domain(dev) =3D=3D info->irqdomain) + dev_set_msi_domain(dev, info->irqdomain->parent); fn =3D info->irqdomain->fwnode; irq_domain_remove(info->irqdomain); info->irqdomain =3D NULL; @@ -139,6 +262,10 @@ int riscv_iommu_ir_attach_paging_domain(struct iommu_d= omain *iommu_domain, struc =20 void riscv_iommu_ir_free_paging_domain(struct iommu_domain *iommu_domain) { + struct riscv_iommu_domain *domain =3D iommu_domain_to_riscv(iommu_domain); + + vfree(domain->msi_iova); + domain->msi_iova =3D NULL; } =20 void riscv_iommu_ir_get_resv_regions(struct device *dev, struct list_head = *head) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 049ca1852d7b..1a30bac88101 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -811,9 +811,6 @@ static int riscv_iommu_iodir_set_mode(struct riscv_iomm= u_device *iommu, return 0; } =20 -#define iommu_domain_to_riscv(iommu_domain) \ - container_of(iommu_domain, struct riscv_iommu_domain, domain) - /* * Linkage between an iommu_domain and attached devices. * @@ -1341,6 +1338,8 @@ static struct iommu_domain *riscv_iommu_alloc_paging_= domain(struct device *dev) if (!domain) return ERR_PTR(-ENOMEM); =20 + mutex_init(&domain->mutex); + INIT_LIST_HEAD_RCU(&domain->bonds); spin_lock_init(&domain->lock); /* @@ -1467,6 +1466,7 @@ static struct iommu_device *riscv_iommu_probe_device(= struct device *dev) * any IMSICs or no MSI domain has been set up for the device. */ info->irqdomain =3D irqdomain; + info->dev =3D dev; =20 /* * Allocate and pre-configure device context entries in @@ -1490,6 +1490,11 @@ static struct iommu_device *riscv_iommu_probe_device= (struct device *dev) return &iommu->iommu; } =20 +static void riscv_iommu_probe_finalize(struct device *dev) +{ + riscv_iommu_ir_irq_domain_publish(dev); +} + static void riscv_iommu_release_device(struct device *dev) { struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); @@ -1512,6 +1517,7 @@ static const struct iommu_ops riscv_iommu_ops =3D { .domain_alloc_paging =3D riscv_iommu_alloc_paging_domain, .device_group =3D riscv_iommu_device_group, .probe_device =3D riscv_iommu_probe_device, + .probe_finalize =3D riscv_iommu_probe_finalize, .release_device =3D riscv_iommu_release_device, .get_resv_regions =3D riscv_iommu_get_resv_regions, }; diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index 16b3c9c4cf8c..59779aa9d380 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -32,14 +32,20 @@ struct riscv_iommu_domain { }; struct list_head bonds; spinlock_t lock; /* protect bonds list updates. */ + struct mutex mutex; /* serializes sleepable, domain-wide setups */ int pscid; + dma_addr_t *msi_iova; }; PT_IOMMU_CHECK_DOMAIN(struct riscv_iommu_domain, riscvpt.iommu, domain); =20 +#define iommu_domain_to_riscv(iommu_domain) \ + container_of(iommu_domain, struct riscv_iommu_domain, domain) + /* Private IOMMU data for managed devices, dev_iommu_priv_* */ struct riscv_iommu_info { struct riscv_iommu_domain __rcu *domain; struct irq_domain *irqdomain; + struct device *dev; }; =20 struct riscv_iommu_device; @@ -93,6 +99,7 @@ void riscv_iommu_disable(struct riscv_iommu_device *iommu= ); =20 struct irq_domain *riscv_iommu_ir_irq_domain_create(struct device *dev, struct riscv_iommu_info *info); +void riscv_iommu_ir_irq_domain_publish(struct device *dev); void riscv_iommu_ir_irq_domain_remove(struct device *dev, struct riscv_iom= mu_info *info); int riscv_iommu_ir_attach_paging_domain(struct iommu_domain *iommu_domain,= struct device *dev, struct iommu_domain *old); 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charset="utf-8" MSI IOVAs belong to a paging domain, but iommufd may replace a device's domain while its interrupts remain allocated. Waiting for another IRQ allocation to populate the new table would leave existing interrupts without valid MSI IOVAs. Track live IRQ allocations so the attach path knows when the incoming domain needs an MSI IOVA table. Rebuild the table through iommu_dma_map_msi(), allowing each backend to preserve its own IOVA allocation rules. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu-ir.c | 41 +++++++++++++++++++++++++++++++--- drivers/iommu/riscv/iommu.h | 2 ++ 2 files changed, 40 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/riscv/iommu-ir.c b/drivers/iommu/riscv/iommu-ir.c index 4dc104c6d4b1..5718f90affd6 100644 --- a/drivers/iommu/riscv/iommu-ir.c +++ b/drivers/iommu/riscv/iommu-ir.c @@ -128,19 +128,27 @@ static int riscv_iommu_ir_irq_domain_alloc_irqs(struc= t irq_domain *irqdomain, * quiesced, including MSI teardown, before switching away from or freeing * the domain. iommu_dma_map_msi() requires the group mutex to be held; * take it around the domain lookup too so info->domain can't change - * out from under the build. + * out from under the build. Bump info->nr_irqs here too, before + * irq_domain_alloc_irqs_parent() runs unlocked below, so a concurrent + * riscv_iommu_ir_attach_paging_domain() can never observe a count that + * is lower than the number of IRQs actually in flight for this device. */ scoped_guard(iommu_group, info->dev) { struct riscv_iommu_domain *domain =3D rcu_dereference_protected(info->do= main, true); =20 ret =3D domain ? riscv_iommu_ir_build_msi_iova(domain, info->dev) : 0; + if (!ret) + info->nr_irqs +=3D nr_irqs; } if (ret) return ret; =20 ret =3D irq_domain_alloc_irqs_parent(irqdomain, irq_base, nr_irqs, arg); - if (ret) + if (ret) { + guard(iommu_group)(info->dev); + info->nr_irqs -=3D nr_irqs; return ret; + } =20 for (unsigned int i =3D 0; i < nr_irqs; i++) { struct irq_data *data =3D irq_domain_get_irq_data(irqdomain, irq_base + = i); @@ -151,9 +159,25 @@ static int riscv_iommu_ir_irq_domain_alloc_irqs(struct= irq_domain *irqdomain, return 0; } =20 +static void riscv_iommu_ir_irq_domain_free_irqs(struct irq_domain *irqdoma= in, + unsigned int irq_base, unsigned int nr_irqs) +{ + struct riscv_iommu_info *info =3D irqdomain->host_data; + + irq_domain_free_irqs_parent(irqdomain, irq_base, nr_irqs); + + /* + * Decrement only after the parent free completes, so a concurrent + * riscv_iommu_ir_attach_paging_domain() never observes a count lower + * than the number of IRQs that are actually still live. + */ + scoped_guard(iommu_group, info->dev) + info->nr_irqs -=3D nr_irqs; +} + static const struct irq_domain_ops riscv_iommu_ir_irq_domain_ops =3D { .alloc =3D riscv_iommu_ir_irq_domain_alloc_irqs, - .free =3D irq_domain_free_irqs_parent, + .free =3D riscv_iommu_ir_irq_domain_free_irqs, }; =20 static const struct msi_parent_ops riscv_iommu_ir_msi_parent_ops =3D { @@ -257,6 +281,17 @@ void riscv_iommu_ir_irq_domain_remove(struct device *d= ev, struct riscv_iommu_inf int riscv_iommu_ir_attach_paging_domain(struct iommu_domain *iommu_domain,= struct device *dev, struct iommu_domain *old) { + struct riscv_iommu_domain *domain =3D iommu_domain_to_riscv(iommu_domain); + struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); 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charset="utf-8" MSI composition may run concurrently with a domain switch and derives the target address from the attached domain. A stale domain read across a direct paging-to-identity or identity-to-paging transition can select the wrong addressing mode, so reject these transitions while IRQs remain allocated. Keep the blocking domain available as an immediate fail-stop mode. Since it does not retain the previous translation mode, transitions through it cannot be checked reliably and still require callers to quiesce MSI state. Paging-to-paging replacement remains supported because the new domain's MSI IOVA table is prepared before attachment. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu-ir.c | 38 ++++++++++++++++++++++++++++++++++ drivers/iommu/riscv/iommu.c | 9 ++++++++ drivers/iommu/riscv/iommu.h | 6 ++++++ 3 files changed, 53 insertions(+) diff --git a/drivers/iommu/riscv/iommu-ir.c b/drivers/iommu/riscv/iommu-ir.c index 5718f90affd6..f61b65f29888 100644 --- a/drivers/iommu/riscv/iommu-ir.c +++ b/drivers/iommu/riscv/iommu-ir.c @@ -278,6 +278,44 @@ void riscv_iommu_ir_irq_domain_remove(struct device *d= ev, struct riscv_iommu_inf irq_domain_free_fwnode(fn); } =20 +int riscv_iommu_ir_check_attach_paging_domain(struct iommu_domain *iommu_d= omain, + struct device *dev, + struct iommu_domain *old) +{ + struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); + + /* + * IOMMU_DOMAIN_BLOCKED is intentionally not checked. The immediate old + * domain does not reveal whether BLOCKED was entered from identity or + * paging, so rejecting it would also reject valid same-mode restores. + * IDENTITY -> BLOCKED -> PAGING can therefore bypass this check; callers + * must quiesce and tear down MSIs before making such a change. + */ + if (old && old->type =3D=3D IOMMU_DOMAIN_IDENTITY && info->nr_irqs) + return -EBUSY; + + return 0; +} + +int riscv_iommu_ir_check_attach_identity_domain(struct iommu_domain *iommu= _domain, + struct device *dev, + struct iommu_domain *old) +{ + struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); + + /* + * IOMMU_DOMAIN_BLOCKED is intentionally not checked. The immediate old + * domain does not reveal whether BLOCKED was entered from identity or + * paging, so rejecting it would also reject valid same-mode restores. + * PAGING -> BLOCKED -> IDENTITY can therefore bypass this check; callers + * must quiesce and tear down MSIs before making such a change. + */ + if (old && (old->type & __IOMMU_DOMAIN_PAGING) && info->nr_irqs) + return -EBUSY; + + return 0; +} + int riscv_iommu_ir_attach_paging_domain(struct iommu_domain *iommu_domain,= struct device *dev, struct iommu_domain *old) { diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 1a30bac88101..22cccc69bd2c 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1280,6 +1280,10 @@ static int riscv_iommu_attach_paging_domain(struct i= ommu_domain *iommu_domain, u64 fsc, ta; int ret; =20 + ret =3D riscv_iommu_ir_check_attach_paging_domain(iommu_domain, dev, old); + if (ret) + return ret; + pt_iommu_riscv_64_hw_info(&domain->riscvpt, &pt_info); =20 if (!riscv_iommu_pt_supported(iommu, pt_info.fsc_iosatp_mode)) @@ -1398,6 +1402,11 @@ static int riscv_iommu_attach_identity_domain(struct= iommu_domain *iommu_domain, { struct riscv_iommu_device *iommu =3D dev_to_iommu(dev); struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); + int ret; + + ret =3D riscv_iommu_ir_check_attach_identity_domain(iommu_domain, dev, ol= d); + if (ret) + return ret; =20 riscv_iommu_iodir_update(iommu, dev, RISCV_IOMMU_FSC_BARE, RISCV_IOMMU_PC= _TA_V); riscv_iommu_bond_unlink(old, dev); diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index 24006c1c1722..19e2c0f29301 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -103,6 +103,12 @@ struct irq_domain *riscv_iommu_ir_irq_domain_create(st= ruct device *dev, struct riscv_iommu_info *info); void riscv_iommu_ir_irq_domain_publish(struct device *dev); void riscv_iommu_ir_irq_domain_remove(struct device *dev, struct riscv_iom= mu_info *info); +int riscv_iommu_ir_check_attach_paging_domain(struct iommu_domain *iommu_d= omain, + struct device *dev, + struct iommu_domain *old); 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charset="utf-8" Translate composed IMSIC target addresses through the attached paging domain's pre-mapped IOVA table. This keeps affinity updates on the interrupt hierarchy while directing device MSI writes through the IOMMU. MSI composition may run in atomic context, so publish each fully built table with release ordering and consume it with acquire ordering under RCU. This permits lockless lookup without exposing incomplete table state. When no translated table is available, retain the physical IMSIC target for domains that do not use MSI address translation. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu-ir.c | 41 +++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/riscv/iommu-ir.c b/drivers/iommu/riscv/iommu-ir.c index f61b65f29888..dacaefa62859 100644 --- a/drivers/iommu/riscv/iommu-ir.c +++ b/drivers/iommu/riscv/iommu-ir.c @@ -99,7 +99,8 @@ static int riscv_iommu_ir_build_msi_iova(struct riscv_iom= mu_domain *domain, stru } } =20 - domain->msi_iova =3D msi_iova; + /* Pair with smp_load_acquire() in riscv_iommu_ir_compose_msi_msg() */ + smp_store_release(&domain->msi_iova, msi_iova); =20 return 0; =20 @@ -108,12 +109,50 @@ static int riscv_iommu_ir_build_msi_iova(struct riscv= _iommu_domain *domain, stru return ret; } =20 +static void riscv_iommu_ir_compose_msi_msg(struct irq_data *data, struct m= si_msg *msg) +{ + struct riscv_iommu_info *info =3D data->domain->host_data; + struct riscv_iommu_domain *domain; + dma_addr_t *msi_iova; + struct msi_desc *desc; + phys_addr_t pa; + size_t idx; + + BUG_ON(irq_chip_compose_msi_msg(data->parent_data, msg)); + + desc =3D irq_data_get_msi_desc(data); + if (WARN_ON_ONCE(!desc)) + return; + + guard(rcu)(); + + domain =3D rcu_dereference(info->domain); + if (!domain) { + msi_desc_set_iommu_msi_iova(desc, 0, 0); + return; + } + + /* Pair with smp_store_release() in riscv_iommu_ir_build_msi_iova() */ + msi_iova =3D smp_load_acquire(&domain->msi_iova); + if (!msi_iova) { + msi_desc_set_iommu_msi_iova(desc, 0, 0); + return; + } + + pa =3D ((u64)msg->address_hi << 32) | msg->address_lo; + idx =3D riscv_iommu_ir_msi_iova_idx(pa); + + msi_desc_set_iommu_msi_iova(desc, msi_iova[idx], IMSIC_MMIO_PAGE_SHIFT); + msi_msg_set_addr(desc, msg, pa); +} + static struct irq_chip riscv_iommu_ir_irq_chip =3D { .name =3D "IOMMU-IR", .irq_ack =3D irq_chip_ack_parent, .irq_mask =3D irq_chip_mask_parent, .irq_unmask =3D irq_chip_unmask_parent, .irq_set_affinity =3D irq_chip_set_affinity_parent, + .irq_compose_msi_msg =3D riscv_iommu_ir_compose_msi_msg, }; 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charset="utf-8" From: Tomasz Jeznach Enable IOMMU_DMA for 64-bit RISC-V now that the RISC-V IOMMU driver supports MSI remapping. Signed-off-by: Tomasz Jeznach Signed-off-by: Andrew Jones --- drivers/iommu/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index 6e07bd69467a..1c9f2ad10f36 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -151,7 +151,7 @@ config OF_IOMMU =20 # IOMMU-agnostic DMA-mapping layer config IOMMU_DMA - def_bool ARM64 || X86 || S390 + def_bool ARM64 || X86 || S390 || (RISCV && 64BIT) select DMA_OPS_HELPERS select IOMMU_API select IOMMU_IOVA --=20 2.43.0 From nobody Mon Sep 28 14:47:12 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 495B348CD48 for ; Thu, 20 Aug 2026 21:42:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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charset="utf-8" VFIO and iommufd require IOMMU_CAP_CACHE_COHERENCY because they use IOMMU_CACHE mappings and have no userspace cache-maintenance path. RISC-V page tables preserve physical memory attributes for IOMMU_CACHE mappings. Svpbmt marks mappings without IOMMU_CACHE as non-cacheable, but preserving physical attributes cannot make a noncoherent device path coherent. Report the capability only for devices marked DMA coherent. This limits userspace assignment to paths that can honor cacheable mappings. Signed-off-by: Andrew Jones Reviewed-by: Jason Gunthorpe --- drivers/iommu/riscv/iommu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 22cccc69bd2c..161093b1d9c5 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -1429,6 +1430,16 @@ static struct iommu_group *riscv_iommu_device_group(= struct device *dev) return generic_device_group(dev); } =20 +static bool riscv_iommu_capable(struct device *dev, enum iommu_cap cap) +{ + switch (cap) { + case IOMMU_CAP_CACHE_COHERENCY: + return dev_is_dma_coherent(dev); + default: + return false; + } +} + static int riscv_iommu_of_xlate(struct device *dev, const struct of_phandl= e_args *args) { return iommu_fwspec_add_ids(dev, args->args, 1); @@ -1520,6 +1531,7 @@ static void riscv_iommu_get_resv_regions(struct devic= e *dev, struct list_head *h =20 static const struct iommu_ops riscv_iommu_ops =3D { .of_xlate =3D riscv_iommu_of_xlate, + .capable =3D riscv_iommu_capable, .identity_domain =3D &riscv_iommu_identity_domain, .blocked_domain =3D &riscv_iommu_blocking_domain, .release_domain =3D &riscv_iommu_blocking_domain, --=20 2.43.0 From nobody Mon Sep 28 14:47:12 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63B3E48CD46 for ; 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charset="utf-8" From: Tomasz Jeznach Enable VFIO support on RISC-V architecture, now that the RISC-V IOMMU driver reports the IOMMU_CAP_CACHE_COHERENCY capability VFIO_TYPE1 and iommufd both require before allowing a device to be bound. Signed-off-by: Tomasz Jeznach Signed-off-by: Andrew Jones Reviewed-by: Nutty Liu --- drivers/vfio/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/vfio/Kconfig b/drivers/vfio/Kconfig index ceae52fd7586..ad62205b4e45 100644 --- a/drivers/vfio/Kconfig +++ b/drivers/vfio/Kconfig @@ -39,7 +39,7 @@ config VFIO_GROUP =20 config VFIO_CONTAINER bool "Support for the VFIO container /dev/vfio/vfio" - select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64) + select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64 || RISCV) depends on VFIO_GROUP default y help --=20 2.43.0 From nobody Mon Sep 28 14:47:12 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0910848F83E for ; Thu, 20 Aug 2026 21:42:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" From: Tomasz Jeznach Enable KVM/VFIO support on RISC-V architecture, now that VFIO device assignment is available on RISC-V through VFIO_IOMMU_TYPE1, so a RISC-V KVM guest can be notified about VFIO-assigned devices. Signed-off-by: Tomasz Jeznach Signed-off-by: Andrew Jones Reviewed-by: Nutty Liu --- arch/riscv/kvm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/kvm/Kconfig b/arch/riscv/kvm/Kconfig index ec2cee0a39e0..49179aae9504 100644 --- a/arch/riscv/kvm/Kconfig +++ b/arch/riscv/kvm/Kconfig @@ -29,6 +29,7 @@ config KVM select KVM_GENERIC_DIRTYLOG_READ_PROTECT select KVM_GENERIC_HARDWARE_ENABLING select KVM_MMIO + select KVM_VFIO select VIRT_XFER_TO_GUEST_WORK select SCHED_INFO select GUEST_PERF_EVENTS if PERF_EVENTS --=20 2.43.0 From nobody Mon Sep 28 14:47:12 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A88948F846 for ; Thu, 20 Aug 2026 21:42:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; 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charset="utf-8" Enable iommufd and VFIO in the default configuration now that the RISC-V IOMMU provides the DMA and MSI remapping needed for userspace device access, including assignment to virtual machines. Signed-off-by: Andrew Jones --- arch/riscv/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index ed605b5e3162..bae9a0f32f89 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -249,6 +249,10 @@ CONFIG_DMADEVICES=3Dy CONFIG_DMA_SUN6I=3Dm CONFIG_DW_AXI_DMAC=3Dy CONFIG_MMP_PDMA=3Dm +CONFIG_IOMMUFD=3Dm +CONFIG_VFIO_DEVICE_CDEV=3Dy +CONFIG_VFIO=3Dm +CONFIG_VFIO_PCI=3Dm CONFIG_VIRTIO_PCI=3Dy CONFIG_VIRTIO_BALLOON=3Dy CONFIG_VIRTIO_INPUT=3Dy --=20 2.43.0 From nobody Mon Sep 28 14:47:12 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8FA414908CD for ; Thu, 20 Aug 2026 21:42:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; 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charset="utf-8" The generic VFIO selftests, including iommufd coverage, require no RISC-V-specific source changes. Include riscv64 in their build list. Signed-off-by: Andrew Jones --- tools/testing/selftests/vfio/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/testing/selftests/vfio/Makefile b/tools/testing/selftest= s/vfio/Makefile index 2c32c48db509..c6c5764185ba 100644 --- a/tools/testing/selftests/vfio/Makefile +++ b/tools/testing/selftests/vfio/Makefile @@ -1,6 +1,6 @@ ARCH ?=3D $(shell uname -m) =20 -ifeq (,$(filter $(ARCH),aarch64 arm64 x86 x86_64)) +ifeq (,$(filter $(ARCH),aarch64 arm64 x86 x86_64 riscv64)) # Do nothing on unsupported architectures include ../lib.mk else --=20 2.43.0