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[79.54.86.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-482b14c3775sm10021606f8f.26.2026.08.20.02.17.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2026 02:17:07 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: alexandre.torgue@foss.st.com, francesco.utel@engicam.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, domenico.acri@engicam.com, michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Christophe Parant , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v8 01/16] dt-bindings: arm: stm32: support Engicam MicroGEA-STM32MP257D-RMM board Date: Thu, 20 Aug 2026 11:12:09 +0200 Message-ID: <20260820091652.43541-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> References: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add devicetree bindings for Engicam MicroGEA-STM32MP257D-RMM board based on the Engicam MicroGEA-STM32MP257 SoM (System-on-Module). The use of an enum for a single element is justified by the future addition of other boards based on the same SoM. Signed-off-by: Dario Binacchi Acked-by: Conor Dooley --- Changes in v8: - Rename engicam,microgea-stm32mp257-rmm to engicam,microgea-stm32mp257d-rmm Changes in v2: - Add Acked-by of Conor Dooley for patch 0/1 "dt-bindings: arm: stm32: support Engicam MicroGEA-STM32MP257-RMM board" Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Docum= entation/devicetree/bindings/arm/stm32/stm32.yaml index c6af3a46364f..3ed797ee7cfe 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -203,6 +203,13 @@ properties: - st,stm32mp257f-ev1 - const: st,stm32mp257 =20 + - description: Engicam MicroGEA STM32MP257 SoM based Boards + items: + - enum: + - engicam,microgea-stm32mp257d-rmm + - const: engicam,microgea-stm32mp257 + - const: st,stm32mp257 + - description: ST STM32MP235 based Boards items: - enum: --=20 2.43.0 From nobody Mon Sep 28 17:48:33 2026 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66F9F3E51CB for ; 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[79.54.86.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-482b14c3775sm10021606f8f.26.2026.08.20.02.17.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2026 02:17:09 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: alexandre.torgue@foss.st.com, francesco.utel@engicam.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, domenico.acri@engicam.com, michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v8 02/16] arm64: dts: st: add power-domains to sdmmc1 on stm32mp231 Date: Thu, 20 Aug 2026 11:12:10 +0200 Message-ID: <20260820091652.43541-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> References: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The sdmmc1 node was introduced early in the SoC bring-up before power domains were systematically mapped. Add the missing power-domains property to align it with the rest of the peripheral nodes. Signed-off-by: Dario Binacchi --- (no changes since v5) Changes in v5: - Added in version 5. Suggested by Sashiko. arch/arm64/boot/dts/st/stm32mp231.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/s= t/stm32mp231.dtsi index 9e1d240888ff..0feb8943efae 100644 --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -727,6 +727,7 @@ sdmmc1: mmc@48220000 { cap-mmc-highspeed; max-frequency =3D <120000000>; access-controllers =3D <&rifsc 76>; + power-domains =3D <&cluster_pd>; status =3D "disabled"; }; =20 --=20 2.43.0 From nobody Mon Sep 28 17:48:33 2026 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12804223DE5 for ; Thu, 20 Aug 2026 09:17:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787217436; cv=none; b=GHy+v69hSq/U/QTdlWmwMdyaSoRYG+WcMHqsgJiAumNug213KJGcQBCcBta30jFQ0Af/vbQlqzRFereH3dMMQ8xyMH9EjS4gYR5T9Abqy+g8PlCvgR+F/cbRdaddMZUIGienF9GMeWa/LdhafEnZ/EydcMJtCVEsMZGc550rPgE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787217436; c=relaxed/simple; bh=SRq4aV3Vv1KtanwaZu/HUbm5QTW8rISjxiq71Wm2JKY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RenjA60gJV+VU02ytBAipk0fJ8Ub6mJ4pWOKlczWhyvUDNtlGKFn1PIn6cUkRP0YnPPsWvFFNAb4sxnvl+aVM6JMAJtTHo6ufz9YeVHKhrNvms0NjdzjWPtdn4J6/7RXHSiSM3YgfrhGzycfvVRnNXAYl6jP6Viv1e8LOH4n7Lo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=hNLv2i+H; arc=none smtp.client-ip=209.85.221.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="hNLv2i+H" Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-47f84023916so1905921f8f.3 for ; Thu, 20 Aug 2026 02:17:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1787217433; x=1787822233; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=kjf+9zwLvFnbMj2uY67jnA57NYs5qvgfofKcphxJQbw=; b=hNLv2i+HLH7fNN+PX+TuPAsqrvdW3a3JIPDr2ReTOmaGdnOmOaQfIzvA7nXEQeiTQm 8UvbuxBDaCL+YSR4m/sQ2tEeMJ6sg46D3REwtyaI6vU0lJK83Vu4LqAFRvYfjNKac/dz QtmgpY1So80ToeVvT4JF+DKZl3oNfWQ0l0H0w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787217433; x=1787822233; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=kjf+9zwLvFnbMj2uY67jnA57NYs5qvgfofKcphxJQbw=; b=NfR6XGZHgqtzoR4SLt4IakoXpT2Lkk6mW1YIVk0PBHpfMO8W+Lpp9fkFxNPqdNqXsL zLVWdTkQYjxekpNb+RISzaqrooQDEoIlPhcf4L4a8uc6iTFQRAw7nB4nFTprDfUfAjRB sgwoimxUVV7ndYgi0x2kH6fnGIANvB/9mOvMUHcVCAqLFdFJ7dpkjSgD9RdxSn6nww3j 09nCcYLdc7wQ1iTIsMmRJbTzIN1Z560ytmcQFnwoIAeTBX94VpnozlOXTHztcVoC8ECw DHHtydBlsYUaRQ0IH2Zq6I5An4JDfFKHEviq/zXAkWz74uHPo3LOzQ3I+8m/vAj0O3ve djMA== X-Gm-Message-State: AFuF++n/hGwa4RUkLnckE1vrMqhku0Za7R0HEst7VN04aL26xBNQ6X4a oKXDh3ywMOqbWB0Z8Tl1emZx/dZJ+4OjZyYEQgmXazIpLYeXr1iqH8OuUlBZtD6fye6g7oy6vuT GQq6iK/Q= X-Gm-Gg: AR+sD12/J8+z38huoz0Yr6Gs7iDRuqHRBcKIl5oLYWXNf8Oo2ZuIW1u9rOmO5TMV3Hy CcNWjFkkHT3kvimxEoPTlw5uI77XhWRPCie48ZtScQtMe8McpdxM8PBSADb5dnKRw/39/M+3ttk 6TxesQk5LmLfBEpXFYVw5GzkMQBcc+HqMAkp0yivvWKzCheu2xElz6bFEsAxvPhymGZKxdFSFZ6 VhYcKqrhE7OqpyQUuM45nC7YytCkXqSL+IC7XKn1nXXgPKHP0O/PgfmEfe6Kk/x6Go9hEb+AYM1 MLsM7NRD9mKKmA/bb/IMuWN9x+6ZrN4jLwA3agLirf+CbZNRwtIcbKoirZoY4Y/pbao5qGXKu7K 9JVerf/E0O57hbpYMugm6mQRdsCpZi9gQh9w+VAKcbXd8T6Y19RFqRRLo7swl/RFwtfYCno1zJ+ DXoTVZsSeGO2df/ciilfdy+8ynWF8aewZ5xYqdLJ52Nahhh/i9ds3JMY59FDODFqGro7coH7CQd R6O4qh3XEiIsJdIBPVr+vWMqWJJ2mQGMBcsF5Q5lDrkra6dgeMCtVeQtBgS6eJn8ciK5sfcycu8 VCxX5TDenMug8vm2DYJ8t5d9OF9gQbTBAlqH8CZLw20LXzgajGB7CGPlbIZTsvCcQ4VCXo5imA= = X-Received: by 2002:a05:6000:2881:b0:47f:97e9:fe60 with SMTP id ffacd0b85a97d-482b1fd9579mr19387927f8f.15.1787217433214; Thu, 20 Aug 2026 02:17:13 -0700 (PDT) Received: from dario-ThinkPad-P14s-Gen-5.homenet.telecomitalia.it (host-79-54-86-139.retail.telecomitalia.it. [79.54.86.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-482b14c3775sm10021606f8f.26.2026.08.20.02.17.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2026 02:17:12 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: alexandre.torgue@foss.st.com, francesco.utel@engicam.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, domenico.acri@engicam.com, michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v8 03/16] arm64: dts: st: add power-domains to sdmmc1 on stm32mp251 Date: Thu, 20 Aug 2026 11:12:11 +0200 Message-ID: <20260820091652.43541-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> References: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The sdmmc1 node was introduced early in the SoC bring-up before power domains were systematically mapped. Add the missing power-domains property to align it with the rest of the peripheral nodes. Signed-off-by: Dario Binacchi --- (no changes since v5) Changes in v5: - Added in version 5. Suggested by Sashiko. arch/arm64/boot/dts/st/stm32mp251.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 9c63fdb5a885..ae36d703532c 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1664,6 +1664,7 @@ sdmmc1: mmc@48220000 { cap-mmc-highspeed; max-frequency =3D <120000000>; access-controllers =3D <&rifsc 76>; + power-domains =3D <&CLUSTER_PD>; status =3D "disabled"; }; =20 --=20 2.43.0 From nobody Mon Sep 28 17:48:33 2026 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FD303E6394 for ; Thu, 20 Aug 2026 09:17:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787217439; cv=none; b=kGhOd1ZsBkPPo30NLtogoJ8spGAwuLnsuMcgEUfOIJyen0QoAXh+bnkXqzI7oBA/yV+5BJTgwOGT+U3uPxRUOBX30/0I1TES3iaIhVhoPhGEtcFZ4ZIMgDEq6fxQrXUOpZbbsyfunXpyItQBwkTHuKutKcZYdHOLYjqU3M0mIJM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787217439; c=relaxed/simple; bh=9IgDtyv6yAMUkWsg7RNaWcItxtFHo8kakpm/KHcWfnA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=l9cFB4WaVH0tzrIywWB6eVLmn2h/pWWZqeNTG9E4cPsx2K9Hbax5mJpIzBqTSYw3hKBpJwUtW38u09ssWXvJzJiD/HQpoA4vcpWeytLBWVFkekVuSr9tilo58MFxL4HuCL0yPjcbGL/sIlmTyL1Jk70awbDL/d7l1LjPHLtZHhg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=ii9ohhI9; arc=none smtp.client-ip=209.85.221.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="ii9ohhI9" Received: by mail-wr1-f46.google.com with SMTP id ffacd0b85a97d-47fd4531020so1211778f8f.3 for ; Thu, 20 Aug 2026 02:17:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1787217437; x=1787822237; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=fAmctwTyX9ptfNTsOcFrY+BzuI2WSByIHEJFFIRpN/Y=; b=ii9ohhI9dYIKqxMbQo/O858JaY6cYij70c8t7zY2mtHxu4QXxT9oFjB2fv3FuC4wBO JZ4I4EtcfivwdLVzKvLshjv4TqxGXSjt2LekdZgC5YvIqtvZGU7fzzfdeL6R5Z/ga0sR PJkvWEztlnaPmOJfbU7rGQ18NJVuDqGk3loEo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787217437; x=1787822237; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=fAmctwTyX9ptfNTsOcFrY+BzuI2WSByIHEJFFIRpN/Y=; b=bLSLMScAFSELKzF9Tsc19IEcyxZbrde8E7MZU4hQW+rT8xDoSuC5S6kIH0pSH3PBb0 WOk+dGCboBDX+1qt9xCx4AZIB8hNilnTDhViVex6ijxj5eAofwAoWLQtnoAmoeUap5zE jU1+VreDD+wbpGBVah19w4QrvyYJGVl0HIvTKEH/u5CpaBik3F03nR2kJCUSctX0mG3s jq4nyRenANbTSgpDarKeLv9T6H8Lbtv7HzQjCUHS5xTD/ZREJZ9HdMYkGSiqz6MKnAy4 kxbpXHJjRvjifk+vdBJv+km9iqSuGprlPzfcePwd+AD3DFobT/AMLeuOvwihAxi5mLJU 4srA== X-Gm-Message-State: AFuF++mp0PAWVWez4asDaqejBpQsC1mbO+iSE+5Y+jmFBSr5z2W7JND3 U21kknt8xt6vmEuru5VLbY+L3a6KkgMN2zd9n+i9287sR1rKUvbvEdaTtAYTb/a9/2YRzDV+4SU oLIdUTgg= X-Gm-Gg: AR+sD12oC4U0KDZYVXpS8gZI2dbD8Ge3GoTnSYP///7zBBfUvnaXZgwZMUlCVPfZBPX h1YlTuJt2sg/aQilomDAtKFrNJ68iug5dMIkBFHfXjKno7+CxaUYlsEF8i7IdK1wUivtzuMs/47 E2USiBwVDu550AuQxSN835AQHj7C1HDiBx2zA0IRveE79wh2xb+LNTFfcPssSeeCQxYIJ/2NSOI A+lpwUE//rU8b3Tv0UuypeuIuRtgoSTApism9HdAmQXSvvgGa2W0yuE7cH+TrRUqz+4JdEO9+Qy p9YICBoFW86yn+xIwxxnRXHVNanhOGywvLxD7Nml/y9wFajSM/We2cHXlRbA3MnL2MKt2uPuB6W EtJEY09CWJrl3hwUA1yA2KOzfqOgCFPyDLnfg+RrCb8NvBu5fLu90J9B1pKecM3xwJKkrQ5R9T+ VrJoYFJWTvVaixey/0JoB+yd10/MZ4TqRQfY8u6yNPzdnuI4EQKg2dxhoZPCndwbaOUuzvfQGJo SVAFgyohKPLJz7PN87OVp/p+bE7bB78subKOnnjNOk5zDHH3HLn/MWGY6KzEJsl60UrsQscWoJi /4RuNXcFaq1YCcJzBgdTyme7Orl/czlFrvAOsZcwIz6LJIvlCdw3ydINJDtpSw== X-Received: by 2002:a05:6000:490c:b0:481:56ec:b422 with SMTP id ffacd0b85a97d-482b1eaa195mr20533368f8f.9.1787217436548; Thu, 20 Aug 2026 02:17:16 -0700 (PDT) Received: from dario-ThinkPad-P14s-Gen-5.homenet.telecomitalia.it (host-79-54-86-139.retail.telecomitalia.it. [79.54.86.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-482b14c3775sm10021606f8f.26.2026.08.20.02.17.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2026 02:17:16 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: alexandre.torgue@foss.st.com, francesco.utel@engicam.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, domenico.acri@engicam.com, michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v8 04/16] arm64: dts: st: add SDMMC2 support on stm32mp25 Date: Thu, 20 Aug 2026 11:12:12 +0200 Message-ID: <20260820091652.43541-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> References: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SDMMC2 controller supports SD cards, eMMC memories and SDIO devices. Signed-off-by: Dario Binacchi --- (no changes since v3) Changes in v3: - Add power-domains property. Suggested by Sashiko. arch/arm64/boot/dts/st/stm32mp251.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index ae36d703532c..44938c036e30 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1668,6 +1668,22 @@ sdmmc1: mmc@48220000 { status =3D "disabled"; }; =20 + sdmmc2: mmc@48230000 { + compatible =3D "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid =3D <0x00353180>; + reg =3D <0x48230000 0x400>, <0x44230800 0x8>; + interrupts =3D ; + clocks =3D <&rcc CK_KER_SDMMC2>; + clock-names =3D "apb_pclk"; + resets =3D <&rcc SDMMC2_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency =3D <120000000>; + access-controllers =3D <&rifsc 77>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + }; + ethernet1: ethernet@482c0000 { compatible =3D "st,stm32mp25-dwmac", "snps,dwmac-5.20"; reg =3D <0x482c0000 0x4000>; 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[79.54.86.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-482b14c3775sm10021606f8f.26.2026.08.20.02.17.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2026 02:17:18 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: alexandre.torgue@foss.st.com, francesco.utel@engicam.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, domenico.acri@engicam.com, michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v8 05/16] arm64: dts: st: add CAN1 support on stm32mp25 Date: Thu, 20 Aug 2026 11:12:13 +0200 Message-ID: <20260820091652.43541-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> References: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The controller is compliant with ISO 11898-1: 2015 (CAN protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0. Signed-off-by: Dario Binacchi --- (no changes since v2) Changes in v2: - Add resets property to dts CAN node. Suggested by Sashiko. arch/arm64/boot/dts/st/stm32mp253.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi b/arch/arm64/boot/dts/s= t/stm32mp253.dtsi index eeceb086252b..7e82f01fdc10 100644 --- a/arch/arm64/boot/dts/st/stm32mp253.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi @@ -43,6 +43,22 @@ &optee { }; =20 &rifsc { + m_can1: can@402d0000 { + compatible =3D "bosch,m_can"; + reg =3D <0x402d0000 0x400>, <0x40310000 0xd50>; + reg-names =3D "m_can", "message_ram"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + clocks =3D <&rcc CK_BUS_FDCAN>, <&rcc CK_KER_FDCAN>; + clock-names =3D "hclk", "cclk"; + resets =3D <&rcc FDCAN_R>; + bosch,mram-cfg =3D <0x0 0 0 32 0 0 2 2>; + access-controllers =3D <&rifsc 56>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + }; + ethernet2: ethernet@482d0000 { compatible =3D "st,stm32mp25-dwmac", "snps,dwmac-5.20"; reg =3D <0x482d0000 0x4000>; --=20 2.43.0 From nobody Mon Sep 28 17:48:33 2026 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A8583EB80E for ; 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[79.54.86.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-482b14c3775sm10021606f8f.26.2026.08.20.02.17.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2026 02:17:20 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: alexandre.torgue@foss.st.com, francesco.utel@engicam.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, domenico.acri@engicam.com, michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v8 06/16] arm64: dts: st: add i2c1 pins for stm32mp25 Date: Thu, 20 Aug 2026 11:12:14 +0200 Message-ID: <20260820091652.43541-7-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> References: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the i2c1 pins used on MicroGEA-STM32MP257D-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index 456ece7f8ebc..db485b9ed904 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -203,6 +203,25 @@ pins { }; }; =20 + /omit-if-no-ref/ + i2c1_pins_a: i2c1-0 { + pins { + pinmux =3D , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate =3D <0>; + }; + }; + + /omit-if-no-ref/ + i2c1_sleep_pins_a: i2c1-sleep-0 { + pins { + pinmux =3D , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; + }; + /omit-if-no-ref/ i2c2_pins_a: i2c2-0 { pins { --=20 2.43.0 From nobody Mon Sep 28 17:48:33 2026 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D74353E7BBF for ; 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[79.54.86.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-482b14c3775sm10021606f8f.26.2026.08.20.02.17.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2026 02:17:22 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: alexandre.torgue@foss.st.com, francesco.utel@engicam.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, domenico.acri@engicam.com, michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v8 07/16] arm64: dts: st: add ltdc pins for stm32mp25 Date: Thu, 20 Aug 2026 11:12:15 +0200 Message-ID: <20260820091652.43541-8-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> References: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the LTDC pins used on MicroGEA-STM32MP257D-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v5) Changes in v5: - Increase slew-rate to <1> to support the 27 MHz pixel clock and prevent timing violations. Suggested by Sashiko arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index db485b9ed904..50f454630cf2 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -260,6 +260,77 @@ pins { }; }; =20 + /omit-if-no-ref/ + ltdc_pins_a: ltdc-0 { + pins { + pinmux =3D , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + bias-disable; + drive-push-pull; + slew-rate =3D <1>; + }; + }; + + /omit-if-no-ref/ + ltdc_sleep_pins_a: ltdc-sleep-0 { + pins { + pinmux =3D , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + }; + }; + /omit-if-no-ref/ ospi_port1_clk_pins_a: ospi-port1-clk-0 { pins { --=20 2.43.0 From nobody Mon Sep 28 17:48:33 2026 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 498203E9C0D for ; Thu, 20 Aug 2026 09:17:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[79.54.86.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-482b14c3775sm10021606f8f.26.2026.08.20.02.17.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2026 02:17:24 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: alexandre.torgue@foss.st.com, francesco.utel@engicam.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, domenico.acri@engicam.com, michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v8 08/16] arm64: dts: st: add can1 pins for stm32mp25 Date: Thu, 20 Aug 2026 11:12:16 +0200 Message-ID: <20260820091652.43541-9-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> References: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the can1 pins used on MicroGEA-STM32MP257D-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index 50f454630cf2..6482dd47e977 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -331,6 +331,28 @@ pins { }; }; =20 + /omit-if-no-ref/ + m_can1_pins_a: m-can1-0 { + pins1 { + pinmux =3D ; /* CAN1_TX */ + slew-rate =3D <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux =3D ; /* CAN1_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + m_can1_sleep_pins_a: m-can1-sleep-0 { + pins { + pinmux =3D , /* CAN1_TX */ + ; /* CAN1_RX */ + }; + }; + /omit-if-no-ref/ ospi_port1_clk_pins_a: ospi-port1-clk-0 { pins { --=20 2.43.0 From nobody Mon Sep 28 17:48:33 2026 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3FE03EFD02 for ; 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[79.54.86.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-482b14c3775sm10021606f8f.26.2026.08.20.02.17.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2026 02:17:28 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: alexandre.torgue@foss.st.com, francesco.utel@engicam.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, domenico.acri@engicam.com, michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v8 09/16] arm64: dts: st: add pwm2/pwm4 pins for stm32mp25 Date: Thu, 20 Aug 2026 11:12:17 +0200 Message-ID: <20260820091652.43541-10-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> References: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the pwm2 and pwm4 pins used on MicroGEA-STM32MP257D-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index 6482dd47e977..695c9d771853 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -433,6 +433,23 @@ pins { }; }; =20 + /omit-if-no-ref/ + pwm2_pins_a: pwm2-0 { + pins { + pinmux =3D ; /* TIM2_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate =3D <0>; + }; + }; + + /omit-if-no-ref/ + pwm2_sleep_pins_a: pwm2-sleep-0 { + pins { + pinmux =3D ; /* TIM2_CH1 */ + }; + }; + /omit-if-no-ref/ pwm3_pins_a: pwm3-0 { pins { @@ -450,6 +467,23 @@ pins { }; }; =20 + /omit-if-no-ref/ + pwm4_pins_a: pwm4-0 { + pins { + pinmux =3D ; /* TIM4_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate =3D <0>; + }; + }; + + /omit-if-no-ref/ + pwm4_sleep_pins_a: pwm4-sleep-0 { + pins { + pinmux =3D ; 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[79.54.86.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-482b14c3775sm10021606f8f.26.2026.08.20.02.17.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2026 02:17:32 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: alexandre.torgue@foss.st.com, francesco.utel@engicam.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, domenico.acri@engicam.com, michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Olivier Moysan , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v8 10/16] arm64: dts: st: add sai1 pins for stm32mp25 Date: Thu, 20 Aug 2026 11:12:18 +0200 Message-ID: <20260820091652.43541-11-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> References: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the sai1 pins used on MicroGEA-STM32MP257D-RMM board. Signed-off-by: Dario Binacchi Reviewed-by: Olivier Moysan --- (no changes since v7) Changes in v7: - Add Reviewed-by tag of Olivier Moysan arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index 695c9d771853..002fbc724b9d 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -520,6 +520,51 @@ pins { }; }; =20 + /omit-if-no-ref/ + sai1a_pins_a: sai1a-0 { + pins1 { + pinmux =3D , /* SAI1_SD_A */ + , /* SAI1_FS_A */ + ; /* SAI1_SCK_A */ + bias-disable; + drive-push-pull; + slew-rate =3D <1>; + }; + pins2 { + pinmux =3D ; /* SAI1_MCLK_A */ + bias-disable; + drive-push-pull; + slew-rate =3D <2>; + }; + }; + + /omit-if-no-ref/ + sai1a_sleep_pins_a: sai1a-sleep-0 { + pins { + pinmux =3D , /* SAI1_SD_A */ + , /* SAI1_FS_A */ + , /* SAI1_SCK_A */ + ; /* SAI1_MCLK_A */ + }; + }; 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[79.54.86.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-482b14c3775sm10021606f8f.26.2026.08.20.02.17.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2026 02:17:35 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: alexandre.torgue@foss.st.com, francesco.utel@engicam.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, domenico.acri@engicam.com, michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v8 11/16] arm64: dts: st: add sdmmc2 pins for stm32mp25 Date: Thu, 20 Aug 2026 11:12:19 +0200 Message-ID: <20260820091652.43541-12-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> References: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the sdmmc2 pins used on MicroGEA-STM32MP257D-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v5) Changes in v5: - Change SDMMC2_CK pin bias from pull-up to bias-disable to avoid signal integrity issues on the clock line. Suggested by Sashiko arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index 002fbc724b9d..c816a6aece47 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -622,6 +622,86 @@ pins { }; }; =20 + /omit-if-no-ref/ + sdmmc2_b4_pins_a: sdmmc2-b4-0 { + pins1 { + pinmux =3D , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + ; /* SDMMC2_CMD */ + slew-rate =3D <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux =3D ; /* SDMMC2_CK */ + slew-rate =3D <2>; + drive-push-pull; + bias-disable; + }; + }; + + /omit-if-no-ref/ + sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { + pins1 { + pinmux =3D , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + ; /* SDMMC2_D3 */ + slew-rate =3D <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux =3D ; /* SDMMC2_CK */ + slew-rate =3D <2>; + drive-push-pull; + bias-disable; + }; + pins3 { + pinmux =3D ; /* SDMMC2_CMD */ + slew-rate =3D <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { + pins { + pinmux =3D , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_CK */ + ; /* SDMMC2_CMD */ + }; + }; + + /omit-if-no-ref/ + sdmmc2_d47_pins_a: sdmmc2-d47-0 { + pins { + pinmux =3D , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + slew-rate =3D <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { + pins { + pinmux =3D , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + /omit-if-no-ref/ spi3_pins_a: spi3-0 { pins1 { --=20 2.43.0 From nobody Mon Sep 28 17:48:33 2026 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57CE93E834D for ; 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[79.54.86.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-482b14c3775sm10021606f8f.26.2026.08.20.02.17.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2026 02:17:37 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: alexandre.torgue@foss.st.com, francesco.utel@engicam.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, domenico.acri@engicam.com, michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v8 12/16] arm64: dts: st: add spi1 pins for stm32mp25 Date: Thu, 20 Aug 2026 11:12:20 +0200 Message-ID: <20260820091652.43541-13-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> References: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the spi1 pins used on MicroGEA-STM32MP257D-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index c816a6aece47..4e570e2e5157 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -702,6 +702,30 @@ pins { }; }; =20 + /omit-if-no-ref/ + spi1_pins_a: spi1-0 { + pins1 { + pinmux =3D , /* SPI1_SCK */ + ; /* SPI1_MOSI */ + drive-push-pull; + bias-disable; + slew-rate =3D <1>; + }; + pins2 { + pinmux =3D ; /* SPI1_MISO */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + spi1_sleep_pins_a: spi1-sleep-0 { + pins1 { + pinmux =3D , /* SPI1_SCK */ + , /* SPI1_MOSI */ + ; /* SPI1_MISO */ + }; + }; + /omit-if-no-ref/ spi3_pins_a: spi3-0 { pins1 { --=20 2.43.0 From nobody Mon Sep 28 17:48:33 2026 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E0F53F12E3 for ; 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[79.54.86.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-482b14c3775sm10021606f8f.26.2026.08.20.02.17.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2026 02:17:39 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: alexandre.torgue@foss.st.com, francesco.utel@engicam.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, domenico.acri@engicam.com, michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v8 13/16] arm64: dts: st: add usart1 pins for stm32mp25 Date: Thu, 20 Aug 2026 11:12:21 +0200 Message-ID: <20260820091652.43541-14-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> References: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the usart1 pins used on MicroGEA-STM32MP257D-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index 4e570e2e5157..d515e44832d7 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -766,6 +766,39 @@ pins { }; }; =20 + /omit-if-no-ref/ + usart1_pins_b: usart1-1 { + pins1 { + pinmux =3D ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate =3D <0>; + }; + pins2 { + pinmux =3D ; /* USART1_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + usart1_idle_pins_b: usart1-idle-1 { + pins1 { + pinmux =3D ; /* USART1_TX */ + }; + pins2 { + pinmux =3D ; /* USART1_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + usart1_sleep_pins_b: usart1-sleep-1 { + pins { + pinmux =3D , /* USART1_TX */ + ; /* USART1_RX */ + }; + }; + /omit-if-no-ref/ usart2_pins_a: usart2-0 { pins1 { --=20 2.43.0 From nobody Mon Sep 28 17:48:33 2026 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D21DE3F0AB8 for ; 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[79.54.86.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-482b14c3775sm10021606f8f.26.2026.08.20.02.17.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2026 02:17:42 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: alexandre.torgue@foss.st.com, francesco.utel@engicam.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, domenico.acri@engicam.com, michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v8 14/16] arm64: dts: st: support Engicam MicroGEA-STM32MP257 SoM Date: Thu, 20 Aug 2026 11:12:22 +0200 Message-ID: <20260820091652.43541-15-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> References: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support Engicam MicroGEA-STM32MP257 SoM with: - 8 GB eMMC Flash - 2 GB LPDDR4 DRAM The SoM also provides an Ethernet MAC, but Ethernet support is not enabled at this stage due to a known silicon limitation documented in [1]. This corresponds to section 2.21.2 ("ETH1 RMII mode could have CRC errors"), where CRC errors may occur in ETH1 RMII direct mode when directly connected to I/Os. The workaround requires use of the Ethernet switch (ETHSW), which introduces additional DT bindings and topology complexity. This is intended to be addressed in a separate patch series. [1] https://www.st.com/resource/en/errata_sheet/es0598-stm32mp23xx25xx-devi= ce-errata-stmicroelectronics.pdf Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - Drop inclusion of stm32mp25xf.dtsi, we are using stm32mp257d. Changes in v3: - Fix a typo in the URL .../dts/st/stm32mp257-engicam-microgea.dtsi | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi diff --git a/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi b/arch= /arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi new file mode 100644 index 000000000000..5b4287e86def --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026 Amarula Solutions, Dario Binacchi + * Copyright (C) 2026 Engicam srl + */ + +/dts-v1/; + +#include +#include "stm32mp257.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxai-pinctrl.dtsi" + +/ { + model =3D "Engicam MicroGEA STM32MP257 SoM"; + compatible =3D "engicam,microgea-stm32mp257", "st,stm32mp257"; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x80000000>; + }; +}; + +&scmi_regu { + scmi_vddio1: regulator@0 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + scmi_vddcore: regulator@b { + reg =3D ; + regulator-name =3D "vddcore"; + }; + scmi_v1v8: regulator@e { + reg =3D ; + regulator-name =3D "v1v8"; + }; + scmi_v3v3: regulator@10 { + reg =3D ; + regulator-name =3D "v3v3"; + }; + scmi_vdd3v3_usb: regulator@14 { + reg =3D ; + regulator-name =3D "vdd3v3_usb"; + }; +}; + +/* eMMC */ +&sdmmc2 { + pinctrl-names =3D "default", "opendrain", "sleep"; + pinctrl-0 =3D <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + pinctrl-1 =3D <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; + pinctrl-2 =3D <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width =3D <8>; + vmmc-supply =3D <&scmi_v3v3>; + vqmmc-supply =3D <&scmi_vddio2>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + status =3D "okay"; +}; --=20 2.43.0 From nobody Mon Sep 28 17:48:33 2026 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EAE203F2101 for ; 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[79.54.86.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-482b14c3775sm10021606f8f.26.2026.08.20.02.17.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2026 02:17:44 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: alexandre.torgue@foss.st.com, francesco.utel@engicam.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, domenico.acri@engicam.com, michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v8 15/16] arm64: dts: st: support Engicam MicroGEA-STM32MP257D-RMM board Date: Thu, 20 Aug 2026 11:12:23 +0200 Message-ID: <20260820091652.43541-16-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> References: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support for Engicam MicroGEA-STM32MP257D-RMM board with: - 8 GB eMMC Flash - 2 GB LPDDR4 DRAM - CAN - LEDs - LCD panel with touchscreen - Micro SD card connector - Audio codec - Buzzer Signed-off-by: Dario Binacchi --- Changes in v8: - Rename stm32mp257-engicam-microgea-rmm.dts to stm32mp257d-engicam-microge= a-rmm.dts and update the Makefile entry accordingly. - Rename the board compatible engicam,microgea-stm32mp257-rmm to engicam,microgea-stm32mp257d-rmm. Changes in v5: - Fix touchscreen resolution to 480x854 - Fix SPI1 CS0 polarity to GPIO_ACTIVE_LOW Changes in v2: - Drop the clocks property from the sai1 node in stm32mp257-engicam-microge= a-rmm.dts to avoid overriding the peripheral bus clock reference defined in the base SoC device tree. Suggested by Sashiko. - Reference the existing labeled nodes directly at the root level using &sai1a and &sai1b in stm32mp257-engicam-microgea-rmm.dts instead of redefining the entire node structure and redeclaring the labels. Suggeste= d by Sashiko. - Drop the #clock-cells property from sai1a and remove the reference to sai= 1a from the clocks array in sai1b, relying strictly on the st,sync property to ha= ndle internal synchronization. arch/arm64/boot/dts/st/Makefile | 1 + .../st/stm32mp257d-engicam-microgea-rmm.dts | 319 ++++++++++++++++++ 2 files changed, 320 insertions(+) create mode 100644 arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm= .dts diff --git a/arch/arm64/boot/dts/st/Makefile b/arch/arm64/boot/dts/st/Makef= ile index 63908113ae36..6cbccfd50993 100644 --- a/arch/arm64/boot/dts/st/Makefile +++ b/arch/arm64/boot/dts/st/Makefile @@ -2,5 +2,6 @@ dtb-$(CONFIG_ARCH_STM32) +=3D \ stm32mp215f-dk.dtb \ stm32mp235f-dk.dtb \ + stm32mp257d-engicam-microgea-rmm.dtb \ stm32mp257f-dk.dtb \ stm32mp257f-ev1.dtb diff --git a/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm.dts b/= arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm.dts new file mode 100644 index 000000000000..f5af0913bf1b --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm.dts @@ -0,0 +1,319 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026 Amarula Solutions, Dario Binacchi + * Copyright (C) 2026 Engicam srl + */ + +/dts-v1/; + +#include +#include +#include + +#include "stm32mp257-engicam-microgea.dtsi" + +/ { + model =3D "Engicam MicroGEA STM32MP257D RMM Board"; + compatible =3D "engicam,microgea-stm32mp257d-rmm", + "engicam,microgea-stm32mp257", "st,stm32mp257"; + + aliases { + mmc0 =3D &sdmmc1; + mmc1 =3D &sdmmc2; + serial0 =3D &usart2; + serial1 =3D &usart1; + }; + + backlight: backlight { + compatible =3D "pwm-backlight"; + brightness-levels =3D <0 100>; + num-interpolated-steps =3D <100>; + default-brightness-level =3D <85>; + pwms =3D <&pwm2 0 100000 0>; + }; + + buzzer { + compatible =3D "pwm-beeper"; + pwms =3D <&pwm4 0 1000000 0>; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + framebuffer { + compatible =3D "simple-framebuffer"; + clocks =3D <&rcc CK_BUS_LTDC>, <&rcc CK_KER_LTDC>; + lcd-supply =3D <®_3v3>; + status =3D "disabled"; + }; + }; + + leds { + compatible =3D "gpio-leds"; + + led-0 { + gpios =3D <&gpioh 2 GPIO_ACTIVE_HIGH>; + default-state =3D "off"; + status =3D "okay"; + }; + + led-1 { + gpios =3D <&gpioh 6 GPIO_ACTIVE_HIGH>; + default-state =3D "off"; + status =3D "okay"; + }; + }; + + mclk: clock-mclk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + }; + + reg_1v8: regulator-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + reg_3v3: regulator-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + reg_ext_pwr: regulator-ext-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "ext-pwr"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpiog 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound { + compatible =3D "audio-graph-card"; + label =3D "STM32MP25-RMM"; + widgets =3D "Headphone", "Headphone Jack", + "Microphone", "Microphone Jack"; + routing =3D "Headphone Jack", "HP_OUT", + "MIC_IN", "Microphone Jack", + "Microphone Jack", "Mic Bias"; + dais =3D <&sai1a_port &sai1b_port>; + status =3D "okay"; + }; +}; + +&arm_wdt { + timeout-sec =3D <32>; + status =3D "okay"; +}; + +&i2c1 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&i2c1_pins_a>; + pinctrl-1 =3D <&i2c1_sleep_pins_a>; + i2c-scl-rising-time-ns =3D <185>; + i2c-scl-falling-time-ns =3D <20>; + status =3D "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + touchscreen@38 { + compatible =3D "edt,edt-ft5306"; + reg =3D <0x38>; + interrupt-parent =3D <&gpiob>; + interrupts =3D <0 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&gpiod 1 GPIO_ACTIVE_LOW>; + touchscreen-size-x =3D <480>; + touchscreen-size-y =3D <854>; + }; +}; + +&i2c2 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&i2c2_pins_a>; + pinctrl-1 =3D <&i2c2_sleep_pins_a>; + i2c-scl-rising-time-ns =3D <185>; + i2c-scl-falling-time-ns =3D <20>; + status =3D "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + sgtl5000: codec@a { + compatible =3D "fsl,sgtl5000"; + reg =3D <0x0a>; + #sound-dai-cells =3D <0>; + clocks =3D <&mclk>; + + VDDA-supply =3D <®_3v3>; + VDDIO-supply =3D <®_3v3>; + VDDD-supply =3D <®_1v8>; + + sgtl5000_port: port { + #address-cells =3D <1>; + #size-cells =3D <0>; + + sgtl5000_tx_endpoint: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&sai1a_endpoint>; + frame-master =3D <&sgtl5000_tx_endpoint>; + bitclock-master =3D <&sgtl5000_tx_endpoint>; + }; + + sgtl5000_rx_endpoint: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&sai1b_endpoint>; + frame-master =3D <&sgtl5000_rx_endpoint>; + bitclock-master =3D <&sgtl5000_rx_endpoint>; + }; + }; + }; +}; + +<dc { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <<dc_pins_a>; + pinctrl-1 =3D <<dc_sleep_pins_a>; + status =3D "okay"; + + port { + ltdc_out: endpoint { + remote-endpoint =3D <&panel_in>; + }; + }; +}; + +&m_can1 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&m_can1_pins_a>; + pinctrl-1 =3D <&m_can1_sleep_pins_a>; + status =3D "okay"; +}; + +&sai1 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&sai1a_pins_a>, <&sai1b_pins_a>; + pinctrl-1 =3D <&sai1a_sleep_pins_a>, <&sai1b_sleep_pins_a>; + status =3D "okay"; +}; + +&sai1a { + dma-names =3D "tx"; + status =3D "okay"; + + sai1a_port: port { + sai1a_endpoint: endpoint { + remote-endpoint =3D <&sgtl5000_tx_endpoint>; + dai-format =3D "i2s"; + mclk-fs =3D <512>; + }; + }; +}; + +&sai1b { + dma-names =3D "rx"; + st,sync =3D <&sai1a 2>; + clocks =3D <&rcc CK_KER_SAI1>; + clock-names =3D "sai_ck"; + status =3D "okay"; + + sai1b_port: port { + sai1b_endpoint: endpoint { + remote-endpoint =3D <&sgtl5000_rx_endpoint>; + dai-format =3D "i2s"; + mclk-fs =3D <512>; + }; + }; +}; + +/* MicroSD */ +&sdmmc1 { + pinctrl-names =3D "default", "opendrain", "sleep"; + pinctrl-0 =3D <&sdmmc1_b4_pins_a>; + pinctrl-1 =3D <&sdmmc1_b4_od_pins_a>; + pinctrl-2 =3D <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + disable-wp; + st,neg-edge; + bus-width =3D <4>; + vmmc-supply =3D <&scmi_v3v3>; + vqmmc-supply =3D <&scmi_vddio1>; + no-1-8-v; + status =3D "okay"; +}; + +&spi1 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&spi1_pins_a>; + pinctrl-1 =3D <&spi1_sleep_pins_a>; + #address-cells =3D <1>; + #size-cells =3D <0>; + cs-gpios =3D <&gpioh 8 GPIO_ACTIVE_LOW>, <&gpioh 3 GPIO_ACTIVE_HIGH>; + status =3D "okay"; + + display: display@0 { + compatible =3D "rocktech,rk050hr345-ct106a", "ilitek,ili9806e"; + reg =3D <0>; + vdd-supply =3D <®_3v3>; + spi-max-frequency =3D <10000000>; + reset-gpios =3D <&gpiob 6 GPIO_ACTIVE_LOW>; + backlight =3D <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint =3D <<dc_out>; + }; + }; + }; +}; + +&timers2 { + status =3D "okay"; + + pwm2: pwm { + pinctrl-0 =3D <&pwm2_pins_a>; + pinctrl-1 =3D <&pwm2_sleep_pins_a>; + pinctrl-names =3D "default", "sleep"; + status =3D "okay"; + }; +}; + +&timers4 { + status =3D "okay"; + + pwm4: pwm { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&pwm4_pins_a>; + pinctrl-1 =3D <&pwm4_sleep_pins_a>; + status =3D "okay"; + }; +}; + +&usart1 { + pinctrl-names =3D "default", "idle", "sleep"; + pinctrl-0 =3D <&usart1_pins_b>; + pinctrl-1 =3D <&usart1_idle_pins_b>; + pinctrl-2 =3D <&usart1_sleep_pins_b>; + /delete-property/ dmas; + /delete-property/ dma-names; + status =3D "okay"; +}; + +&usart2 { + pinctrl-names =3D "default", "idle", "sleep"; + pinctrl-0 =3D <&usart2_pins_a>; + pinctrl-1 =3D <&usart2_idle_pins_a>; + pinctrl-2 =3D <&usart2_sleep_pins_a>; + /delete-property/ dmas; + /delete-property/ dma-names; + status =3D "okay"; +}; --=20 2.43.0 From nobody Mon Sep 28 17:48:33 2026 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 159063F0A96 for ; Thu, 20 Aug 2026 09:17:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[79.54.86.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-482b14c3775sm10021606f8f.26.2026.08.20.02.17.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2026 02:17:46 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: alexandre.torgue@foss.st.com, francesco.utel@engicam.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, domenico.acri@engicam.com, michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Arnd Bergmann , Bjorn Andersson , Dmitry Baryshkov , Eric Biggers , Geert Uytterhoeven , Krzysztof Kozlowski , Luca Weiss , Michal Simek , Sven Peter Subject: [PATCH v8 16/16] arm64: defconfig: enable configs for Engicam MicroGEA-STM32MP257D-RMM Date: Thu, 20 Aug 2026 11:12:24 +0200 Message-ID: <20260820091652.43541-17-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> References: <20260820091652.43541-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable I2C (touchscreen and audio codec), SPI (display configuration), DRM panel and SAI (audio) configurations required to support the Engicam MicroGEA-STM32MP257D-RMM board Signed-off-by: Dario Binacchi --- (no changes since v7) Changes in v7: - Switch CONFIG_I2C_STM32F7 and CONFIG_SPI_STM32 to modules. Changes in v6: - Update arch/arm64/configs/defconfig to match the current upstream defconf= ig after merge window changes (no functional changes). Changes in v3: - Drop patch "arm64: defconfig: cleanup the defconfig" - Rebased after dropping patch "arm64: defconfig: cleanup the defconfig" arch/arm64/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 6ec8d3a69c98..f6d3d94ab7db 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -636,6 +636,7 @@ CONFIG_I2C_RK3X=3Dy CONFIG_I2C_RZV2M=3Dm CONFIG_I2C_S3C2410=3Dy CONFIG_I2C_SH_MOBILE=3Dy +CONFIG_I2C_STM32F7=3Dm CONFIG_I2C_TEGRA=3Dy CONFIG_I2C_UNIPHIER_F=3Dy CONFIG_I2C_XILINX=3Dm @@ -673,6 +674,7 @@ CONFIG_SPI_QUP=3Dy CONFIG_SPI_QCOM_GENI=3Dm CONFIG_SPI_S3C64XX=3Dy CONFIG_SPI_SH_MSIOF=3Dm +CONFIG_SPI_STM32=3Dm CONFIG_SPI_STM32_OSPI=3Dm CONFIG_SPI_SUN6I=3Dy CONFIG_SPI_TEGRA210_QUAD=3Dm @@ -1018,6 +1020,7 @@ CONFIG_DRM_PANEL_LVDS=3Dm CONFIG_DRM_PANEL_HIMAX_HX8279=3Dm CONFIG_DRM_PANEL_HIMAX_HX83112A=3Dm CONFIG_DRM_PANEL_HIMAX_HX83112B=3Dm +CONFIG_DRM_PANEL_ILITEK_ILI9806E_SPI=3Dm CONFIG_DRM_PANEL_ILITEK_ILI9882T=3Dm CONFIG_DRM_PANEL_KHADAS_TS050=3Dm CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=3Dm @@ -1120,6 +1123,7 @@ CONFIG_SND_SOC_ROCKCHIP_SPDIF=3Dm CONFIG_SND_SOC_ROCKCHIP_RT5645=3Dm CONFIG_SND_SOC_RK3399_GRU_SOUND=3Dm CONFIG_SND_SOC_SAMSUNG=3Dm +CONFIG_SND_SOC_STM32_SAI=3Dm CONFIG_SND_SUN8I_CODEC=3Dm CONFIG_SND_SUN8I_CODEC_ANALOG=3Dm CONFIG_SND_SUN50I_CODEC_ANALOG=3Dm --=20 2.43.0