From nobody Mon Sep 28 18:36:00 2026 Received: from out198-33.us.a.mail.aliyun.com (out198-33.us.a.mail.aliyun.com [47.90.198.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D442930FC1D for ; Thu, 20 Aug 2026 01:58:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=47.90.198.33 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787191092; cv=none; b=Ds5osvQJeLubYGRmZdycLeNJEQIuIe5FlwIu6l0QCy+ESCnBhNXnQb6tP4pKk1aH+TjNoxWkRdkrJ2rG3gNYDOKV5sWiQbTU8DNzaXygRLNC8vNnwfm0g3mc+Rcq1FiYhE/5W5wt3Pn6DWNxdUWxq4AHzM04H92mpEZZmWRAu/s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787191092; c=relaxed/simple; bh=CPkcUgkcV38848G6igqHi9Ltr9OUf2085az0ZiZeadA=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=XtiemFVyh71YGv1xjETOFZxwCvzzKCrIqtrzD9Omz54PsiRt/LdrNvyaQ/DEHVZ4gCx7zLdeMqEUoBrc6aHdCCRFQ3BlJBB8PC5OgzCcJRx7vRDXSFjRmY3VU8cmoZwjcnHFJxdIQfvcq/abPaMTil0WEy0v8oOaJrhWUjX4Jbo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=hieco.com.cn; spf=pass smtp.mailfrom=hieco.com.cn; arc=none smtp.client-ip=47.90.198.33 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=hieco.com.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=hieco.com.cn X-Alimail-AntiSpam: AC=CONTINUE;BC=0.2176403|-1;BR=01201311R631S45rulernew998_84748_2000303;CH=blue;DM=|CONTINUE|false|;DS=CONTINUE|ham_system_inform|0.00404728-6.84712e-05-0.995884;FP=7117192059941373210|0|0|0|0|-1|-1|-1;HT=maildocker-contentspam033037017159;MF=zhangzihao@hieco.com.cn;NM=1;PH=DS;RN=16;RT=16;SR=0;TI=SMTPD_---.irm7tq-_1787191068; Received: from localhost.localdomain(mailfrom:zhangzihao@hieco.com.cn fp:SMTPD_---.irm7tq-_1787191068 cluster:ay29) by smtp.aliyun-inc.com; Thu, 20 Aug 2026 09:57:55 +0800 From: Mouse Zhang To: puwen@hygon.cn, tglx@kernel.org, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org Cc: hpa@zytor.com, wyes.karny@amd.com, peterz@infradead.org, linux-kernel@vger.kernel.org, tingyin.duan@gmail.com, xinruizhu75@gamil.com, shenxiaochen@open-hieco.net, fuhao@open-hieco.net, jianyong.wu@outlook.com, Mouse Zhang Subject: [PATCH] x86/cpu/hygon: Prefer HLT over MWAIT for C1 idle when SMT is enabled Date: Thu, 20 Aug 2026 09:57:46 +0800 Message-Id: <20260820015746.1715315-1-zhangzihao@hieco.com.cn> X-Mailer: git-send-email 2.39.3 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In init_hygon(), set boot_option_idle_override to IDLE_NOMWAIT when no explicit idle=3D option was given and SMT is enabled, so that the default C1 idle uses HLT instead of MWAIT. This keeps prefer_mwait_c1_over_halt() vendor-neutral while encoding the Hygon-specific policy in its own init path. On Hygon processors with SMT (2 or 4 threads per core) enabled, entering C1 with MWAIT causes a significant single-thread performance loss compared to HLT when the sibling thread is also in C1. When the sibling thread is in C2, it enters that state via IOPORT, which is independent of HLT and MWAIT, so performance is unaffected. Hygon and AMD use different hardware implementations for MWAIT C1, and HLT performs better than MWAIT on Hygon platforms when SMT is enabled. On a Hygon family 18h model 7h system with SMT2 enabled, the single-core UnixBench results show HLT outperforming MWAIT by 14.53%, and the single-core SPEC CPU 2017 results show improvements of 12.68% (intrate) and 19.73% (fprate). Commit aebef63cf7ff ("x86: Remove vendor checks from prefer_mwait_c1_over_halt"), merged in v6.0-rc1, removed the vendor check that previously made Hygon use HLT, so Hygon adopted MWAIT and hit the performance regression described above. Restore the pre-v6.0 default to avoid the regression. Fixes: aebef63cf7ff ("x86: Remove vendor checks from prefer_mwait_c1_over_h= alt") Signed-off-by: Mouse Zhang --- arch/x86/kernel/cpu/hygon.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c index ec51c2b9a257..bac71b13a0a3 100644 --- a/arch/x86/kernel/cpu/hygon.c +++ b/arch/x86/kernel/cpu/hygon.c @@ -7,6 +7,7 @@ * Author: Pu Wen */ #include +#include =20 #include #include @@ -174,6 +175,17 @@ static void init_hygon(struct cpuinfo_x86 *c) { u64 vm_cr; =20 + /* + * On Hygon platforms with SMT enabled, MWAIT is disabled by default + * for better performance. + */ + if (boot_option_idle_override =3D=3D IDLE_NO_OVERRIDE && + __max_threads_per_core > 1 && + cpu_smt_control =3D=3D CPU_SMT_ENABLED) { + pr_info("On Hygon platforms with SMT enabled, set idle=3Dnomwait by defa= ult.\n"); + boot_option_idle_override =3D IDLE_NOMWAIT; + } + early_init_hygon(c); =20 set_cpu_cap(c, X86_FEATURE_REP_GOOD); --=20 2.39.3