From nobody Mon Sep 28 14:47:00 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D61AF3A4F23; Thu, 20 Aug 2026 19:12:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787253128; cv=none; b=r7q6s9FH+Y+fmfc5W0sk7Fuam9zWoe/+9IwcYxfSKwDJ1iMr+yFHgrV1x4IUcNd5pzcahITFchRaXOHp3sKJcLmMCHiRO7L9TjVBCzAYpKjRUz4PuL8OvvOdaj71vysE+AIulvd4z1sBmycgvWXE9EBdQs3a6QzG+yB5lP8L9wQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787253128; c=relaxed/simple; bh=ksXb9ni7G9dqEx6LwsW4bBnhqCsne0tIy7naRonbgIY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CGQp0I+sezpn27DwQVE9DfeEHxWaa+eiDNcN40FUI+1T3J/fVji/KfZwawAd/mD9IqIIKymQTE/9rL8bC2Xe2e/n047ExgLwx8DH833we0XtxHSROo23Sw6aBa9NyQHAXzRwwy528fNSzfd4fQxE/ScZitYMMUahcC7A0/m1H90= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jwqXTZF3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jwqXTZF3" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6E8FDC2BCC7; Thu, 20 Aug 2026 19:12:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787253128; bh=ksXb9ni7G9dqEx6LwsW4bBnhqCsne0tIy7naRonbgIY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=jwqXTZF3KIEQx7y1BPdHwHBcL8P6vtg0jNNIRwLI78V6e6PlRCCWte/vIsoSQAywr hhh9hzwPWcCmBQFAP4sjUF9ZtSQUuvbG/OQEc4fEFV3aRqmDt6nlDPugBshQw6saKf MYf1ZXKGTHwDUR+qxV+WoKq7E8ixwzU5czvH2SoKyR461HqSl0Sa2J/BCQ9PlBSm9Y 0Uoc+46mH9SC82te0MM7ZyOVoBT7cOfvlNnF3IZo8QSFBNc+DPLo5A/3utjSR4iRUs c9TcbL2qUBLHO8OGdrQfwKMDd1i4cuOTZPJ5DQAo21bA71tmQcHz9+KTfYlGVeSO6W 78LL86kt51O6A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CAA6C5DF86; Thu, 20 Aug 2026 19:12:08 +0000 (UTC) From: Markuss Broks via B4 Relay Date: Thu, 20 Aug 2026 22:12:05 +0300 Subject: [PATCH 1/4] iommu/exynos: detect SysMMUs without BLOCK mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260820-exynos-iommu-fixes-v1-1-6bbcd673bb15@gmail.com> References: <20260820-exynos-iommu-fixes-v1-0-6bbcd673bb15@gmail.com> In-Reply-To: <20260820-exynos-iommu-fixes-v1-0-6bbcd673bb15@gmail.com> To: Marek Szyprowski , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Krzysztof Kozlowski , Peter Griffin , Alim Akhtar Cc: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Markuss Broks X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787253126; l=1479; i=markuss.broks@gmail.com; s=20260803; h=from:subject:message-id; bh=mOr89jBc1c/3DemuQ56Wmn7lSeAvv7DoZx+sJdo6D2U=; b=6nEHQ0bpJYt2EXU7sB+pTrh8uM4qqZlYciy0rMZ3uIIw056/blzZCqnEYUw/BlDczramgZk8s D+ueRGcYxxyB9FQi32Q0zQlCTS+8SQDf1EHZSuOANkujC0hVsTMRojF X-Developer-Key: i=markuss.broks@gmail.com; a=ed25519; pk=oKzGUTm30BCDqinRMpiHQqByOx1mp2mwmhg80Mv7Zg4= X-Endpoint-Received: by B4 Relay for markuss.broks@gmail.com/20260803 with auth_id=911 X-Original-From: Markuss Broks Reply-To: markuss.broks@gmail.com From: Markuss Broks Newer SysMMU instances may not implement BLOCK mode: writing CTRL_BLOCK does not stop translation, and MMU_STATUS never reports a blocked state. The hardware advertises this in CAPA1 bit 15, which the vendor driver reads as MMU_CAPA1_NO_BLOCK_MODE; the SysMMUs on Exynos8835 are such instances. Signed-off-by: Markuss Broks Acked-by: Marek Szyprowski --- drivers/iommu/exynos-iommu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 874d05f4b396..0319da9fd831 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -143,6 +143,7 @@ static u32 lv2ent_offset(sysmmu_iova_t iova) #define CTRL_VM_FAULT_MODE_STALL BIT(3) #define CAPA0_CAPA1_EXIST BIT(11) #define CAPA1_VCR_ENABLED BIT(14) +#define CAPA1_NO_BLOCK_MODE BIT(15) =20 /* common registers */ #define REG_MMU_CTRL 0x000 @@ -306,6 +307,7 @@ struct sysmmu_drvdata { =20 /* v7 fields */ bool has_vcr; /* virtual machine control register */ + bool no_block; /* BLOCK mode not implemented */ }; =20 #define SYSMMU_REG(data, reg) ((data)->sfrbase + (data)->variant->reg) @@ -511,6 +513,7 @@ static void __sysmmu_get_vcr(struct sysmmu_drvdata *dat= a) u32 capa1 =3D readl(data->sfrbase + REG_V7_CAPA1); =20 data->has_vcr =3D capa1 & CAPA1_VCR_ENABLED; + data->no_block =3D capa1 & CAPA1_NO_BLOCK_MODE; } =20 static void __sysmmu_get_version(struct sysmmu_drvdata *data) --=20 2.55.0 From nobody Mon Sep 28 14:47:00 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF97F3A48E3; Thu, 20 Aug 2026 19:12:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787253128; cv=none; b=SaMwIedzyNZH1g9NQ2T++Ys9Puf0DzFHfGjAUCujjCcm+66hnElsmz9I/gOJIQDHscQtKrjzBFIkVOUzWHYARHcA8GBcVBkqWyUZW4wdW44z2Et5BcAA+WIxH5Yyble8DoCK3B1VKxV9oOMlc0bzR5FlgOp7HdNI3+Ids3bI3Ag= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787253128; c=relaxed/simple; bh=FClt2rXZfpheNKgojWzXtNzlVz6kIXUmUxfCqnurlQ4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oVY2uudR6iXlGuf17v6iPycqb//Eo9sXehHITVAgvi5g4HqBILQCmsg8TDJCPxZYdqtTtZnS3u5EQgmI7k8UcNmRBYaww5PmU7WS+BDljH7qbTR1uBvBIWO8K6VvGeukPMBiCXsVfLF6deHkthEEAVK1URWKB2IMsMIMWqjwvwQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=K8ZO7Hpn; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="K8ZO7Hpn" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7CDC8C2BCFB; Thu, 20 Aug 2026 19:12:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787253128; bh=FClt2rXZfpheNKgojWzXtNzlVz6kIXUmUxfCqnurlQ4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=K8ZO7HpnJU8dJkDP7rMbPNU6BEe9coezE1NuY6A+PMdpR9SHdHO5QpiSZ2OcnNKxn rpD69lypdibG8FMcZZ+BrEvBGBLs/zffIZ1skw1LYYvLz8yEKnYiraMae0tyl5Z9c3 mR2mqg45/xv1fCv2n7ghjyn9n00DeOXvsrJn1+LKJ0yW+Gz8ZVciVZmjqDy+XTMIjd 3frmvOUJP3FEv9uE25Te/hHqII6tw9p9BcCdwgg2dnOGm7Py4tCXR3NnGJmVpnPpue V8CIvuJpnHHLSiTYdR9ea8CkA3haAVhsvtMqE3E4bSLhonqTSMNQ1ny7G4LHBlxpSa LeiFOA16UomMA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 668F8C5DF8C; Thu, 20 Aug 2026 19:12:08 +0000 (UTC) From: Markuss Broks via B4 Relay Date: Thu, 20 Aug 2026 22:12:06 +0300 Subject: [PATCH 2/4] iommu/exynos: fix the enable sequence for no-block SysMMUs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260820-exynos-iommu-fixes-v1-2-6bbcd673bb15@gmail.com> References: <20260820-exynos-iommu-fixes-v1-0-6bbcd673bb15@gmail.com> In-Reply-To: <20260820-exynos-iommu-fixes-v1-0-6bbcd673bb15@gmail.com> To: Marek Szyprowski , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Krzysztof Kozlowski , Peter Griffin , Alim Akhtar Cc: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Markuss Broks X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787253126; l=1548; i=markuss.broks@gmail.com; s=20260803; h=from:subject:message-id; bh=K4btCYT7ezjlx6H4fapioD7ShFs/jWpvk5zQdk+w7+8=; b=eWfEM667DBzpg9cwP+89xFePRCc5Xqc6CdWKOSqJyauS4P76wUs+9H76z2L5zWlaTjSRxLcuD 8bTDvt94nd4AEmQKh38tilyh8prRWFXzKOGzlp4YWDUx7VO7+47Egjo X-Developer-Key: i=markuss.broks@gmail.com; a=ed25519; pk=oKzGUTm30BCDqinRMpiHQqByOx1mp2mwmhg80Mv7Zg4= X-Endpoint-Received: by B4 Relay for markuss.broks@gmail.com/20260803 with auth_id=911 X-Original-From: Markuss Broks Reply-To: markuss.broks@gmail.com From: Markuss Broks __sysmmu_enable() writes CTRL_BLOCK before programming CFG, the page table base and the VM registers. CTRL_BLOCK has the enable bit set, so on hardware without BLOCK mode this write immediately starts translation with whatever FLPT base the registers hold: reset values on the first enable, a stale page table on re-enable. A master that is already emitting traffic at that point gets its transactions translated through that garbage. Keep the MMU disabled while it is being programmed on such hardware; the final CTRL_ENABLE write then brings it up with a consistent configuration in one step, which is also the same as the vendor driver sequence. Signed-off-by: Markuss Broks Acked-by: Marek Szyprowski --- drivers/iommu/exynos-iommu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 0319da9fd831..a3a59d8a4cf1 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -655,7 +655,12 @@ static void __sysmmu_enable(struct sysmmu_drvdata *dat= a) __sysmmu_enable_clocks(data); =20 spin_lock_irqsave(&data->lock, flags); - writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); + /* + * On no-block hardware CTRL_BLOCK acts as a plain enable; keep the + * MMU disabled until it is fully programmed. + */ + if (!data->no_block) + writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); __sysmmu_init_config(data); __sysmmu_set_ptbase(data, data->pgtable); __sysmmu_enable_vid(data); --=20 2.55.0 From nobody Mon Sep 28 14:47:00 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D62B83A4F30; Thu, 20 Aug 2026 19:12:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787253128; cv=none; b=sqRoHRBa4KX4objqxTgZJBEMXFC0wTCc7y3I2SmAJiFDlcDslwrwfJAaVOECQ8Mky/QtR9SuVCdW3pgKnO/PfETgISYgq0kyFR8LfebEqqoXuIqOcD+zhgPZKJnXEvy0wUZNFa9MjhGh0oKc6/e0oP+ow7GoTCt6tcrzpnYKTJs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787253128; c=relaxed/simple; bh=ga11gBdb5eBtt5ElhIBixkEHwyzyp+XXck2vhlIjGFc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=r9VbHxQCfLHXzvxeZ/PHxf0FD/CWzl2D+5q9T44LG0KWvQsxhHRkPfF6vTEiGyYbsSeYr7dAyhxgib3cBtcNCq0hIAHjUMVsuhnlo2wxdxqKq4gb7rOGvA/dJm0E/j5jcomMPkxGc7bc9HupPRcIl+9Kth9/jYKTop086P1vDvY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JAd617qk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JAd617qk" Received: by smtp.kernel.org (Postfix) with ESMTPS id 97A49C2BCFD; Thu, 20 Aug 2026 19:12:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787253128; bh=ga11gBdb5eBtt5ElhIBixkEHwyzyp+XXck2vhlIjGFc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=JAd617qke6WhYeXp6mm3jjnGfXY7EeDzezRBCQNVNOipOX2rXLOJG60Ek4Yc/dFCz wzdojLHJpujIKPaiWpRcW8T8egeqv+IyvSlU9scQII41yJ1MgIcPBTu19AAA2dwPl3 QBaCfU2+5p98eEvK12BOpBZuLGkjgnLlykPfrXbGYyByg8dcZWPAm2PbxVRspFv3Ru tFASHlChBHKxFuN3LfXbWMmuohahLzd6uMobYMmEUhfTwdzq0uNiNIDO20MSf+1vBT xz+8azPrm2QBH+iLjEPbY4EMx+VSerQGZOpktSuet2I42FQQN1YILUVtj+cmX3QVMj oeogWAaz9Z4FQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85FC0C5DF86; Thu, 20 Aug 2026 19:12:08 +0000 (UTC) From: Markuss Broks via B4 Relay Date: Thu, 20 Aug 2026 22:12:07 +0300 Subject: [PATCH 3/4] iommu/exynos: fix TLB invalidation for no-block SysMMUs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260820-exynos-iommu-fixes-v1-3-6bbcd673bb15@gmail.com> References: <20260820-exynos-iommu-fixes-v1-0-6bbcd673bb15@gmail.com> In-Reply-To: <20260820-exynos-iommu-fixes-v1-0-6bbcd673bb15@gmail.com> To: Marek Szyprowski , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Krzysztof Kozlowski , Peter Griffin , Alim Akhtar Cc: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Markuss Broks X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787253126; l=1957; i=markuss.broks@gmail.com; s=20260803; h=from:subject:message-id; bh=HrkpBlZCi51pjFv6cW4myb/9v3ctbW7Y5uVSy6+Uxlw=; b=4vw4diMfzpg6jMkBwD2QGOLnKc61wkJfWQEuXDwnPSCbO5WU6JnfM39Vifoh4H+FbAxFDD6wV p0M+hzavBGOB8tUTLy3V1uIZ8yBWZGf0XlDyHVi71pnU0kqsYoODXCe X-Developer-Key: i=markuss.broks@gmail.com; a=ed25519; pk=oKzGUTm30BCDqinRMpiHQqByOx1mp2mwmhg80Mv7Zg4= X-Endpoint-Received: by B4 Relay for markuss.broks@gmail.com/20260803 with auth_id=911 X-Original-From: Markuss Broks Reply-To: markuss.broks@gmail.com From: Markuss Broks sysmmu_block() polls MMU_STATUS for the blocked state, which no-block hardware never reports, so on such SysMMUs it always fails, and both sysmmu_tlb_invalidate_entry() and sysmmu_tlb_invalidate_flpdcache() skip the invalidation entirely when blocking fails. On no-block hardware the invalidation registers are written with the MMU running; the vendor driver never blocks around invalidation. Do the same and write the invalidation directly. In the FLPD cache path no-block implies a v7+ SysMMU, hence the unconditional flush-all. Signed-off-by: Markuss Broks Acked-by: Marek Szyprowski --- drivers/iommu/exynos-iommu.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index a3a59d8a4cf1..29b27c7e400a 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -685,7 +685,14 @@ static void sysmmu_tlb_invalidate_flpdcache(struct sys= mmu_drvdata *data, spin_lock_irqsave(&data->lock, flags); if (data->active && data->version >=3D MAKE_MMU_VER(3, 3)) { clk_enable(data->clk_master); - if (sysmmu_block(data)) { + /* + * No-block hardware accepts invalidation writes while the + * MMU is running; it is also v7+, so flush-all covers the + * FLPD cache. + */ + if (data->no_block) { + __sysmmu_tlb_invalidate(data); + } else if (sysmmu_block(data)) { if (data->version >=3D MAKE_MMU_VER(5, 0)) __sysmmu_tlb_invalidate(data); else @@ -721,7 +728,9 @@ static void sysmmu_tlb_invalidate_entry(struct sysmmu_d= rvdata *data, if (MMU_MAJ_VER(data->version) =3D=3D 2) num_inv =3D min_t(unsigned int, size / SPAGE_SIZE, 64); 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Thu, 20 Aug 2026 19:12:08 +0000 (UTC) From: Markuss Broks via B4 Relay Date: Thu, 20 Aug 2026 22:12:08 +0300 Subject: [PATCH 4/4] iommu/exynos: decode the v7 fault transaction info Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260820-exynos-iommu-fixes-v1-4-6bbcd673bb15@gmail.com> References: <20260820-exynos-iommu-fixes-v1-0-6bbcd673bb15@gmail.com> In-Reply-To: <20260820-exynos-iommu-fixes-v1-0-6bbcd673bb15@gmail.com> To: Marek Szyprowski , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Krzysztof Kozlowski , Peter Griffin , Alim Akhtar Cc: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Markuss Broks X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787253126; l=2986; i=markuss.broks@gmail.com; s=20260803; h=from:subject:message-id; bh=ds2FwQf93t6aWc7pL7d/0AcQafl2TKcR73r3avK3lF8=; b=YUghpcT3gXo+61EMw7hA+qlTiMj8yjh8tzM6VDTi7YPQ3VKz8u0bFvtG0QjbiBNKUcMwHH56R lT9X87yn00mAy1WcXOJKoOOwxQsnmgcSMKU4sIwgXItFBMqnTdANjT/ X-Developer-Key: i=markuss.broks@gmail.com; a=ed25519; pk=oKzGUTm30BCDqinRMpiHQqByOx1mp2mwmhg80Mv7Zg4= X-Endpoint-Received: by B4 Relay for markuss.broks@gmail.com/20260803 with auth_id=911 X-Original-From: Markuss Broks Reply-To: markuss.broks@gmail.com From: Markuss Broks The v7+ fault registers carry a transaction-info word alongside the faulting address, but it is only used to derive the read/write direction and then thrown away. Keep it and print it: AxID identifies which port inside the master issued the faulting transaction, which is the only way to tell apart the several DMA engines a single block can contain, and the remaining bits of the raw word are implementation defined and worth having in a fault report. Define the known fields of the word instead of open-coding the masks; this also names the direction bit the driver was already testing as a bare BIT(20). Gate the print on the variant having a fault_info register, so older SysMMUs are unaffected. Signed-off-by: Markuss Broks Acked-by: Marek Szyprowski --- drivers/iommu/exynos-iommu.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 29b27c7e400a..0bca3662fdc2 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -8,6 +8,7 @@ #define DEBUG #endif =20 +#include #include #include #include @@ -144,6 +145,9 @@ static u32 lv2ent_offset(sysmmu_iova_t iova) #define CAPA0_CAPA1_EXIST BIT(11) #define CAPA1_VCR_ENABLED BIT(14) #define CAPA1_NO_BLOCK_MODE BIT(15) +#define FAULT_INFO_AXID GENMASK(15, 0) +#define FAULT_INFO_AXLEN GENMASK(19, 16) +#define FAULT_INFO_WRITE BIT(20) =20 /* common registers */ #define REG_MMU_CTRL 0x000 @@ -194,6 +198,7 @@ struct sysmmu_fault { sysmmu_iova_t addr; /* IOVA address that caused fault */ const char *name; /* human readable fault name */ unsigned int type; /* fault type for report_iommu_fault() */ + u32 info; /* raw transaction info (v7+ only) */ }; =20 struct sysmmu_v1_fault_info { @@ -360,7 +365,8 @@ static int exynos_sysmmu_v7_get_fault_info(struct sysmm= u_drvdata *data, =20 fault->addr =3D readl(SYSMMU_REG(data, fault_va)); fault->name =3D sysmmu_v7_fault_names[itype % 4]; - fault->type =3D (info & BIT(20)) ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ; + fault->type =3D (info & FAULT_INFO_WRITE) ? IOMMU_FAULT_WRITE : IOMMU_FAU= LT_READ; + fault->info =3D info; =20 return 0; } @@ -558,6 +564,12 @@ static void show_fault_information(struct sysmmu_drvda= ta *data, dev_name(data->master), fault->type =3D=3D IOMMU_FAULT_READ ? "READ" : "WRITE", fault->name, fault->addr); + /* AxID identifies the issuing port inside the master */ + if (data->variant->fault_info) + dev_err(data->sysmmu, "transaction info %#010x: AxID %#lx, AxLEN %lu\n", + fault->info, + FIELD_GET(FAULT_INFO_AXID, fault->info), + FIELD_GET(FAULT_INFO_AXLEN, fault->info)); dev_dbg(data->sysmmu, "Page table base: %pa\n", &data->pgtable); ent =3D section_entry(phys_to_virt(data->pgtable), fault->addr); dev_dbg(data->sysmmu, "\tLv1 entry: %#x\n", *ent); --=20 2.55.0