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Wed, 19 Aug 2026 12:13:28 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Laurent Pinchart , Philipp Zabel , Bartosz Golaszewski , Magnus Damm Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v4 1/4] soc: renesas: rz-sysc: Register auxiliary device for PWRRDY power sequencer Date: Wed, 19 Aug 2026 20:13:18 +0100 Message-ID: <20260819191325.217809-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260819191325.217809-1-biju.das.jz@bp.renesas.com> References: <20260819191325.217809-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Some RZ SoCs (e.g. RZ/G3L) have a PWRRDY register that is controlled through a power sequencer rather than directly by the SYSC driver. Add a pwrrdy_pwrseq flag to struct rz_sysc_soc_id_init_data to mark SoCs with this property, and set it for RZ/G3L. When set, rz_sysc_probe() registers a "pwrseq-pwrrdy" auxiliary device so a dedicated driver can handle the PWRRDY sequencing. Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das --- v3->v4: * Dropped rz_sysc_pwrrdy_pwrseq_init() * Collected tag. v2->v3: * Updated commit description by dropping devm_add_action_or_reset(). * Config now selects AUXILIARY_BUS to avoid compilation issues. * Dropped the cast in devm_auxiliary_device_create(). v1->v2: * Switched to devm_auxiliary_device_create(). * Added regmap parameter to rz_sysc_pwrrdy_pwrseq_init(),so that regmap can be passed as platform data. --- drivers/soc/renesas/Kconfig | 1 + drivers/soc/renesas/r9a08g046-sysc.c | 1 + drivers/soc/renesas/rz-sysc.c | 5 +++++ drivers/soc/renesas/rz-sysc.h | 2 ++ 4 files changed, 9 insertions(+) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index eb8ac0d47d9d..4929ea350cec 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -486,6 +486,7 @@ config RZN1_IRQMUX config SYSC_RZ bool "System controller for RZ SoCs" if COMPILE_TEST select MFD_SYSCON + select AUXILIARY_BUS =20 config SYSC_R9A08G045 bool "Renesas System controller support for R9A08G045 (RZ/G3S)" if COMPIL= E_TEST diff --git a/drivers/soc/renesas/r9a08g046-sysc.c b/drivers/soc/renesas/r9a= 08g046-sysc.c index 90db9d383539..cd129c727461 100644 --- a/drivers/soc/renesas/r9a08g046-sysc.c +++ b/drivers/soc/renesas/r9a08g046-sysc.c @@ -76,6 +76,7 @@ static const struct rz_sysc_soc_id_init_data rzg3l_sysc_s= oc_id_init_data __initc .devid_offset =3D 0xa04, .revision_mask =3D GENMASK(31, 28), .specific_id_mask =3D GENMASK(27, 0), + .pwrrdy_pwrseq =3D true, }; =20 const struct rz_sysc_init_data rzg3l_sysc_init_data __initconst =3D { diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c index 161e8c38eea6..0e92c415d4be 100644 --- a/drivers/soc/renesas/rz-sysc.c +++ b/drivers/soc/renesas/rz-sysc.c @@ -5,6 +5,7 @@ * Copyright (C) 2024 Renesas Electronics Corp. */ =20 +#include #include #include #include @@ -149,6 +150,10 @@ static int rz_sysc_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); =20 + if (data->soc_id_init_data->pwrrdy_pwrseq && + !devm_auxiliary_device_create(dev, "pwrseq-pwrrdy", regmap)) + return -ENODEV; + return of_syscon_register_regmap(dev->of_node, regmap); } =20 diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h index 921ee0d26c47..e55f3258d703 100644 --- a/drivers/soc/renesas/rz-sysc.h +++ b/drivers/soc/renesas/rz-sysc.h @@ -20,6 +20,7 @@ * @revision_mask: SYSC SoC ID revision mask * @specific_id_mask: SYSC SoC ID specific ID mask * @print_id: print SoC-specific extended device identification + * @pwrrdy_pwrseq: has pwrrdy register controlled through power sequencer */ struct rz_sysc_soc_id_init_data { const char * const family; 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Wed, 19 Aug 2026 12:13:29 -0700 (PDT) Received: from biju.lan ([2a00:23c4:a702:d301:c7e0:8c9b:65f0:4aef]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-482b14c338dsm6153398f8f.25.2026.08.19.12.13.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Aug 2026 12:13:29 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Bartosz Golaszewski , Geert Uytterhoeven , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Laurent Pinchart , Philipp Zabel , Magnus Damm Cc: Biju Das , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v4 2/4] power: sequencing: Fix build issue with COMPILE_TEST Date: Wed, 19 Aug 2026 20:13:19 +0100 Message-ID: <20260819191325.217809-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260819191325.217809-1-biju.das.jz@bp.renesas.com> References: <20260819191325.217809-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The POWER_SEQUENCING_TH1520_GPU driver depends on (ARCH_THEAD && AUXILIARY_BUS) || COMPILE_TEST. This means when COMPILE_TEST=3Dy and ARCH_THEAD is not set, the driver can still be built even though it requires AUXILIARY_BUS, which may not be selected in that configuration, leading to a build failure. Fix this by dropping AUXILIARY_BUS from the dependency and instead selecting it directly, so the dependency is satisfied regardless of whether COMPILE_TEST or ARCH_THEAD is enabled. Fixes: 1a7312b93ab0 ("power: sequencing: extend build coverage with COMPILE= _TEST=3Dy") Signed-off-by: Biju Das --- v4: * New patch. --- drivers/power/sequencing/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/power/sequencing/Kconfig b/drivers/power/sequencing/Kc= onfig index 1c5f5820f5b7..226c62704d9b 100644 --- a/drivers/power/sequencing/Kconfig +++ b/drivers/power/sequencing/Kconfig @@ -29,7 +29,8 @@ config POWER_SEQUENCING_QCOM_WCN =20 config POWER_SEQUENCING_TH1520_GPU tristate "T-HEAD TH1520 GPU power sequencing driver" - depends on (ARCH_THEAD && AUXILIARY_BUS) || COMPILE_TEST + depends on ARCH_THEAD || COMPILE_TEST + select AUXILIARY_BUS help Say Y here to enable the power sequencing driver for the TH1520 SoC GPU. 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Wed, 19 Aug 2026 12:13:30 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Bartosz Golaszewski , Geert Uytterhoeven , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Laurent Pinchart , Philipp Zabel , Magnus Damm Cc: Biju Das , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v4 3/4] power: sequencing: Add Renesas RZ/G3L Power Ready driver Date: Wed, 19 Aug 2026 20:13:20 +0100 Message-ID: <20260819191325.217809-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260819191325.217809-1-biju.das.jz@bp.renesas.com> References: <20260819191325.217809-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add a power sequencing driver for the Renesas RZ/G3L PWRRDY module, which signals power readiness for various IPs (USB, DSI, CSI etc.) on the SoC. The driver binds as an auxiliary device to the parent SYSC driver, using its regmap to toggle the SYS_PWRRDY_N register bits, and exposes {usb,dsi,csi}-pwrrdy pwrseq targets. Signed-off-by: Biju Das --- v3->v4: * Replace the large of_device_id structures by C strings, and using of_device_is_compatible() will reduce kernel size. * Replaced of_device.h -> of.h * Dropped local variable pwrseq from pwrseq_rzg3l_pwrrdy_probe(). v2->v3: * Kconfig selects AUXILIARY_BUS to avoid compilation issues. * Added match for consumer device and added of_device.h header file. * Replaced regmap_update_bits()->regmap_assign_bits() and updated the function parameter of pwrseq_rzg3l_set_pwrrdy(). * Simpilfied probe() return with PTR_ERR_OR_ZERO macro. v1->v2: * Added a comment in pwrseq_rzg3l_pwrrdy_match(). * Dropped dev_get_regmap() from probe as regmap is now part of platform data. * Added a blank line before devm_pwrseq_device_register() in probe. * Dropped the error message devm_pwrseq_device_register() as probe prints failure message. * Dropped local variables dev and regmap from probe(). --- drivers/power/sequencing/Kconfig | 9 ++ drivers/power/sequencing/Makefile | 1 + .../power/sequencing/pwrseq-renesas-pwrrdy.c | 137 ++++++++++++++++++ 3 files changed, 147 insertions(+) create mode 100644 drivers/power/sequencing/pwrseq-renesas-pwrrdy.c diff --git a/drivers/power/sequencing/Kconfig b/drivers/power/sequencing/Kc= onfig index 226c62704d9b..6b5d187dd4b5 100644 --- a/drivers/power/sequencing/Kconfig +++ b/drivers/power/sequencing/Kconfig @@ -27,6 +27,15 @@ config POWER_SEQUENCING_QCOM_WCN this driver is needed for correct power control or else we'd risk not respecting the required delays between enabling Bluetooth and WLAN. =20 +config POWER_SEQUENCING_RENESAS_PWRRDY + tristate "Renesas Power Ready sequencing driver" + depends on SYSC_RZ || COMPILE_TEST + select AUXILIARY_BUS + help + Say Y here to enable the power sequencing driver for the Renesas + Power Ready signals. This driver handles the power ready signals + required to power on the various IP's on RZ/G3L platform. + config POWER_SEQUENCING_TH1520_GPU tristate "T-HEAD TH1520 GPU power sequencing driver" depends on ARCH_THEAD || COMPILE_TEST diff --git a/drivers/power/sequencing/Makefile b/drivers/power/sequencing/M= akefile index 0911d4618298..b33d08d82f43 100644 --- a/drivers/power/sequencing/Makefile +++ b/drivers/power/sequencing/Makefile @@ -4,5 +4,6 @@ obj-$(CONFIG_POWER_SEQUENCING) +=3D pwrseq-core.o pwrseq-core-y :=3D core.o =20 obj-$(CONFIG_POWER_SEQUENCING_QCOM_WCN) +=3D pwrseq-qcom-wcn.o +obj-$(CONFIG_POWER_SEQUENCING_RENESAS_PWRRDY) +=3D pwrseq-renesas-pwrrdy.o obj-$(CONFIG_POWER_SEQUENCING_TH1520_GPU) +=3D pwrseq-thead-gpu.o obj-$(CONFIG_POWER_SEQUENCING_PCIE_M2) +=3D pwrseq-pcie-m2.o diff --git a/drivers/power/sequencing/pwrseq-renesas-pwrrdy.c b/drivers/pow= er/sequencing/pwrseq-renesas-pwrrdy.c new file mode 100644 index 000000000000..b8d62a4fecc7 --- /dev/null +++ b/drivers/power/sequencing/pwrseq-renesas-pwrrdy.c @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/G3L Power Ready driver + * + */ + +#include +#include +#include +#include +#include + +#define SYS_PWRRDY_N 0xd70 +#define SYS_PWRRDY_N_USB_MASK BIT(0) +#define SYS_PWRRDY_N_DSI_MASK BIT(1) +#define SYS_PWRRDY_N_CSI_MASK BIT(2) + +static int pwrseq_rzg3l_set_pwrrdy(struct pwrseq_device *pwrseq, u32 mask, + bool val) +{ + struct regmap *regmap =3D pwrseq_device_get_drvdata(pwrseq); + + return regmap_assign_bits(regmap, SYS_PWRRDY_N, mask, val); +} + +static int pwrseq_rzg3l_usb_pwrrdy_enable(struct pwrseq_device *pwrseq) +{ + return pwrseq_rzg3l_set_pwrrdy(pwrseq, SYS_PWRRDY_N_USB_MASK, 0); +} + +static int pwrseq_rzg3l_usb_pwrrdy_disable(struct pwrseq_device *pwrseq) +{ + return pwrseq_rzg3l_set_pwrrdy(pwrseq, SYS_PWRRDY_N_USB_MASK, 1); +} + +static const struct pwrseq_unit_data pwrseq_rzg3l_usb_pwrrdy_unit =3D { + .name =3D "usb-pwrrdy-power-sequence", + .enable =3D pwrseq_rzg3l_usb_pwrrdy_enable, + .disable =3D pwrseq_rzg3l_usb_pwrrdy_disable, +}; + +static int pwrseq_rzg3l_dsi_pwrrdy_enable(struct pwrseq_device *pwrseq) +{ + return pwrseq_rzg3l_set_pwrrdy(pwrseq, SYS_PWRRDY_N_DSI_MASK, 0); +} + +static int pwrseq_rzg3l_dsi_pwrrdy_disable(struct pwrseq_device *pwrseq) +{ + return pwrseq_rzg3l_set_pwrrdy(pwrseq, SYS_PWRRDY_N_DSI_MASK, 1); +} + +static const struct pwrseq_unit_data pwrseq_rzg3l_dsi_pwrrdy_unit =3D { + .name =3D "dsi-pwrrdy-sequence", + .enable =3D pwrseq_rzg3l_dsi_pwrrdy_enable, + .disable =3D pwrseq_rzg3l_dsi_pwrrdy_disable, +}; + +static int pwrseq_rzg3l_csi_pwrrdy_enable(struct pwrseq_device *pwrseq) +{ + return pwrseq_rzg3l_set_pwrrdy(pwrseq, SYS_PWRRDY_N_CSI_MASK, 0); +} + +static int pwrseq_rzg3l_csi_pwrrdy_disable(struct pwrseq_device *pwrseq) +{ + return pwrseq_rzg3l_set_pwrrdy(pwrseq, SYS_PWRRDY_N_CSI_MASK, 1); +} + +static const struct pwrseq_unit_data pwrseq_rzg3l_csi_pwrrdy_unit =3D { + .name =3D "csi-pwrrdy-power-sequence", + .enable =3D pwrseq_rzg3l_csi_pwrrdy_enable, + .disable =3D pwrseq_rzg3l_csi_pwrrdy_disable, +}; + +static const struct pwrseq_target_data pwrseq_rzg3l_usb_pwrrdy_target =3D { + .name =3D "usb-pwrrdy", + .unit =3D &pwrseq_rzg3l_usb_pwrrdy_unit, +}; + +static const struct pwrseq_target_data pwrseq_rzg3l_dsi_pwrrdy_target =3D { + .name =3D "dsi-pwrrdy", + .unit =3D &pwrseq_rzg3l_dsi_pwrrdy_unit, +}; + +static const struct pwrseq_target_data pwrseq_rzg3l_csi_pwrrdy_target =3D { + .name =3D "csi-pwrrdy", + .unit =3D &pwrseq_rzg3l_csi_pwrrdy_unit, +}; + +static const struct pwrseq_target_data *pwrseq_rzg3l_pwrrdy_targets[] =3D { + &pwrseq_rzg3l_usb_pwrrdy_target, + &pwrseq_rzg3l_dsi_pwrrdy_target, + &pwrseq_rzg3l_csi_pwrrdy_target, + NULL +}; + +static int pwrseq_rzg3l_pwrrdy_match(struct pwrseq_device *pwrseq, + struct device *dev) +{ + if (of_device_is_compatible(dev->of_node, "renesas,r9a08g046-usbphy-ctrl"= ) || + of_device_is_compatible(dev->of_node, "renesas,r9a08g046-mipi-dsi")) + return PWRSEQ_MATCH_OK; + + return PWRSEQ_NO_MATCH; +} + +static int pwrseq_rzg3l_pwrrdy_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct pwrseq_config config =3D { + .parent =3D &adev->dev, + .owner =3D THIS_MODULE, + .drvdata =3D adev->dev.platform_data, + .match =3D pwrseq_rzg3l_pwrrdy_match, + .targets =3D pwrseq_rzg3l_pwrrdy_targets, + }; + + return PTR_ERR_OR_ZERO(devm_pwrseq_device_register(&adev->dev, &config)); +} + +static const struct auxiliary_device_id pwrseq_rzg3l_pwrrdy_id_table[] =3D= { + { .name =3D "rz_sysc.pwrseq-pwrrdy" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(auxiliary, pwrseq_rzg3l_pwrrdy_id_table); + +static struct auxiliary_driver pwrseq_rzg3l_pwrrdy_driver =3D { + .driver =3D { + .name =3D "pwrseq-rzg3l-pwrrdy", + }, + .probe =3D pwrseq_rzg3l_pwrrdy_probe, + .id_table =3D pwrseq_rzg3l_pwrrdy_id_table, +}; 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Wed, 19 Aug 2026 12:13:31 -0700 (PDT) Received: from biju.lan ([2a00:23c4:a702:d301:c7e0:8c9b:65f0:4aef]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-482b14c338dsm6153398f8f.25.2026.08.19.12.13.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Aug 2026 12:13:30 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Laurent Pinchart , Philipp Zabel , Bartosz Golaszewski , Magnus Damm Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v4 4/4] soc: renesas: Kconfig: Select POWER_SEQUENCING_RENESAS_PWRRDY for R9A08G046 Date: Wed, 19 Aug 2026 20:13:21 +0100 Message-ID: <20260819191325.217809-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260819191325.217809-1-biju.das.jz@bp.renesas.com> References: <20260819191325.217809-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The RZ/G3L SYSC driver registers a "pwrseq-pwrrdy" auxiliary device to handle the PWRRDY power sequencing, which requires the pwrseq-renesas-pwrrdy driver to bind to it. Select POWER_SEQUENCING_RENESAS_PWRRDY from SYSC_R9A08G046 so it's built whenever RZ/G3L SYSC support is enabled. Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das --- v3->v4: * Collected the tag. v2->v3: * Kconfig selects POWER_SEQUENCING as POWER_SEQUENCING_RENESAS_PWRRDY is defined inside an if POWER_SEQUENCING block in drivers/power/sequencing/Kconfig v1->v2: * No change. --- drivers/soc/renesas/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 4929ea350cec..987958d494a5 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -495,6 +495,8 @@ config SYSC_R9A08G045 config SYSC_R9A08G046 bool "Renesas System controller support for R9A08G046 (RZ/G3L)" if COMPIL= E_TEST select SYSC_RZ + select POWER_SEQUENCING + select POWER_SEQUENCING_RENESAS_PWRRDY =20 config SYS_R9A09G047 bool "Renesas System controller support for R9A09G047 (RZ/G3E)" if COMPIL= E_TEST --=20 2.43.0