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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-327bef77fc0sm15148144eec.8.2026.08.19.08.24.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Aug 2026 08:24:12 -0700 (PDT) From: Shawn Guo To: Bartosz Golaszewski Cc: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo , stable@vger.kernel.org Subject: [PATCH] pinctrl: qcom: nord: Split QUP1 SE2/SE3 into lane-pair functions Date: Wed, 19 Aug 2026 23:23:56 +0800 Message-ID: <20260819152356.904023-1-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=E5/9Y6dl c=1 sm=1 tr=0 ts=6a85ca9e cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=hkSOFwkIQQlSBzuAjywA:9 a=O8hF6Hzn-FEA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-GUID: N5KV9zvyewG3z3vzlTDDzymF0WKQp5SH X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODE5MDEyMCBTYWx0ZWRfX8S0IfeaQ+kEL PEtZY751LSf0K2INDC6AyJvSjtSaclB6AtQRvpstT4C7sQLijuVdJ5jKFMlBQ0nyKRWCWGDYv0T 3NmOwEDjJTrYVmj8lKn4CPi0SvqhH55B8yUPXzuiQXbj2HdqZ4PX5mUyUE99e4uhoQ8ZMt9DdXj OsRoREFh7gxWh/8OkjIsRjb45ZsWFoexuknM+ToakqLeOo2gdt8PEvvHrF+apG+uXKFsoHoIxtg l7+Tfk73wovtOs7gMONcfMj+uGIFmiplJCZp7LllGpZ9KERQYcsjQ7Fc7v5z1KM/9Xfq+6vbIZ0 Jtxljnw9ppEui2W3QwkhaIR2nwbuQ12tg5T7q8K2yqYna/HTC+5OgymlFabZh/ebveIBaxdRlzD xiqeE2QoPaHKeKYsgrVLnU0EdYNUBxQ7xpslsbX9D0dn5DIbWNfXHRdGB7uPq2Rdk4iKxgiHDwy IuqWADTmJ2pczBhu4MQ== X-Proofpoint-ORIG-GUID: N5KV9zvyewG3z3vzlTDDzymF0WKQp5SH X-Proofpoint-Spam-Info: AW1haW4tMjYwODE5MDEyMCBTYWx0ZWRfXwS4G1G2G+nFD wLUX00eVyOEI7HxXkx52qAlDYACPR2X798Ycl+W41j0Wk3rQUtmqjAdetwvItrLlYqCYTfFyyAO I8VpVWbU5dCGJ3FPK8K9VqxTRDlIKRY= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-19_04,2026-08-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 adultscore=0 priorityscore=1501 suspectscore=0 phishscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608190120 Content-Type: text/plain; charset="utf-8" QUP1 SE2 and SE3 pack all four of their lanes pair-wise onto only two pins each: lanes 0/1 (I2C SDA/SCL) at mux value 2 and lanes 2/3 (UART TX/RX) at mux value 1, on gpio127/gpio128 and gpio129/gpio130 respectively. Both mux values were named "qup1_se2" (respectively "qup1_se3"), so the two distinct lane pairs became indistinguishable. msm_pinmux_set_mux() stops at the first entry matching the requested function, which means mux value 1 was always selected and the I2C lanes could never be muxed out. In practice i2c9 and i2c10 got the UART lanes and did not work, while uart9 and uart10 happened to be muxed correctly. Give each lane pair its own function, following the _01/_23 naming already used for the same hardware arrangement by the shikra, eliza, hawi and maili TLMM drivers. Both functions still cover the full pin pair, so a single pinctrl state per protocol remains sufficient. Drop gpio129/gpio130 from the SE2 group list, since those pins belong to SE3 and were never reachable through the SE2 function. Also rename QUP1 SE2/SE3 functions in the binding doc accordingly. While at it, add missing QUP3 SE0 functions qup3_se0_mira and qup3_se0_mirb to the binding doc. Fixes: c24dd0826f06 ("pinctrl: qcom: add the TLMM driver for the Nord platf= orms") Cc: stable@vger.kernel.org Assisted-by: LLM Signed-off-by: Shawn Guo --- .../bindings/pinctrl/qcom,nord-tlmm.yaml | 5 +-- drivers/pinctrl/qcom/pinctrl-nord.c | 34 +++++++++++++------ 2 files changed, 26 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml = b/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml index 4bb511719f31..6b5ec9f49971 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml @@ -98,9 +98,10 @@ $defs: pcie3_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1, pwrbrk_i_n, qdss, qdss_cti, qspi, qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, qup0_se5, - qup1_se0, qup1_se1, qup1_se3, qup1_se2, qup1_se4, qup1_se5, + qup1_se0, qup1_se1, qup1_se2_01, qup1_se2_23, qup1_se3_01, + qup1_se3_23, qup1_se4, qup1_se5, qup1_se6, qup2_se0, qup2_se1, qup2_se2, qup2_se3, qup2_se4, - qup2_se5, qup2_se6, + qup2_se5, qup2_se6, qup3_se0_mira, qup3_se0_mirb, sailss_ospi, sdc4_clk, sdc4_cmd, sdc4_data, smb_alert, smb_alert_n, smb_clk, smb_dat, tb_trig_sdc4, tmess_prng0, tmess_prng1, tsc_timer, tsense_pwm, usb0_hs, diff --git a/drivers/pinctrl/qcom/pinctrl-nord.c b/drivers/pinctrl/qcom/pin= ctrl-nord.c index 7c21306e77ff..7f37f8e819ba 100644 --- a/drivers/pinctrl/qcom/pinctrl-nord.c +++ b/drivers/pinctrl/qcom/pinctrl-nord.c @@ -570,8 +570,10 @@ enum nord_functions { msm_mux_qup0_se5, msm_mux_qup1_se0, msm_mux_qup1_se1, - msm_mux_qup1_se2, - msm_mux_qup1_se3, + msm_mux_qup1_se2_01, + msm_mux_qup1_se2_23, + msm_mux_qup1_se3_01, + msm_mux_qup1_se3_23, msm_mux_qup1_se4, msm_mux_qup1_se5, msm_mux_qup1_se6, @@ -1152,11 +1154,19 @@ static const char *const qup1_se1_groups[] =3D { "gpio123", "gpio124", "gpio125", "gpio126", }; =20 -static const char *const qup1_se2_groups[] =3D { - "gpio127", "gpio128", "gpio129", "gpio130", +static const char *const qup1_se2_01_groups[] =3D { + "gpio127", "gpio128", }; =20 -static const char *const qup1_se3_groups[] =3D { +static const char *const qup1_se2_23_groups[] =3D { + "gpio127", "gpio128", +}; + +static const char *const qup1_se3_01_groups[] =3D { + "gpio129", "gpio130", +}; + +static const char *const qup1_se3_23_groups[] =3D { "gpio129", "gpio130", }; =20 @@ -1428,8 +1438,10 @@ static const struct pinfunction nord_functions[] =3D= { MSM_PIN_FUNCTION(qup0_se5), MSM_PIN_FUNCTION(qup1_se0), MSM_PIN_FUNCTION(qup1_se1), - MSM_PIN_FUNCTION(qup1_se2), - MSM_PIN_FUNCTION(qup1_se3), + MSM_PIN_FUNCTION(qup1_se2_01), + MSM_PIN_FUNCTION(qup1_se2_23), + MSM_PIN_FUNCTION(qup1_se3_01), + MSM_PIN_FUNCTION(qup1_se3_23), MSM_PIN_FUNCTION(qup1_se4), MSM_PIN_FUNCTION(qup1_se5), MSM_PIN_FUNCTION(qup1_se6), @@ -1633,13 +1645,13 @@ static const struct msm_pingroup nord_groups[] =3D { _, _, _, _, _, _, _), [126] =3D PINGROUP(126, qup1_se1, qup1_se0, ccu_i2c_scl, mdp1_vsync_out, _, atest_usb20, ddr_pxi, _, _, _, _), - [127] =3D PINGROUP(127, qup1_se2, qup1_se2, _, atest_usb21, ddr_pxi, + [127] =3D PINGROUP(127, qup1_se2_23, qup1_se2_01, _, atest_usb21, ddr_pxi, _, _, _, _, _, _), - [128] =3D PINGROUP(128, qup1_se2, qup1_se2, _, atest_usb20, ddr_pxi, + [128] =3D PINGROUP(128, qup1_se2_23, qup1_se2_01, _, atest_usb20, ddr_pxi, _, _, _, _, _, _), - [129] =3D PINGROUP(129, qup1_se3, qup1_se3, ccu_i2c_sda, mdp1_vsync_out, + [129] =3D PINGROUP(129, qup1_se3_23, qup1_se3_01, ccu_i2c_sda, mdp1_vsync= _out, _, atest_usb21, ddr_pxi, _, _, _, _), - [130] =3D PINGROUP(130, qup1_se3, qup1_se3, ccu_i2c_scl, mdp1_vsync_out, + [130] =3D PINGROUP(130, qup1_se3_23, qup1_se3_01, ccu_i2c_scl, mdp1_vsync= _out, _, atest_usb20, ddr_pxi, _, _, _, _), [131] =3D PINGROUP(131, qup1_se4, qup1_se6, ccu_i2c_sda, mdp1_vsync_out, _, atest_usb21, ddr_pxi, _, _, _, _), --=20 2.43.0