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charset="utf-8" Add binding for the Qualcomm CAMNOC interconnect provider. CAMNOC is the internal AXI interconnect within the camera subsystem. Multiple sub-devices share CAM_CC_CAMNOC_AXI_CLK; the ICC provider aggregates their bandwidth votes and scales the clock accordingly, avoiding the last-writer-wins race from direct clk_set_rate() calls. Signed-off-by: Atanas Filipov --- .../bindings/interconnect/qcom,camnoc.yaml | 124 ++++++++++++++++++ .../dt-bindings/interconnect/qcom,camnoc.h | 52 ++++++++ 2 files changed, 176 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,cam= noc.yaml create mode 100644 include/dt-bindings/interconnect/qcom,camnoc.h diff --git a/Documentation/devicetree/bindings/interconnect/qcom,camnoc.yam= l b/Documentation/devicetree/bindings/interconnect/qcom,camnoc.yaml new file mode 100644 index 000000000000..b2659db2cf27 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,camnoc.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,camnoc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera NOC (CAMNOC) Interconnect Provider + +maintainers: + - Atanas Filipov + +description: + The Camera Network-on-Chip (CAMNOC) is the internal AXI interconnect + within the Qualcomm camera subsystem. It arbitrates AXI bandwidth + between camera sub-devices (IFE, JPEG, BPS, IPE, etc.) and the external + memory interconnect. Multiple consumers may independently request + bandwidth via icc_set_bw(); the CAMNOC ICC provider aggregates all active + votes and scales CAM_CC_CAMNOC_AXI_CLK accordingly, avoiding the + last-writer-wins race that arises when each consumer calls clk_set_rate() + directly on the shared clock. + + Each camera sub-device driver that shares the CAMNOC AXI clock should + obtain an ICC path from its master port to SLAVE_CAMNOC_AXI and vote for + bandwidth using the port IDs defined in + include/dt-bindings/interconnect/qcom,camnoc.h. + +properties: + compatible: + enum: + - qcom,sm8250-cam-virt + + clocks: + items: + - description: CAMNOC AXI clock + + clock-names: + items: + - const: camnoc_axi + + '#interconnect-cells': + const: 1 + +required: + - compatible + - clocks + - clock-names + - '#interconnect-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + /* CAMNOC ICC provider node */ + cam_virt: interconnect-cam-virt { + compatible =3D "qcom,sm8250-cam-virt"; + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>; + clock-names =3D "camnoc_axi"; + #interconnect-cells =3D <1>; + }; + + /* + * Simple consumer example: IFE sub-device voting for CAMNOC bandwidth + * directly via icc_set_bw(). + */ + camera-ife@0 { + reg =3D <0x0 0x1000>; + + interconnects =3D <&cam_virt MASTER_CAMNOC_IFE_0 + &cam_virt SLAVE_CAMNOC_AXI>; + interconnect-names =3D "camnoc"; + }; + + /* + * OPP-based consumer example: JPEG encoder driving its CAMNOC bandwid= th + * vote from the same OPP entry that selects its core clock rate and + * RPMh performance state. opp-peak-kBps is the minimum CAMNOC bandwid= th + * required at each operating point; the actual value depends on the + * target resolution and quality settings. + * + * opp-hz refers to the JPEG dedicated core clock rate. All shared + * clocks (e.g. CAMNOC AXI) are managed by the ICC framework so that + * votes from multiple consumers are aggregated before the rate is + * applied to the hardware. + */ + camera-jpeg@ac53000 { + reg =3D <0x0ac53000 0x1000>; + + interconnects =3D <&cam_virt MASTER_CAMNOC_JPEG + &cam_virt SLAVE_CAMNOC_AXI>; + interconnect-names =3D "camnoc"; + + operating-points-v2 =3D <&jpeg_opp_table>; + + jpeg_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + opp-peak-kBps =3D <22246>; + required-opps =3D <&rpmhpd_opp_min_svs>; + }; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + opp-peak-kBps =3D <44492>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + opp-peak-kBps =3D <88983>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-480000000 { + opp-hz =3D /bits/ 64 <480000000>; + opp-peak-kBps =3D <106780>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; diff --git a/include/dt-bindings/interconnect/qcom,camnoc.h b/include/dt-bi= ndings/interconnect/qcom,camnoc.h new file mode 100644 index 000000000000..9b6468f852ec --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,camnoc.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_CAMNOC_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_CAMNOC_H + +/* + * CAMNOC master port IDs for SM8250 (Kona). + * Each ID identifies a camera sub-device that can vote for CAMNOC AXI + * bandwidth via icc_set_bw(). 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Multiple camera sub-devices share CAM_CC_CAMNOC_AXI_CLK; direct clk_set_rate() calls from each consumer cause a last-writer-wins race. Each consumer obtains an ICC path to SLAVE_CAMNOC_AXI and votes via icc_set_bw(). The ICC core aggregates votes (max peak_bw) and the set() callback converts the result to clk_set_rate(). Consumers encode the required frequency as peak_bw in kBps. Signed-off-by: Atanas Filipov --- drivers/interconnect/qcom/Kconfig | 10 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/qcom-camnoc.c | 279 ++++++++++++++++++++++++ 3 files changed, 291 insertions(+) create mode 100644 drivers/interconnect/qcom/qcom-camnoc.c diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/= Kconfig index 5b8a094ca4ed..9d9d238019a0 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -135,6 +135,16 @@ config INTERCONNECT_QCOM_NORD the RPMh hardware and communicates via Bus Clock Manager (BCM) through the Resource State Coordinator (RSC). =20 +config INTERCONNECT_QCOM_CAMNOC + tristate "Qualcomm CAMNOC interconnect driver" + depends on INTERCONNECT_QCOM || COMPILE_TEST + depends on ARM64 || COMPILE_TEST + help + Say y here to support the Camera Network-on-Chip (CAMNOC) + interconnect driver for Qualcomm SoCs. It aggregates bandwidth + requests from camera sub-devices (IFE, JPEG, BPS, etc.) and + scales CAM_CC_CAMNOC_AXI_CLK accordingly. + config INTERCONNECT_QCOM_OSM_L3 tristate "Qualcomm OSM L3 interconnect driver" depends on INTERCONNECT_QCOM || COMPILE_TEST diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom= /Makefile index 1c7d410b40cc..52a5998ae6a8 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -18,6 +18,7 @@ qnoc-msm8974-objs :=3D msm8974.o qnoc-msm8976-objs :=3D msm8976.o qnoc-msm8996-objs :=3D msm8996.o qnoc-nord-objs :=3D nord.o +icc-camnoc-objs :=3D qcom-camnoc.o icc-osm-l3-objs :=3D osm-l3.o qnoc-qcm2290-objs :=3D qcm2290.o qnoc-qcs404-objs :=3D qcs404.o @@ -66,6 +67,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_MSM8974) +=3D qnoc-msm8974= .o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8976) +=3D qnoc-msm8976.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8996) +=3D qnoc-msm8996.o obj-$(CONFIG_INTERCONNECT_QCOM_NORD) +=3D qnoc-nord.o +obj-$(CONFIG_INTERCONNECT_QCOM_CAMNOC) +=3D icc-camnoc.o obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) +=3D icc-osm-l3.o obj-$(CONFIG_INTERCONNECT_QCOM_QCM2290) +=3D qnoc-qcm2290.o obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) +=3D qnoc-qcs404.o diff --git a/drivers/interconnect/qcom/qcom-camnoc.c b/drivers/interconnect= /qcom/qcom-camnoc.c new file mode 100644 index 000000000000..9a703b052b2d --- /dev/null +++ b/drivers/interconnect/qcom/qcom-camnoc.c @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * Qualcomm Camera NOC (CAMNOC) interconnect provider. + * + * CAMNOC is the internal AXI interconnect within the Qualcomm camera + * subsystem. Multiple camera sub-devices (IFE, JPEG, BPS, etc.) share + * CAM_CC_CAMNOC_AXI_CLK. This driver acts as an ICC provider so that + * each sub-device can independently vote for bandwidth; the ICC core + * aggregates the votes (max of peak_bw across all consumers) and this + * driver translates the result into a clk_set_rate() call, avoiding + * the last-writer-wins race that occurs with direct clk_set_rate(). + * + * Consumers express their required clock rate directly as peak_bw in + * kBps (e.g. 400000 for 400 MHz). The driver converts kBps =E2=86=92 Hz: + * rate_hz =3D peak_bw_kBps * 1000 + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define to_camnoc_provider(_p) \ + container_of(_p, struct qcom_camnoc_icc_provider, provider) + +struct qcom_camnoc_icc_provider { + struct clk *clk; + struct icc_provider provider; +}; + +struct qcom_camnoc_node { + const char *name; + u16 buswidth; +}; + +/* IFE */ +static const struct qcom_camnoc_node camnoc_master_ife_0 =3D { + .name =3D "master-camnoc-ife-0", .buswidth =3D 16 +}; + +static const struct qcom_camnoc_node camnoc_master_ife_0_rdi =3D { + .name =3D "master-camnoc-ife-0-rdi", .buswidth =3D 16 +}; + +static const struct qcom_camnoc_node camnoc_master_ife_1 =3D { + .name =3D "master-camnoc-ife-1", .buswidth =3D 16 +}; + +static const struct qcom_camnoc_node camnoc_master_ife_1_rdi =3D { + .name =3D "master-camnoc-ife-1-rdi", .buswidth =3D 16 +}; + +static const struct qcom_camnoc_node camnoc_master_ife_lite_0 =3D { + .name =3D "master-camnoc-ife-lite-0", .buswidth =3D 8 +}; + +static const struct qcom_camnoc_node camnoc_master_ife_lite_1 =3D { + .name =3D "master-camnoc-ife-lite-1", .buswidth =3D 8 +}; + +static const struct qcom_camnoc_node camnoc_master_ife_lite_2 =3D { + .name =3D "master-camnoc-ife-lite-2", .buswidth =3D 8 +}; + +static const struct qcom_camnoc_node camnoc_master_ife_lite_3 =3D { + .name =3D "master-camnoc-ife-lite-3", .buswidth =3D 8 +}; + +static const struct qcom_camnoc_node camnoc_master_ife_lite_4 =3D { + .name =3D "master-camnoc-ife-lite-4", .buswidth =3D 8 +}; + +/* BPS */ +static const struct qcom_camnoc_node camnoc_master_bps =3D { + .name =3D "master-camnoc-bps", .buswidth =3D 16 +}; + +/* IPE */ +static const struct qcom_camnoc_node camnoc_master_ipe_0 =3D { + .name =3D "master-camnoc-ipe-0", .buswidth =3D 16 +}; + +static const struct qcom_camnoc_node camnoc_master_ipe_1 =3D { + .name =3D "master-camnoc-ipe-1", .buswidth =3D 16 +}; + +/* JPEG */ +static const struct qcom_camnoc_node camnoc_master_jpeg =3D { + .name =3D "master-camnoc-jpeg", .buswidth =3D 16 +}; + +static const struct qcom_camnoc_node camnoc_master_jpeg_dma =3D { + .name =3D "master-camnoc-jpeg-dma", .buswidth =3D 16 +}; + +/* CDM */ +static const struct qcom_camnoc_node camnoc_master_cdm =3D { + .name =3D "master-camnoc-cdm", .buswidth =3D 4 +}; + +/* FD */ +static const struct qcom_camnoc_node camnoc_master_fd =3D { + .name =3D "master-camnoc-fd", .buswidth =3D 16 +}; + +/* SBI */ +static const struct qcom_camnoc_node camnoc_master_sbi =3D { + .name =3D "master-camnoc-sbi", .buswidth =3D 16 +}; + +/* ICP */ +static const struct qcom_camnoc_node camnoc_master_icp =3D { + .name =3D "master-camnoc-icp", .buswidth =3D 8 +}; + +/* Slave */ +static const struct qcom_camnoc_node camnoc_slave_axi =3D { + .name =3D "slave-camnoc-axi", .buswidth =3D 32 +}; + +static const struct qcom_camnoc_node * const camnoc_nodes[] =3D { + [MASTER_CAMNOC_IFE_0] =3D &camnoc_master_ife_0, + [MASTER_CAMNOC_IFE_0_RDI] =3D &camnoc_master_ife_0_rdi, + [MASTER_CAMNOC_IFE_1] =3D &camnoc_master_ife_1, + [MASTER_CAMNOC_IFE_1_RDI] =3D &camnoc_master_ife_1_rdi, + [MASTER_CAMNOC_IFE_LITE_0] =3D &camnoc_master_ife_lite_0, + [MASTER_CAMNOC_IFE_LITE_1] =3D &camnoc_master_ife_lite_1, + [MASTER_CAMNOC_IFE_LITE_2] =3D &camnoc_master_ife_lite_2, + [MASTER_CAMNOC_IFE_LITE_3] =3D &camnoc_master_ife_lite_3, + [MASTER_CAMNOC_IFE_LITE_4] =3D &camnoc_master_ife_lite_4, + [MASTER_CAMNOC_BPS] =3D &camnoc_master_bps, + [MASTER_CAMNOC_IPE_0] =3D &camnoc_master_ipe_0, + [MASTER_CAMNOC_IPE_1] =3D &camnoc_master_ipe_1, + [MASTER_CAMNOC_JPEG] =3D &camnoc_master_jpeg, + [MASTER_CAMNOC_JPEG_DMA] =3D &camnoc_master_jpeg_dma, + [MASTER_CAMNOC_CDM] =3D &camnoc_master_cdm, + [MASTER_CAMNOC_FD] =3D &camnoc_master_fd, + [MASTER_CAMNOC_SBI] =3D &camnoc_master_sbi, + [MASTER_CAMNOC_ICP] =3D &camnoc_master_icp, + [SLAVE_CAMNOC_AXI] =3D &camnoc_slave_axi, +}; + +#define CAMNOC_NUM_NODES ARRAY_SIZE(camnoc_nodes) + +static int qcom_camnoc_get_bw(struct icc_node *node, u32 *avg, u32 *peak) +{ + *avg =3D 0; + *peak =3D 0; + + return 0; +} + +static int qcom_camnoc_set(struct icc_node *src, struct icc_node *dst) +{ + struct qcom_camnoc_icc_provider *cp =3D + to_camnoc_provider(src->provider); + unsigned long rate; + + /* + * peak_bw is the aggregated max across all consumers (kBps). + * Consumers encode the required clock frequency directly as kBps, + * so the conversion is simply: rate_hz =3D peak_bw * 1000. + * A vote of 0 means no requirement; leave the clock at its minimum. + */ + rate =3D icc_units_to_bps(dst->peak_bw); + + return clk_set_rate(cp->clk, rate); +} + +static void qcom_camnoc_remove(struct platform_device *pdev) +{ + struct qcom_camnoc_icc_provider *cp =3D platform_get_drvdata(pdev); + + icc_provider_deregister(&cp->provider); + icc_nodes_remove(&cp->provider); +} + +static int qcom_camnoc_probe(struct platform_device *pdev) +{ + struct qcom_camnoc_icc_provider *cp; + struct icc_onecell_data *data; + struct icc_provider *provider; + struct icc_node *node; + unsigned int i; + int ret; + + cp =3D devm_kzalloc(&pdev->dev, sizeof(*cp), GFP_KERNEL); + if (!cp) + return -ENOMEM; + + cp->clk =3D devm_clk_get(&pdev->dev, "camnoc_axi"); + if (IS_ERR(cp->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(cp->clk), + "failed to get camnoc_axi clock\n"); + + data =3D devm_kzalloc(&pdev->dev, + struct_size(data, nodes, CAMNOC_NUM_NODES), + GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->num_nodes =3D CAMNOC_NUM_NODES; + + provider =3D &cp->provider; + provider->dev =3D &pdev->dev; + provider->get_bw =3D qcom_camnoc_get_bw; + provider->set =3D qcom_camnoc_set; + provider->aggregate =3D icc_std_aggregate; + provider->xlate =3D of_icc_xlate_onecell; + provider->data =3D data; + + icc_provider_init(provider); + + for (i =3D 0; i < CAMNOC_NUM_NODES; i++) { + node =3D icc_node_create_dyn(); + if (IS_ERR(node)) { + ret =3D PTR_ERR(node); + goto err_remove; + } + + ret =3D icc_node_set_name(node, provider, camnoc_nodes[i]->name); + if (ret) { + icc_node_destroy(node->id); + goto err_remove; + } + + node->data =3D (void *)camnoc_nodes[i]; + icc_node_add(node, provider); + data->nodes[i] =3D node; + } + + /* Link every master to the single CAMNOC AXI slave. */ + for (i =3D 0; i < CAMNOC_NUM_NODES - 1; i++) { + if (camnoc_nodes[i] =3D=3D &camnoc_slave_axi) + continue; + ret =3D icc_link_nodes(data->nodes[i], + &data->nodes[SLAVE_CAMNOC_AXI]); + if (ret) + goto err_remove; + } + + ret =3D icc_provider_register(provider); + if (ret) + goto err_remove; + + platform_set_drvdata(pdev, cp); + + return 0; + +err_remove: + icc_nodes_remove(provider); + return ret; +} + +static const struct of_device_id qcom_camnoc_of_match[] =3D { + { .compatible =3D "qcom,sm8250-cam-virt" }, + { } +}; +MODULE_DEVICE_TABLE(of, qcom_camnoc_of_match); + +static struct platform_driver qcom_camnoc_driver =3D { + .probe =3D qcom_camnoc_probe, + .remove =3D qcom_camnoc_remove, + .driver =3D { + .name =3D "qcom-camnoc-icc", + .of_match_table =3D qcom_camnoc_of_match, + .sync_state =3D icc_sync_state, + }, +}; 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charset="utf-8" Add the cam_virt CAMNOC ICC provider node alongside the other virtual interconnect nodes in the SM8250 DTSI. Signed-off-by: Atanas Filipov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qco= m/sm8250.dtsi index 7076720413ab..33535c83a4d9 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -377,6 +378,13 @@ qup_virt: interconnect-qup-virt { qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + cam_virt: interconnect-cam-virt { + compatible =3D "qcom,sm8250-cam-virt"; + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>; + clock-names =3D "camnoc_axi"; + #interconnect-cells =3D <1>; + }; + cpu0_opp_table: opp-table-cpu0 { compatible =3D "operating-points-v2"; opp-shared; --=20 2.34.1