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charset="utf-8" As per, 'Designware Cores PCI Express DM Controller - Reference Manual', section 3.2.34.3, VSEC for DEVICE INFORMATION supports the channel separation mechanisms. Basically, the HDMA IP allows the user to configure the separation between DMA channel registers and retrieve it via the VSEC capability mentioned above. HDMA IP supports the channel register space separation from 256B to 32KB. Default supported size is 256B. Signed-off-by: Devendra K Verma Reviewed-by: Frank Li --- Changes in v3: o Reverted the trivial changes / typos. Changes in v2: o Replaced 'ch_sep_sz' with 'ch_space_sz' wherever applicable upon reviewer recommendation. o Dropped 1/3 patch of this series, after review, now the 2/3 is 1/2 of the current patch series. Changes in v1: o Modified dw_edma_get_ch_sep_sz() as per review comment. The function now supports ch_sep_sz up to 32KB. o Updated to description to reflect the supported channel separation sizes. --- drivers/dma/dw-edma/dw-edma-pcie.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-ed= ma-pcie.c index 791c46e8ae4c..f287879b2cb9 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -33,6 +33,8 @@ #define DW_PCIE_XILINX_MDB_VSEC_ID 0x20 #define DW_PCIE_XILINX_MDB_VSEC_DMA_BAR GENMASK(10, 8) #define DW_PCIE_XILINX_MDB_VSEC_DMA_MAP GENMASK(2, 0) +/* AMD CPM6 (Xilinx) supported cap */ +#define DW_PCIE_XILINX_CPM6_VSEC_CH_SEP GENMASK(18, 16) #define DW_PCIE_XILINX_MDB_VSEC_DMA_WR_CH GENMASK(9, 0) #define DW_PCIE_XILINX_MDB_VSEC_DMA_RD_CH GENMASK(25, 16) =20 @@ -73,6 +75,7 @@ struct dw_edma_pcie_data { u16 wr_ch_cnt; u16 rd_ch_cnt; u64 devmem_phys_off; + u32 ch_space_sz; }; =20 static const struct dw_edma_pcie_data snps_edda_data =3D { @@ -189,6 +192,13 @@ static int dw_edma_pcie_irq_vector(struct device *dev,= unsigned int nr) return pci_irq_vector(to_pci_dev(dev), nr); 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charset="utf-8" HDMA supports configurable DMA channel register space separation which ranges from 256B to 32KB. Current implementation supports 256B as default for DMA channel register space. CPM6 supports the selection of channel register space via VSEC. The default value for channel register space for CPM6 is 512B. Updated the functions and methods to calculate the DMA channel registers base address as per the selected channel separation available as part of 'ch_space_sz'. Removed the unused function __dw_regs() and structs, namely dw_hdma_v0_ch and dw_hdma_v0_regs. Signed-off-by: Devendra K Verma Reviewed-by: Frank Li --- Changes in v3: o No change. Changes in v2: o Replace 'ch_sep_sz' with 'ch_space_sz' as per review recommendations. o As patch 1/3 of previous series dropped after review, this patch becomes 2/2 of the current series. Changes in v1: o Updated the description as per the review comment o Updated ch_sep_sz for EPC driver. --- drivers/dma/dw-edma/dw-edma-pcie.c | 4 ++++ drivers/dma/dw-edma/dw-hdma-v0-core.c | 23 ++++++++++++-------- drivers/dma/dw-edma/dw-hdma-v0-debugfs.c | 17 +++++---------- drivers/dma/dw-edma/dw-hdma-v0-regs.h | 10 --------- drivers/pci/controller/dwc/pcie-designware.c | 1 + include/linux/dma/edma.h | 1 + 6 files changed, 26 insertions(+), 30 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-ed= ma-pcie.c index f287879b2cb9..2eb8293b87b4 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -114,6 +114,7 @@ static const struct dw_edma_pcie_data snps_edda_data = =3D { .irqs =3D 1, .wr_ch_cnt =3D 2, .rd_ch_cnt =3D 2, + .ch_space_sz =3D 256, }; =20 static const struct dw_edma_pcie_data xilinx_mdb_data =3D { @@ -127,6 +128,7 @@ static const struct dw_edma_pcie_data xilinx_mdb_data = =3D { .irqs =3D 1, .wr_ch_cnt =3D 8, .rd_ch_cnt =3D 8, + .ch_space_sz =3D 256, }; =20 static const struct dw_edma_pcie_data xilinx_cpm6_dma_data =3D { @@ -140,6 +142,7 @@ static const struct dw_edma_pcie_data xilinx_cpm6_dma_d= ata =3D { .irqs =3D 1, .wr_ch_cnt =3D 8, .rd_ch_cnt =3D 8, + .ch_space_sz =3D 512, }; =20 static void dw_edma_set_chan_region_offset(struct dw_edma_pcie_data *pdata, @@ -436,6 +439,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, chip->nr_irqs =3D nr_irqs; chip->ops =3D &dw_edma_pcie_plat_ops; chip->cfg_non_ll =3D non_ll; + chip->ch_space_sz =3D vsec_data->ch_space_sz; =20 chip->ll_wr_cnt =3D vsec_data->wr_ch_cnt; chip->ll_rd_cnt =3D vsec_data->rd_ch_cnt; diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw= -hdma-v0-core.c index 632abb8b481c..f8b2383b294a 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c @@ -23,18 +23,23 @@ enum dw_hdma_control { DW_HDMA_V0_LLE =3D BIT(9), }; =20 -static inline struct dw_hdma_v0_regs __iomem *__dw_regs(struct dw_edma *dw) -{ - return dw->chip->reg_base; -} - static inline struct dw_hdma_v0_ch_regs __iomem * __dw_ch_regs(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch) { - if (dir =3D=3D EDMA_DIR_WRITE) - return &(__dw_regs(dw)->ch[ch].wr); - else - return &(__dw_regs(dw)->ch[ch].rd); + u32 ch_base; + + /* + * For Write, the channel register index starts at + * wr_base(ch_idx) =3D (2 * ch_idx) * ch_space_sz + * + * For Read channel, + * rd_base(ch_idx) =3D (2 * ch_idx + 1) * ch_space_sz + */ + ch_base =3D 2 * ch; + if (dir =3D=3D EDMA_DIR_READ) + ch_base +=3D 1; + + return dw->chip->reg_base + (ch_base * dw->chip->ch_space_sz); } =20 #define SET_CH_32(dw, dir, ch, name, value) \ diff --git a/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c b/drivers/dma/dw-edma= /dw-hdma-v0-debugfs.c index dcdc57fe976c..3fa16e045a58 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c @@ -13,22 +13,17 @@ #include "dw-hdma-v0-regs.h" #include "dw-edma-core.h" =20 -#define REGS_ADDR(dw, name) \ - ({ \ - struct dw_hdma_v0_regs __iomem *__regs =3D (dw)->chip->reg_base; \ - \ - (void __iomem *)&__regs->name; \ - }) - #define REGS_CH_ADDR(dw, name, _dir, _ch) \ ({ \ - struct dw_hdma_v0_ch_regs __iomem *__ch_regs; \ + struct dw_hdma_v0_ch_regs __iomem *__ch_regs; \ + off_t __off =3D (dw)->chip->ch_space_sz; \ \ - if (_dir =3D=3D EDMA_DIR_READ) \ - __ch_regs =3D REGS_ADDR(dw, ch[_ch].rd); \ + if ((_dir) =3D=3D EDMA_DIR_READ) \ + __off *=3D (2 * (_ch) + 1); \ else \ - __ch_regs =3D REGS_ADDR(dw, ch[_ch].wr); \ + __off *=3D (2 * (_ch)); \ \ + __ch_regs =3D ((dw)->chip->reg_base + __off); \ (void __iomem *)&__ch_regs->name; \ }) =20 diff --git a/drivers/dma/dw-edma/dw-hdma-v0-regs.h b/drivers/dma/dw-edma/dw= -hdma-v0-regs.h index 7759ba9b4850..2475b8d96133 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-regs.h +++ b/drivers/dma/dw-edma/dw-hdma-v0-regs.h @@ -84,16 +84,6 @@ struct dw_hdma_v0_ch_regs { }; } msi_abort; u32 msi_msgdata; /* 0x00a8 */ - u32 padding_2[21]; /* 0x00ac..0x00fc */ -} __packed; - -struct dw_hdma_v0_ch { - struct dw_hdma_v0_ch_regs wr; /* 0x0000 */ - struct dw_hdma_v0_ch_regs rd; /* 0x0100 */ -} __packed; - -struct dw_hdma_v0_regs { - struct dw_hdma_v0_ch ch[HDMA_V0_MAX_NR_CH]; /* 0x0000..0x0fa8 */ } __packed; =20 struct dw_hdma_v0_lli { diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index ec4722ed9303..dfb7deaff751 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -1049,6 +1049,7 @@ static void dw_pcie_edma_init_data(struct dw_pcie *pc= i) pci->edma.ops =3D &dw_pcie_edma_ops; =20 pci->edma.flags |=3D DW_EDMA_CHIP_LOCAL; + pci->edma.ch_space_sz =3D 256; } =20 static int dw_pcie_edma_find_mf(struct dw_pcie *pci) diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index 1fafd5b0e315..182d4eeae22a 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -104,6 +104,7 @@ struct dw_edma_chip { =20 struct dw_edma *dw; bool cfg_non_ll; + u32 ch_space_sz; }; =20 /* Export to the platform drivers */ --=20 2.43.0