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(unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id 8B6863F7057; Mon, 17 Aug 2026 20:47:30 -0700 (PDT) From: Ratheesh Kannoth To: , , , , CC: , , , , , , "Ratheesh Kannoth" Subject: [PATCH net] octeontx2: fix PTP RX enable mbox failure on VF Date: Tue, 18 Aug 2026 09:17:28 +0530 Message-ID: <20260818034728.2047614-1-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=Q7LiJY2a c=1 sm=1 tr=0 ts=6a83d5d7 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=qit2iCtTFQkLgVSMPQTB:22 a=M5GUcnROAAAA:8 a=NHMKxiKwEXHd31jJAx8A:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: YIrPYyh6SwbyN8IKB9vwdKSH8epDZ8IU X-Proofpoint-Spam-Info: AW1haW4tMjYwODE4MDAyNSBTYWx0ZWRfX8OF5mAbztc8J yl5ejeRpzhdoaHouUh187S0cZbcX5XZuczyDvoSpKDhnmQaNZPbE2o2DxD+43Y3CQ9BNP7jgRv2 xCQmdM6nOlLh2UjLRGPcMSk+lHDgxAE= X-Proofpoint-GUID: YIrPYyh6SwbyN8IKB9vwdKSH8epDZ8IU X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODE4MDAyNSBTYWx0ZWRfX15aWy75jGkZm KnPejDczn5hQdJW677rpOMWlp86Po29Sihzc01XV9qA06ij1i+3t+IyMZ94uI9MCFGdTLFRHrjc WJETuCiqygyhQ9/rtgthmYOcSaJ81Y3WYucWV4XpUhQ87wDIjzBjNTKaDmRlwIxrzNFfj3U7PUW FNNgZTNfSTEkPIXTEmJ9FBzikdBPhlaw6qw/1fPmjsawKISkE5ajzi5QlLU8LUWJV1QHtwpvj/e HqLOtce5EubvluDAGW/dsViXXO3S5VCfmLIm2VjGeLnzrgJYFEf9sa7cOdZ+HiqieUmGyiUqm7n 1uPdWJ3uZkmiSGO8UlL1xVKb0kX/q0+D3XUGQNIxgMrIp+RciAKQZSnM9fmjA4j9hcwEtc6tXNh groRwcfXgoaHo0NpjrosoPhkoqboFbMNKW6s4IwTfRGO0t4RW1Z302wulaUKeNhWGpGww+yzfl/ XvsLsjZp1bJzAtbQSow== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-17_04,2026-08-12_01,2025-10-01_01 Content-Type: text/plain; charset="utf-8" From: Sai Krishna When a VF enables PTP RX timestamping, the AF must notify the parent PF so it can adjust its RX data offset before CGX prepends the 8-byte timestamp header. Use the correct upcall mailbox pattern (wait for zero, then msg_send_up) instead of msg_send/wait_for_rsp, which causes the mbox to fail on VF. Add the CGX_PTP_RX_INFO upcall message and PF/VF handlers to propagate the PTP enable state to VFs. Fixes: 30e7ecb6441d ("octeontx2-af: Support for PTP notification to PF") Signed-off-by: Sai Krishna Signed-off-by: Ratheesh Kannoth --- .../net/ethernet/marvell/octeontx2/af/mbox.h | 8 ++- .../ethernet/marvell/octeontx2/af/rvu_cgx.c | 20 +++++++ .../marvell/octeontx2/nic/otx2_common.h | 2 + .../ethernet/marvell/octeontx2/nic/otx2_pf.c | 59 +++++++++++++++++++ .../ethernet/marvell/octeontx2/nic/otx2_vf.c | 14 +++++ 5 files changed, 102 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net= /ethernet/marvell/octeontx2/af/mbox.h index 714e47f68d93..96e1b93f8122 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -427,7 +427,8 @@ M(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_ge= t, \ =20 /* Messages initiated by AF (range 0xC00 - 0xEFF) */ #define MBOX_UP_CGX_MESSAGES \ -M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) +M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) \ +M(CGX_PTP_RX_INFO, 0xC01, cgx_ptp_rx_info, cgx_ptp_rx_info_msg, msg_rsp) =20 #define MBOX_UP_CPT_MESSAGES \ M(CPT_INST_LMTST, 0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp) @@ -647,6 +648,11 @@ struct cgx_link_info_msg { struct cgx_link_user_info link_info; }; =20 +struct cgx_ptp_rx_info_msg { + struct mbox_msghdr hdr; + u8 ptp_en; +}; + struct cgx_pause_frm_cfg { struct mbox_msghdr hdr; u8 set; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_cgx.c index 87d21889dc49..cb95f3fb60ae 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c @@ -820,6 +820,24 @@ int rvu_mbox_handler_cgx_promisc_disable(struct rvu *r= vu, struct msg_req *req, return 0; } =20 +static void cgx_notify_up_ptp_info(struct rvu *rvu, int pf, bool enable) +{ + struct cgx_ptp_rx_info_msg *msg; + + /* Send mbox message to PF */ + msg =3D otx2_mbox_alloc_msg_cgx_ptp_rx_info(rvu, pf); + if (!msg) { + dev_err(rvu->dev, "failed to alloc message\n"); + return; + } + + msg->ptp_en =3D enable; + + otx2_mbox_wait_for_zero(&rvu->afpf_wq_info.mbox_up, pf); + + otx2_mbox_msg_send_up(&rvu->afpf_wq_info.mbox_up, pf); +} + static int rvu_cgx_ptp_rx_cfg(struct rvu *rvu, u16 pcifunc, bool enable) { struct rvu_pfvf *pfvf =3D rvu_get_pfvf(rvu, pcifunc); @@ -837,6 +855,8 @@ static int rvu_cgx_ptp_rx_cfg(struct rvu *rvu, u16 pcif= unc, bool enable) if (!is_pf_cgxmapped(rvu, pf)) return -EPERM; =20 + cgx_notify_up_ptp_info(rvu, pf, enable); + rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); cgxd =3D rvu_cgx_pdata(cgx_id, rvu); =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/dri= vers/net/ethernet/marvell/octeontx2/nic/otx2_common.h index eecee612b7b2..13b54287facf 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h @@ -286,6 +286,7 @@ enum vfperm { struct otx2_vf_config { struct otx2_nic *pf; struct delayed_work link_event_work; + struct delayed_work ptp_info_work; bool intf_down; /* interface was either configured or not */ u8 mac[ETH_ALEN]; u16 vlan; @@ -324,6 +325,7 @@ struct otx2_ptp { u64 thresh; =20 struct ptp_pin_desc extts_config; + bool ptp_en; u64 (*convert_rx_ptp_tstmp)(u64 timestamp); u64 (*convert_tx_ptp_tstmp)(u64 timestamp); u64 (*ptp_tstamp2nsec)(const struct timecounter *time_counter, u64 timest= amp); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_pf.c index c995f2900859..8e2443041ee8 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c @@ -44,6 +44,7 @@ MODULE_LICENSE("GPL v2"); MODULE_DEVICE_TABLE(pci, otx2_pf_id_table); =20 static void otx2_vf_link_event_task(struct work_struct *work); +static void otx2_vf_ptp_info_task(struct work_struct *work); =20 enum { TYPE_PFAF, @@ -960,6 +961,30 @@ int otx2_mbox_up_handler_cgx_link_event(struct otx2_ni= c *pf, return 0; } =20 +int otx2_mbox_up_handler_cgx_ptp_rx_info(struct otx2_nic *pf, + struct cgx_ptp_rx_info_msg *msg, + struct msg_rsp *rsp) +{ + int i; + + if (!pf->ptp) + return 0; + + pf->ptp->ptp_en =3D msg->ptp_en; + + /* notify VFs about ptp event */ + for (i =3D 0; i < pci_num_vf(pf->pdev); i++) { + struct otx2_vf_config *config =3D &pf->vf_configs[i]; + struct delayed_work *dwork =3D &config->ptp_info_work; + + if (config->intf_down) + continue; + + schedule_delayed_work(dwork, msecs_to_jiffies(100)); + } + return 0; +} + static int otx2_process_mbox_msg_up(struct otx2_nic *pf, struct mbox_msghdr *req) { @@ -3041,6 +3066,8 @@ static int otx2_sriov_vfcfg_init(struct otx2_nic *pf) pf->vf_configs[i].trusted =3D false; INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work, otx2_vf_link_event_task); + INIT_DELAYED_WORK(&pf->vf_configs[i].ptp_info_work, + otx2_vf_ptp_info_task); } =20 return 0; @@ -3055,6 +3082,7 @@ static void otx2_sriov_vfcfg_cleanup(struct otx2_nic = *pf) =20 for (i =3D 0; i < pf->total_vfs; i++) { cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work); + cancel_delayed_work_sync(&pf->vf_configs[i].ptp_info_work); otx2_set_vf_permissions(pf, i, OTX2_RESET_VF_PERM); } } @@ -3417,6 +3445,37 @@ static void otx2_vf_link_event_task(struct work_stru= ct *work) mutex_unlock(&pf->mbox.lock); } =20 +static void otx2_vf_ptp_info_task(struct work_struct *work) +{ + struct cgx_ptp_rx_info_msg *req; + struct otx2_vf_config *config; + struct mbox_msghdr *msghdr; + struct otx2_nic *pf; + int vf_idx; + + config =3D container_of(work, struct otx2_vf_config, + ptp_info_work.work); + vf_idx =3D config - config->pf->vf_configs; + pf =3D config->pf; + + if (config->intf_down || !pf->ptp) + return; + + msghdr =3D otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx, + sizeof(*req), sizeof(struct msg_rsp)); + if (!msghdr) { + dev_err(pf->dev, "Failed to create VF%d ptp info event\n", vf_idx); + return; + } + + req =3D (struct cgx_ptp_rx_info_msg *)msghdr; + req->hdr.id =3D MBOX_MSG_CGX_PTP_RX_INFO; + req->hdr.sig =3D OTX2_MBOX_REQ_SIG; + req->ptp_en =3D pf->ptp->ptp_en; + + otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx); +} + static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs) { struct net_device *netdev =3D pci_get_drvdata(pdev); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_vf.c index b022f52c6845..60f81062007b 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c @@ -141,6 +141,20 @@ static int otx2vf_process_mbox_msg_up(struct otx2_nic = *vf, err =3D otx2_mbox_up_handler_cgx_link_event( vf, (struct cgx_link_info_msg *)req, rsp); return err; + case MBOX_MSG_CGX_PTP_RX_INFO: + rsp =3D (struct msg_rsp *)otx2_mbox_alloc_msg(&vf->mbox.mbox_up, + 0, sizeof(struct msg_rsp)); + if (!rsp) + return -ENOMEM; + + rsp->hdr.id =3D MBOX_MSG_CGX_PTP_RX_INFO; + rsp->hdr.sig =3D OTX2_MBOX_RSP_SIG; + rsp->hdr.pcifunc =3D req->pcifunc; + rsp->hdr.rc =3D 0; + err =3D otx2_mbox_up_handler_cgx_ptp_rx_info(vf, + (struct cgx_ptp_rx_info_msg *)req, + rsp); + return err; default: otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id); return -ENODEV; --=20 2.43.0