From nobody Mon Sep 28 18:33:30 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0B5B3672BD for ; Tue, 18 Aug 2026 21:50:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787089854; cv=none; b=TDlk4lhbykJB3cPlvP1y2BmIpbvK5HsBENQ147LAviLMosqm6CE9LZxyUQ6AecbFgoywr6Em8u0rbnHCtbYU6MnSj0y+djdY5sbX3k9iSt8kSUDwRJbCiFgKYHU/a7tjjTqM25tP3U5QKncsTN9LybjZN5ruzoHGplcLR6gdc20= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787089854; c=relaxed/simple; bh=uFxMqukVO5YlvxV5/cy9Ia3Ua//bTQISjjvkMZCr2V8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To; b=l4LCPa1PXaU16ZZFwN+x4O/uKH5G30D/++KzoXbPkL4T3Her8vGf/9zFS2YdtZvKGQw0II8jBk51Q1+490d/25ule/uIC9dMwzx4Y9MlYtqdiq0a6FoxnFosRAOwggQNg9jtStcBvMOAC2DL4SSyYnO+wjU4BOhBlOr5sH0iQMc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Dl/qm53z; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Dl/qm53z" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2190B1F00A3A; Tue, 18 Aug 2026 21:50:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1787089852; bh=Ry4QZbPnuEQxe4p4XNnGXWIIPWtSeHiaHlSEC8uvgLk=; h=From:Date:Subject:References:In-Reply-To:To; b=Dl/qm53zHh9GF6FcJ34/tRkRdaoW1NLKNFoa8THIN4RjHxLLQa6a/uT4vP3ITndfI zrvgnBOGOWwNH98twJ2eJEdd6q4VMjC7J2MCO/F1gVW8IM8keqT2alJSgnOB229F7g H/OVTNseU4q43EgVMQ1VHgPRsxXffp//XS5zMlW43aYLQk1IIjmqGf/xGPTG1PcIpb wwXDhLMIIdrH8sKLajI3tpljy5AZnnKnA2iLnFzC7nWhogbZc15ZzwlvGpO0kGnuqq kzvmEk1DMU+pEI3iE9VrMVSJwbUmbTgy8kNa3raHuiqCQqMl2ix3E+byzQN6L0Z+Eq Pml1lfh90pdbQ== From: Mark Brown Date: Tue, 18 Aug 2026 22:50:44 +0100 Subject: [PATCH 1/2] regmap: Allow a base register to be specified for the RAM regmap Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260818-regmap-kunit-cache-high-bit-v1-1-7e790676dea3@kernel.org> References: <20260818-regmap-kunit-cache-high-bit-v1-0-7e790676dea3@kernel.org> In-Reply-To: <20260818-regmap-kunit-cache-high-bit-v1-0-7e790676dea3@kernel.org> To: linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=4888; i=broonie@kernel.org; h=from:subject:message-id; bh=uFxMqukVO5YlvxV5/cy9Ia3Ua//bTQISjjvkMZCr2V8=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqhNO3LQ5hdmuEk+POYy5sg/Q6MzKCjie8NK5Bz /9KHsB2NmGJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaoTTtwAKCRAk1otyXVSH 0OVqB/wJPdJaQh9l8sMC2lef4p2a8/9OuflwUXzERQtfz+n9CQl/OZEGcRDH7+x7ORK3IxqMG+7 mDypjwig1t/C2PseXakqpKfvrMw97qAYsraXB+UI+FieaQEVS8GYvHaG31/38RxHD4lI5rOaXPW CwpKAdJ3LXNsRBf3ZMawijLvPVHPw+BRsJANzduqJHp9G53+4Asbc0bX/FyupwpBKQTlucAGpx0 6U1S3Rjj/WwFUsYqDch5qXElyqUK+9KckHrARyTFkzt9VbdQ6y0dlH/SgbJbMII5GNjxKiLTfNp GtBFCGHIX6asYu6wwDHzRcDIcKcvHKjDWdfnILRU5F1yeRuE X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB To allow testing of register maps with very large register values add support for specifying base address to the RAM regmap. Since the config struct is shared with the raw RAM regmap also update that, though we will not use it. Signed-off-by: Mark Brown --- drivers/base/regmap/internal.h | 1 + drivers/base/regmap/regmap-ram.c | 26 ++++++++++++++++++++------ drivers/base/regmap/regmap-raw-ram.c | 21 +++++++++++++-------- 3 files changed, 34 insertions(+), 14 deletions(-) diff --git a/drivers/base/regmap/internal.h b/drivers/base/regmap/internal.h index 55273a6178f8..8176d91aacd1 100644 --- a/drivers/base/regmap/internal.h +++ b/drivers/base/regmap/internal.h @@ -322,6 +322,7 @@ static inline unsigned int regcache_get_index_by_order(= const struct regmap *map, } =20 struct regmap_ram_data { + unsigned int base_reg; unsigned int *vals; /* Allocatd by caller */ bool *read; bool *written; diff --git a/drivers/base/regmap/regmap-ram.c b/drivers/base/regmap/regmap-= ram.c index c7356b0d8c83..a666bfb4d667 100644 --- a/drivers/base/regmap/regmap-ram.c +++ b/drivers/base/regmap/regmap-ram.c @@ -20,8 +20,11 @@ static int regmap_ram_write(void *context, unsigned int = reg, unsigned int val) { struct regmap_ram_data *data =3D context; =20 - data->vals[reg] =3D val; - data->written[reg] =3D true; + if (reg < data->base_reg) + return -EINVAL; + + data->vals[reg - data->base_reg] =3D val; + data->written[reg - data->base_reg] =3D true; =20 return 0; } @@ -30,8 +33,11 @@ static int regmap_ram_read(void *context, unsigned int r= eg, unsigned int *val) { struct regmap_ram_data *data =3D context; =20 - *val =3D data->vals[reg]; - data->read[reg] =3D true; + if (reg < data->base_reg) + return -EINVAL; + + *val =3D data->vals[reg - data->base_reg]; + data->read[reg - data->base_reg] =3D true; =20 return 0; } @@ -60,17 +66,25 @@ struct regmap *__regmap_init_ram(struct device *dev, const char *lock_name) { struct regmap *map; + unsigned int num_regs; =20 if (!config->max_register) { pr_crit("No max_register specified for RAM regmap\n"); return ERR_PTR(-EINVAL); } =20 - data->read =3D kzalloc_objs(bool, config->max_register + 1); + if (data->base_reg > config->max_register) { + pr_crit("base_reg above max_register for RAM regmap\n"); + return ERR_PTR(-EINVAL); + } + + num_regs =3D config->max_register - data->base_reg + 1; + + data->read =3D kzalloc_objs(bool, num_regs); if (!data->read) return ERR_PTR(-ENOMEM); =20 - data->written =3D kzalloc_objs(bool, config->max_register + 1); + data->written =3D kzalloc_objs(bool, num_regs); if (!data->written) { kfree(data->read); return ERR_PTR(-ENOMEM); diff --git a/drivers/base/regmap/regmap-raw-ram.c b/drivers/base/regmap/reg= map-raw-ram.c index 60d6e95cdd1b..c63c464549f9 100644 --- a/drivers/base/regmap/regmap-raw-ram.c +++ b/drivers/base/regmap/regmap-raw-ram.c @@ -16,14 +16,17 @@ =20 #include "internal.h" =20 -static unsigned int decode_reg(enum regmap_endian endian, const void *reg) +static unsigned int decode_reg(struct regmap_ram_data *data, const void *r= eg) { const u16 *r =3D reg; + unsigned int decode; =20 - if (endian =3D=3D REGMAP_ENDIAN_BIG) - return be16_to_cpu(*r); + if (data->reg_endian =3D=3D REGMAP_ENDIAN_BIG) + decode =3D be16_to_cpu(*r); else - return le16_to_cpu(*r); + decode =3D le16_to_cpu(*r); + + return decode - data->base_reg; } =20 static int regmap_raw_ram_gather_write(void *context, @@ -40,7 +43,7 @@ static int regmap_raw_ram_gather_write(void *context, if (val_len % 2) return -EINVAL; =20 - r =3D decode_reg(data->reg_endian, reg); + r =3D decode_reg(data, reg); if (data->noinc_reg && data->noinc_reg(data, r)) { memcpy(&our_buf[r], val + val_len - 2, 2); data->written[r] =3D true; @@ -74,7 +77,7 @@ static int regmap_raw_ram_read(void *context, if (val_len % 2) return -EINVAL; =20 - r =3D decode_reg(data->reg_endian, reg); + r =3D decode_reg(data, reg); if (data->noinc_reg && data->noinc_reg(data, r)) { for (i =3D 0; i < val_len; i +=3D 2) memcpy(val + i, &our_buf[r], 2); @@ -114,6 +117,7 @@ struct regmap *__regmap_init_raw_ram(struct device *dev, const char *lock_name) { struct regmap *map; + unsigned int regs; =20 if (config->reg_bits !=3D 16) return ERR_PTR(-EINVAL); @@ -123,11 +127,12 @@ struct regmap *__regmap_init_raw_ram(struct device *d= ev, return ERR_PTR(-EINVAL); } =20 - data->read =3D kzalloc_objs(bool, config->max_register + 1); + regs =3D config->max_register - data->base_reg + 1; + data->read =3D kzalloc_objs(bool, regs); if (!data->read) return ERR_PTR(-ENOMEM); =20 - data->written =3D kzalloc_objs(bool, config->max_register + 1); + data->written =3D kzalloc_objs(bool, regs); if (!data->written) return ERR_PTR(-ENOMEM); =20 --=20 2.47.3 From nobody Mon Sep 28 18:33:30 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1B9337E2E6 for ; Tue, 18 Aug 2026 21:50:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787089855; cv=none; b=Z14gS3VZdBQAFu2ng1zLtSsFdddaL2srzD4OxaJ1Tn5pefqy7NNlLKWoGj/2urx7t+5BpOQdC1rCFjKY29q0j/KGNsOY9ENtf2vKhB2PwYphnaYXmwYpE0sIp8Yd6DdqupWRCySHWZi7YBZAK1cuK9YCCt7UARx2RIkxstTtnM4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787089855; c=relaxed/simple; bh=vM1lEckXpzDMDzKpUFoITsQjjvej9YM73RqUS3ThRzM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To; b=c86Hl9YIjJdgDNP8kDBNeOn85IhivdLs4pF3QqWTE5mIXl5y2z+G9K/WzWLJY5PlUAFJWGMFjt2wwq6UCZOpVkN74QuiER778FPDs0z+/Oc22AbWZ+zCK681MhHv7NIoqaZALd/Vi0CF4d8CdAjYywXgls30ERZqkLQY5ipd8es= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XtkqCpNA; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XtkqCpNA" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F385D1F00A3D; Tue, 18 Aug 2026 21:50:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1787089853; bh=z7SRpwND44jkkKE7JeR8nJT3Jqa/xRKwaSwS44mWxRg=; h=From:Date:Subject:References:In-Reply-To:To; b=XtkqCpNA7Fv+lqkeE43NPfS0n+fhhMNFvTrl98MQR5sou7hNnFTTAWdT+owxlkdde tDvEtKNCmVqYIjCX+itWvaQ04tsKehHik7T9W2HaAu67LgUBdo/eo6C1vL/sDMl85B zroZztgj+R4TsWqz2tpFCwAfZ09AR96vUyIXoDf+tvJsxHzg2BAWLdXQ9laibxc6ns wXdNyCLIucGHJ36ykm1tPr0p5/iwHr5Rpj99mJUh8IQw1BgKHvQt8SR0HVV6ipo1c/ plJ+E6MWGtuRzUvJXiuGcFbF9nVXx3/i++sveL8JOe/BbAZhfVuUeoJnkdl4vgfuCU TnaPtkHU1xWgA== From: Mark Brown Date: Tue, 18 Aug 2026 22:50:45 +0100 Subject: [PATCH 2/2] regmap: Test rbtree and maple caches for very high register numbers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260818-regmap-kunit-cache-high-bit-v1-2-7e790676dea3@kernel.org> References: <20260818-regmap-kunit-cache-high-bit-v1-0-7e790676dea3@kernel.org> In-Reply-To: <20260818-regmap-kunit-cache-high-bit-v1-0-7e790676dea3@kernel.org> To: linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=6063; i=broonie@kernel.org; h=from:subject:message-id; bh=vM1lEckXpzDMDzKpUFoITsQjjvej9YM73RqUS3ThRzM=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqhNO4NdikCQ7OAyAgoLNADYWuvdIMKDz0/Wlbd gnMZVgsaAyJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaoTTuAAKCRAk1otyXVSH 0L/EB/0fuyv55LrAs1+/5/KDWMKwP9ss4tjNQXzRjZQmqPE/sVpy1jb85nPMUIX8DOtWSwCK2CD u7KQpvC5pPgEvNT7/RWmEs64bTSaKY7dypHqJYedeJg3yFrXR+pRIafJb9ACfuHqkExiDiZLkVT xolDi6uTmZOWiZsEJqTt73NH/3u6tzOBBvdJmIgt7UJp/rDiskEG1qSi78FbkPnf5/96aGq842Y qUuNFvMkAYH2Jrt5X/rkpDhCr+hjAMKTDOo4Wih+487wa+H1dH3+Do1OyUo/mmthdCFDUVGMFau EYPYX6iJY0BiK6CvE4w1mkpgf5sL74cziP4+aydkEVdUlAhB X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB We've had bugs in the cache code with handling of register numbers with the top bit set before, add some test cases for this. It's not really worth fixing up all the individual tests to support a base address, instead write a specific test that reproduces a bunch of the coverge. Run this on the rbtree and maple caches which are the only ones that can reasonably support this case. Signed-off-by: Mark Brown --- drivers/base/regmap/regmap-kunit.c | 98 ++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 95 insertions(+), 3 deletions(-) diff --git a/drivers/base/regmap/regmap-kunit.c b/drivers/base/regmap/regma= p-kunit.c index 2999d9c185d5..c78772b660d6 100644 --- a/drivers/base/regmap/regmap-kunit.c +++ b/drivers/base/regmap/regmap-kunit.c @@ -11,6 +11,8 @@ =20 #define BLOCK_TEST_SIZE 12 =20 +#define HIGH_BIT_REG ((UINT_MAX / 2) - 3) + KUNIT_DEFINE_ACTION_WRAPPER(regmap_exit_action, regmap_exit, struct regmap= *); =20 struct regmap_test_priv { @@ -23,6 +25,7 @@ struct regmap_test_param { enum regcache_type cache; enum regmap_endian val_endian; =20 + unsigned int base_reg; unsigned int from_reg; bool fast_io; }; @@ -204,7 +207,8 @@ static struct regmap *gen_regmap(struct kunit *test, config->max_register +=3D (BLOCK_TEST_SIZE * config->reg_stride); } =20 - size =3D array_size(config->max_register + 1, sizeof(*buf)); + size =3D array_size(config->max_register - param->base_reg + 1, + sizeof(*buf)); buf =3D kmalloc(size, GFP_KERNEL); if (!buf) return ERR_PTR(-ENOMEM); @@ -215,6 +219,7 @@ static struct regmap *gen_regmap(struct kunit *test, if (!(*data)) goto out_free; (*data)->vals =3D buf; + (*data)->base_reg =3D param->base_reg; =20 if (config->num_reg_defaults) { defaults =3D kunit_kcalloc(test, @@ -227,8 +232,8 @@ static struct regmap *gen_regmap(struct kunit *test, config->reg_defaults =3D defaults; =20 for (i =3D 0; i < config->num_reg_defaults; i++) { - defaults[i].reg =3D param->from_reg + (i * config->reg_stride); - defaults[i].def =3D buf[param->from_reg + (i * config->reg_stride)]; + defaults[i].reg =3D param->from_reg - param->base_reg + (i * config->re= g_stride); + defaults[i].def =3D buf[param->from_reg - param->base_reg + (i * config= ->reg_stride)]; } } =20 @@ -1648,6 +1653,92 @@ static void cache_write_zero(struct kunit *test) KUNIT_ASSERT_FALSE(test, regcache_reg_cached(map, 1)); } =20 +static const struct regmap_test_param high_bit_cache_types_list[] =3D { + { .cache =3D REGCACHE_RBTREE, .from_reg =3D HIGH_BIT_REG, + .base_reg =3D HIGH_BIT_REG }, + { .cache =3D REGCACHE_MAPLE, .from_reg =3D HIGH_BIT_REG, + .base_reg =3D HIGH_BIT_REG }, +}; + +KUNIT_ARRAY_PARAM(high_bit_cache_types, high_bit_cache_types_list, param_t= o_desc); + +/* + * Dynamically allocated cache types should support registers with the + * high bit set, the backend will return an error for any operation on + * a register below the expected window. + */ +static void cache_high_bit_reg(struct kunit *test) +{ + const struct regmap_test_param *param =3D test->param_value; + struct regmap_ram_data *data; + struct regmap_config config; + struct regmap *map; + unsigned int val[BLOCK_TEST_SIZE], rval; + int i; + + config =3D test_regmap_config; + + map =3D gen_regmap(test, &config, &data); + KUNIT_ASSERT_FALSE(test, IS_ERR(map)); + if (IS_ERR(map)) + return; + + get_random_bytes(&val, sizeof(val)); + + /* No defaults so no registers cached */ + for (i =3D 0; i < BLOCK_TEST_SIZE; i++) + KUNIT_EXPECT_FALSE(test, regcache_reg_cached(map, param->from_reg + i)); + + /* Writes should reach the device */ + for (i =3D 0; i < BLOCK_TEST_SIZE; i++) + KUNIT_EXPECT_EQ(test, 0, regmap_write(map, param->from_reg + i, + val[i])); + for (i =3D 0; i < BLOCK_TEST_SIZE; i++) { + KUNIT_EXPECT_TRUE(test, data->written[i]); + KUNIT_EXPECT_EQ(test, val[i], data->vals[i]); + } + + /* Reads should be satisfied from the cache */ + for (i =3D 0; i < BLOCK_TEST_SIZE; i++) { + KUNIT_EXPECT_TRUE(test, regcache_reg_cached(map, param->from_reg + i)); + KUNIT_EXPECT_EQ(test, 0, regmap_read(map, param->from_reg + i, + &rval)); + KUNIT_EXPECT_EQ(test, val[i], rval); + KUNIT_EXPECT_FALSE(test, data->read[i]); + } + + /* Trash the data on the device then resync */ + regcache_mark_dirty(map); + for (i =3D 0; i < BLOCK_TEST_SIZE; i++) { + data->vals[i] =3D 0; + data->written[i] =3D false; + } + KUNIT_EXPECT_EQ(test, 0, regcache_sync(map)); + + /* Did we just write the correct data out? */ + for (i =3D 0; i < BLOCK_TEST_SIZE; i++) { + KUNIT_EXPECT_TRUE(test, data->written[i]); + KUNIT_EXPECT_EQ(test, val[i], data->vals[i]); + } + + /* Drop some registers */ + KUNIT_EXPECT_EQ(test, 0, regcache_drop_region(map, param->from_reg + 3, + param->from_reg + 5)); + for (i =3D 0; i < BLOCK_TEST_SIZE; i++) + KUNIT_EXPECT_EQ(test, i < 3 || i > 5, + regcache_reg_cached(map, param->from_reg + i)); + + /* Reread and check only the dropped registers hit the device */ + for (i =3D 0; i < BLOCK_TEST_SIZE; i++) + data->read[i] =3D false; + for (i =3D 0; i < BLOCK_TEST_SIZE; i++) { + KUNIT_EXPECT_EQ(test, 0, regmap_read(map, param->from_reg + i, + &rval)); + KUNIT_EXPECT_EQ(test, val[i], rval); + KUNIT_EXPECT_EQ(test, i >=3D 3 && i <=3D 5, data->read[i]); + } +} + /* Check that caching the window register works with sync */ static void cache_range_window_reg(struct kunit *test) { @@ -2168,6 +2259,7 @@ static struct kunit_case regmap_test_cases[] =3D { KUNIT_CASE_PARAM(cache_drop_all_and_sync_has_defaults, sparse_cache_types= _gen_params), KUNIT_CASE_PARAM(cache_present, sparse_cache_types_gen_params), KUNIT_CASE_PARAM(cache_write_zero, sparse_cache_types_gen_params), + KUNIT_CASE_PARAM(cache_high_bit_reg, high_bit_cache_types_gen_params), KUNIT_CASE_PARAM(cache_range_window_reg, real_cache_types_only_gen_params= ), =20 KUNIT_CASE_PARAM(raw_read_defaults_single, raw_test_types_gen_params), --=20 2.47.3