From nobody Mon Sep 28 20:06:51 2026 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2299B415F13 for ; Mon, 17 Aug 2026 19:26:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786994761; cv=none; b=XbzWbkNhd4tZ4PSCnNp6hMeOka0E6HYsu/ldEgijhGlY1+560kwjWpwQXScFPGkQ5K06Sk1vfQu2l0dea8z2HNZfzu128eRelP17hqtuOAWfEzd6H58P/uPCzYxBZ8fbchn2DCyFsBwz1jKWdMGtbNFCrmPAfW73DfovjIiFbtI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786994761; c=relaxed/simple; bh=JMlnOwy00wDEbAfza6sr9cE+BuAcXlyzfpQbLz5OvTc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TTpWtAEqZ32NMysqiUi6d9x+tAVh9X3xeZXh8EeL7MrVzO+dKnIz9MS0L1aF95a6URs9aBi+zYhgLQcF9wPOFZe/jKtQxa2if7CNdnu9COeCy2Hqpdo9a0JpaGNZPZ1uASXbkjs9z7IY3N1DTLZRh3NxzyfEbxgaSBxfoo2gsrg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=S9Si5qkG; arc=none smtp.client-ip=209.85.214.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="S9Si5qkG" Received: by mail-pl1-f176.google.com with SMTP id d9443c01a7336-2caced6038eso3449535ad.0 for ; Mon, 17 Aug 2026 12:26:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1786994759; x=1787599559; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=c5fBKIKgzNd7gWhqnVVDaPgInr0GNymDhy+5aCajQgo=; b=S9Si5qkGVvfWRNrlO8rBZdERQMtxX9b7FXvEE8xseHm3YDVlfoC3JyGo79m2AQTMVo VHQomorMQPEagNmyAWgsdSd3ZTyyOc70ASUXyTqe1Nw+G/s66iwQU+qOT7jyzvezp83C U3YwjgbsRH7umpWvvi2QoZtsSjN5CLfWqdg2lnyssK/Bmo6iK8aHujEoqOCVeme6dpcD Brz5duvaQ+kwqD/DwFvgEp/o9OtLWIRfbhQBlmDBu2IL5eX4yQ5xUGhq/7ntESQVdjiS xPrsaZNxM6Bz9YSjVbSq6hIt/VbHymsyDIQu0m7mnKrBqqJeWbMUSeXv3ryAOyUK6ntX kL0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786994759; x=1787599559; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=c5fBKIKgzNd7gWhqnVVDaPgInr0GNymDhy+5aCajQgo=; b=qu6eK3K/pDJHDuOcI8kfLnpXew5nrJTNFyt3Q/nYIiC+jCikYbm2IfS6rty30zM6SB rbEfHf6Y6JBoW85K//vmjuVDrY4Z0wnAEQdgFl1jOXfrKNLeuP4uFLyajyotKtTHgmIa 11hum2XhwT7n6QoSuJ1doX0AbYJn46sUDfsb3wIo7ytuAAWttxeMJLN53MeCn+QJA+Ua SqWYtzLjphD33jGeXSJHiff15zXBKY258Tw3yfv1oHQTulWulfOHlgeYCv7/jSKR7QIb XyqZNK2Ki5tUyWvrvwGxM6v8V+ibtj2tMyL8lSRUsfb2q3q21rb9FsVEFwvb7g8lQpSx HMgg== X-Forwarded-Encrypted: i=1; AHgh+RofLM4jNb4QYhKYPflQ2iZZL8QvXD8qgvHejxqib2JCcsPS0NULgqxCGEvwy10UBQmOSJuyfNhvVY9EHnM=@vger.kernel.org X-Gm-Message-State: AOJu0Yy2tZ/AM87UwpouXVlSEcDI3DZkrNmqcjXN05jOVFeo1/+p1NBb fxOD2Iq2uCAEZfuTWC3PfnIcI3gsDLN89ys47LKqc43pOwe7EicktJU6 X-Gm-Gg: AR+sD13GiATbEQZIA8OByHdfAqYUfQovnCBH/S+fpQYFbFPh6tUmivQjC5VfjpFSR6W Ufbq2jKPoaF0ccHQfe4FUOx2nKypjx5hplnlLI4Q39w2ns00RAf+4f674ybaJEGXp5dm+rtmGt9 PYbwjMh0r96WIllkpnzC8cIpn3E0SA6IDlkA8srGVDQTXhz4NaPhvqKDHzRoA5tGzglFTKVVIQV Da/lrpsAnrrk5yL0e1XdCZdrFpdjjiHPlSehLM6wzilG/BO5ZgjmiCpMtfqUxq6c+lH7wJHwocR YumZrO9WbpTR+Or+MjuYJf/MF2jYKMxrWBbzhF/uAWX5DoWO3D6EIJRuK4dWylNMJnDmT5a5fQh UodjC5ULu5bhQDhW0QKD4uOPvvnHQNO20XPxOYDdNxyHxZY57VlSEeWOpCiSUqgHaMSad8BToJk TYlNZ+BwhVHCQbuB9KSzEd/c9U4OWqK7jiTMrBuAZmdx+YiH80GK66aQOVn9J0O38eUi2FvXw6e c677qTK5zRyTvkUZr1MAqfyPMa88DCJt9N7b+C5oVfESgAciipmPkjelfTqO8CuB1DGKNHOgfkh vm33FmtT4A== X-Received: by 2002:a17:903:1983:b0:2c6:8d95:fd7e with SMTP id d9443c01a7336-2d5cac52c6amr10888055ad.6.1786994759276; Mon, 17 Aug 2026 12:25:59 -0700 (PDT) Received: from iku.example.org ([2401:4900:1c06:2735:f886:32ae:1e17:ec13]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-326798cb9f5sm10218757eec.13.2026.08.17.12.25.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Aug 2026 12:25:58 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Michael Turquette , Stephen Boyd , Brian Masney , Guenter Roeck , Wim Van Sebroeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v4 1/7] clk: renesas: r9a09g077: Register SYSC regmap Date: Mon, 17 Aug 2026 20:25:34 +0100 Message-ID: <20260817192540.423994-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260817192540.423994-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260817192540.423994-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Register a syscon regmap for the System Controller (SYSC) integrated into the RZ/T2H and RZ/N2H CPG block. Unlike traditional Renesas CPG/MSSR implementations, the RZ/T2H and RZ/N2H CPG block also integrates the SYSC, which provides low-power management, clock monitoring, write protection and peripheral configuration registers shared by multiple drivers. Implement the RZ/T2H-specific .post_init() callback to create and register a syscon regmap covering the SYSC register space using the CPG device node. For backward compatibility, return without registering the regmap when the mapped resources correspond to older Device Trees that expose only the legacy 64 KiB CPG register window. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v3->v4: - Dropped RZT2H_SYSC_BASE macro - Added array of base pointers to the r9a09g077_sysc_reg struct to support multiple SYSC regions - Merged r9a09g077_writeable_readable_sysc0 and r9a09g077_writeable_readable_sysc1 into a single function that checks the SYSC block and offset to determine if the register is readable/writable. - Added RZT2H_CPG_REG_SIZE macro - Updated r9a09g077_post_init() to call of_address_to_resource() to check the size of the mapped CPG register regions - Dropped changes from cpg_mssr_common_init v2->v3: - Dropped dangerous registers from writeable_readable list. - Renamed sysc_init to post_init and updated signature to take cpg_mssr_pub struct. - Created a single regmap covering both SYSC register regions instead of two separate regmaps. - Updated commit message v1->v2: - Made use of for_each_child_of_node_scoped - Moved sysc_init() to the end of the probe function --- drivers/clk/renesas/Kconfig | 2 + drivers/clk/renesas/r9a09g077-cpg.c | 140 +++++++++++++++++++++++++ drivers/clk/renesas/renesas-cpg-mssr.c | 3 + drivers/clk/renesas/renesas-cpg-mssr.h | 1 + 4 files changed, 146 insertions(+) diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 17b95a2e96fb..46b929e9872b 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -223,11 +223,13 @@ config CLK_R9A09G077 bool "RZ/T2H clock support" if COMPILE_TEST select CLK_RENESAS_CPG_MSSR select CLK_RZV2H_CPG_LIB + select MFD_SYSCON =20 config CLK_R9A09G087 bool "RZ/N2H clock support" if COMPILE_TEST select CLK_RENESAS_CPG_MSSR select CLK_RZV2H_CPG_LIB + select MFD_SYSCON =20 config CLK_SH73A0 bool "SH-Mobile AG5 clock support" if COMPILE_TEST diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a0= 9g077-cpg.c index 5640c2035e5a..0495e3206973 100644 --- a/drivers/clk/renesas/r9a09g077-cpg.c +++ b/drivers/clk/renesas/r9a09g077-cpg.c @@ -7,6 +7,7 @@ */ =20 #include +#include #include #include #include @@ -15,7 +16,10 @@ #include #include #include +#include #include +#include +#include #include #include =20 @@ -87,6 +91,20 @@ MODULE_IMPORT_NS("RZV2H_CPG"); #define CPG_PLL_MON(x) ((x) - 0x10) #define CPG_PLL_MON_LOCK BIT(0) =20 +/* Size of each mapped CPG/MSSR register region (base0, base1) */ +#define RZT2H_CPG_REG_SIZE 0x20000 +/* This is the size of two SYSC regions combined */ +#define RZT2H_SYSC_SIZE 0x20000 +#define RZT2H_SYSC_OFFSET 0x10000 +#define RZT2H_SYSC_BLOCK_MASK BIT(16) +#define RZT2H_SYSC_OFFSET_MASK GENMASK(15, 0) +#define RZT2H_SYSC_BLOCK(x) FIELD_GET(RZT2H_SYSC_BLOCK_MASK, x) +#define RZT2H_SYSC_REG_OFFSET(x) FIELD_GET(RZT2H_SYSC_OFFSET_MASK, x) + +struct r9a09g077_sysc_reg { + void __iomem *base[2]; +}; + enum rzt2h_clk_types { CLK_TYPE_RZT2H_DIV =3D CLK_TYPE_CUSTOM, /* Clock with divider */ CLK_TYPE_RZT2H_MUX, /* Clock with clock source selector */ @@ -875,6 +893,126 @@ r9a09g077_cpg_clk_register(struct device *dev, const = struct cpg_core_clk *core, } } =20 +static int r9a09g077_regmap_read(void *context, unsigned int reg, unsigned= int *val) +{ + struct r9a09g077_sysc_reg *sysc =3D context; + void __iomem *base =3D sysc->base[RZT2H_SYSC_BLOCK(reg)]; + + *val =3D readl(base + RZT2H_SYSC_REG_OFFSET(reg)); + + return 0; +} + +static int r9a09g077_regmap_write(void *context, unsigned int reg, unsigne= d int val) +{ + struct r9a09g077_sysc_reg *sysc =3D context; + void __iomem *base =3D sysc->base[RZT2H_SYSC_BLOCK(reg)]; + + writel(val, base + RZT2H_SYSC_REG_OFFSET(reg)); + + return 0; +} + +static const struct regmap_bus r9a09g077_sys_regmap_bus =3D { + .reg_write =3D r9a09g077_regmap_write, + .reg_read =3D r9a09g077_regmap_read, +}; + +static bool r9a09g077_writeable_readable_sysc(struct device *dev, unsigned= int reg) +{ + unsigned int offset =3D RZT2H_SYSC_REG_OFFSET(reg); + + switch (RZT2H_SYSC_BLOCK(reg)) { + case 0: + switch (offset) { + /* ELOPA/B and GTIOCSEL */ + case 0x0000 ... 0x0008: + /* Encoder config */ + case 0x1000 ... 0x1164: + /* PCIe config */ + case 0x2000 ... 0x2024: + case 0x2030 ... 0x2054: + case 0x2060: + /* xSPI config */ + case 0x3000 ... 0x300C: + case 0x3100 ... 0x310C: + /* MD_MON */ + case 0x4100: + /* PRCRN */ + case 0x4200: + return true; + + default: + return false; + } + case 1: + switch (offset) { + /* WDTDCRm */ + case 0x5100 ... 0x5114: + /* PRCRS */ + case 0x6000: + return true; + + default: + return false; + } + default: + return false; + } +} + +static int r9a09g077_post_init(struct device *dev, struct cpg_mssr_pub *pu= b) +{ + struct regmap_config *regmap_cfg __free(kfree) =3D kzalloc_obj(*regmap_cf= g); + struct r9a09g077_sysc_reg *sysc_reg; + struct regmap *regmap; + struct resource res; + int ret; + + /* + * Return early if the SYSC sizes are not as expected, for backwards + * compatibility with older device trees that only expose the 64 KiB + * CPG register window. + */ + ret =3D of_address_to_resource(dev->of_node, 0, &res); + if (ret) + return ret; + if (resource_size(&res) !=3D RZT2H_CPG_REG_SIZE) + return 0; + + ret =3D of_address_to_resource(dev->of_node, 1, &res); + if (ret) + return ret; + if (resource_size(&res) !=3D RZT2H_CPG_REG_SIZE) + return 0; + + if (!regmap_cfg) + return -ENOMEM; + + sysc_reg =3D devm_kzalloc(dev, sizeof(*sysc_reg), GFP_KERNEL); + if (!sysc_reg) + return -ENOMEM; + + /* Only allow access in the SYSC regions */ + sysc_reg->base[0] =3D pub->base0 + RZT2H_SYSC_OFFSET; + sysc_reg->base[1] =3D pub->base1 + RZT2H_SYSC_OFFSET; + + regmap_cfg->name =3D "rzt2h_sysc"; + regmap_cfg->reg_bits =3D 32; + regmap_cfg->reg_stride =3D 4; + regmap_cfg->val_bits =3D 32; + regmap_cfg->fast_io =3D true; + regmap_cfg->max_register =3D RZT2H_SYSC_SIZE - 1; + regmap_cfg->readable_reg =3D r9a09g077_writeable_readable_sysc; + regmap_cfg->writeable_reg =3D r9a09g077_writeable_readable_sysc; + + regmap =3D devm_regmap_init(dev, &r9a09g077_sys_regmap_bus, sysc_reg, reg= map_cfg); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return of_syscon_register_regmap(dev->of_node, regmap); +} + const struct cpg_mssr_info r9a09g077_cpg_mssr_info =3D { /* Core Clocks */ .core_clks =3D r9a09g077_core_clks, @@ -889,4 +1027,6 @@ const struct cpg_mssr_info r9a09g077_cpg_mssr_info =3D= { =20 .reg_layout =3D CLK_REG_LAYOUT_RZ_T2H, .cpg_clk_register =3D r9a09g077_cpg_clk_register, + + .post_init =3D r9a09g077_post_init, }; diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/r= enesas-cpg-mssr.c index 80f4403ea2ba..f2feac1cc74f 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -1414,6 +1414,9 @@ static int __init cpg_mssr_probe(struct platform_devi= ce *pdev) =20 error =3D cpg_mssr_reset_controller_register(priv); =20 + if (!error && info->post_init) + error =3D info->post_init(priv->dev, &priv->pub); + reserve_exit: cpg_mssr_reserved_exit(priv); =20 diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/r= enesas-cpg-mssr.h index ad11ab5f0069..5bef6f34dcb2 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -178,6 +178,7 @@ struct cpg_mssr_info { =20 /* Callbacks */ int (*init)(struct device *dev); + int (*post_init)(struct device *dev, struct cpg_mssr_pub *pub); struct clk *(*cpg_clk_register)(struct device *dev, const struct cpg_core_clk *core, const struct cpg_mssr_info *info, --=20 2.43.0 From nobody Mon Sep 28 20:06:51 2026 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FCDB415F13 for ; Mon, 17 Aug 2026 19:26:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786994768; cv=none; b=gIwKEaq9C4Qm4Seg+BTDFUJYwrXkPdv/prG8bPLiedYQApTqniyEq478yp0tXWgKvqn+X9GOjjYBNz9w4m4sA8dDXgrpVe059dTtB0C/brOtUIHLGWlJS6Yjk00GJVhq2F2j6Svu08SM1Dqv8NYa54F4I1NSHHtGOTSTEd+clH8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786994768; c=relaxed/simple; bh=m1g97T0KsI8+u2/mma+fo4wXtJYWPRQtDXxF8ylWrvY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mY2OqzHlSG7yw8cKknSZ57cDx1cbYg4tOxOAVnKSqNAFof1nsNcFhULPxie1KTUCHAvMrF/eOhN5hJtkCpkSHEHQsZzAtZjOnkZiqcOQOFRKCj5lNYsRaN0ZNkhIYsjFmoHQjIBa6M2q9NWmGKXXORRDzCONkVs/2Yu3EESa5PQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=EeMWyMG9; arc=none smtp.client-ip=209.85.214.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="EeMWyMG9" Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-2d5cad1a6baso3002765ad.3 for ; Mon, 17 Aug 2026 12:26:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1786994767; x=1787599567; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=gdPzWqXXmK+PEpzF2FUddkIJQuQSykw2wIqGTSDwjWo=; b=EeMWyMG9qF51p6EmfCbpgubzHrya4dCICsQnjkkRIo1Kt+JKPRxAc9zMBvinEpuJDX V1zhLHy8d753KgT5aeNTqEeCnfRMu4FYvS8GY7kTM53Q133uC/dU7TFvGgxA5kKe7zxT czg1Uae0GMu8wrS4qEywCy4KP72BfybPbBQRqVoq6rJ7ypupJZnpUAEe/JxpLNprEl8D wX8dmAmWBa9fuFBjzW8r5AJtP+MAA9WawcIEI98HARJ9liwK0H8spcCK4qQuEkIpj7Cy gQG+LARzlXL5c4ECUvH0VNO6bi4yd7KzLAQQbQ+8tFowpH1s7G3D4/B5ovG5O9BFCnV+ UQcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786994767; x=1787599567; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=gdPzWqXXmK+PEpzF2FUddkIJQuQSykw2wIqGTSDwjWo=; b=VeiU21mf2ABYMXFrgol4sXKTrCUgwWcdXSnsU9WfPgGnZAr8tG4PFGhoicHtmft4LC HTyWuW7JmnxBjbfEpoQL87XZLrH7Kfj/TvDizsErToazVpgOiFpRtfrnbX9TCLs6sjfk zqkIxkU9bcELuVRGRZ5iLvMOg+LmeThY3vWtOyqKajew/cMXzl9W0AW+666RkX7dWBD7 nQJjRetP/SAkD70ReJ7CUpWjgsyVJczTjSVCM/eBeyVXGeYn7FJ5sj6Lhwm1Aj0uR6WJ x4tKOk37adUD9JJpmW6/G6tSDXHG8yyXIJoaCPOoOR5X+bOzOynmua3sHbNr7PdhiIPV nnVQ== X-Forwarded-Encrypted: i=1; AHgh+Rom64ICPnQWthEUGd7p1Gwcm38/UKrVu++9ZS4p8peoUcAIv6AeKO2bU1gol4OIBe3LQj1ZjTpHDytqd34=@vger.kernel.org X-Gm-Message-State: AOJu0Yxm3VY4Goh1M16880y35Tjal6XLOV0f+htx63SnhVs1F3dUxh4p eoBTcxfDSC0Hn3yHXLwNsQ1pLUkUWSU/YTDz4TxDT3vOz4cnSAoB0x8w X-Gm-Gg: AR+sD11kPfXj54+5+919L5cVzUFg8yWiYbG8A5QOHhAdGF1LwqXOzAxznAW9fZzx8xZ c+rjakV3TCiVbl+K1oc2rjFxLNHMAxz12zIeWuXH0E3zu+y4JtZXYHKVXpD0wMsWaNzqqzS+pka eL1ktmpYyXY7b9hBnKh2iZ2gD0NDtDrTSUuawZFiRIo+yPxpbxjmsAxHsynryznFjTkW7Ggygsm +oX+9vbCvj4MG8nYlia6F3RxvozcDGtbkUMgPwn4NZNfdyg3bAye0QFvMhNzBDTU/ltvTtN4VGQ tafqA+rHo5FKAgjtEyw8bFvQrnAPTllxml2FlKst/b/jcR4BMDYNG/78zPNHTIjSRvSLmOhTHrL hik3mw7VNew97OH7n5KauC3iutQwpZDiQdbwjHB91tbMoIE893TIPf6R42+1z6nRjBu5dCUVf3M ezTEqFhHhrGNm+axmHelykzSwXPgZbEAFYdtSf+IsqlRYbql+FEeBjUl2qRLez4zaHfgzerqjn4 3+cJ/4sXkkF63DT2qaDXn3IRa/agb3ixLTwxdRfPADdIPimdP1PhUy2o1fHKbetd+zii4POtEwn Npb863pG5w== X-Received: by 2002:a17:903:1a0e:b0:2c9:d55d:2d3 with SMTP id d9443c01a7336-2d5c5148ff7mr25131325ad.15.1786994766706; Mon, 17 Aug 2026 12:26:06 -0700 (PDT) Received: from iku.example.org ([2401:4900:1c06:2735:f886:32ae:1e17:ec13]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-326798cb9f5sm10218757eec.13.2026.08.17.12.25.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Aug 2026 12:26:06 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Michael Turquette , Stephen Boyd , Brian Masney , Guenter Roeck , Wim Van Sebroeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v4 2/7] arm64: dts: renesas: r9a09g077: Adjust CPG register region sizes Date: Mon, 17 Aug 2026 20:25:35 +0100 Message-ID: <20260817192540.423994-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260817192540.423994-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260817192540.423994-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Increase the size of both CPG register regions from 64 KiB to 128 KiB. On the RZ/T2H SoC, the CPG/MSSR block is a multi-function block where, apart from clock and reset handling, it supports other features including clock monitoring, write protection, and peripheral configuration registers. Expand the mapped register regions to cover the entire register space of this block so these additional features can be utilized. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v3->v4: - No change v2->v3: - new patch --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g077.dtsi index 33f953c110bb..de20bed2797b 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -1075,8 +1075,8 @@ xspi1: spi@801c1000 { =20 cpg: clock-controller@80280000 { compatible =3D "renesas,r9a09g077-cpg-mssr"; - reg =3D <0 0x80280000 0 0x10000>, - <0 0x81280000 0 0x10000>; + reg =3D <0 0x80280000 0 0x20000>, + <0 0x81280000 0 0x20000>; clocks =3D <&extal_clk>; clock-names =3D "extal"; #clock-cells =3D <2>; --=20 2.43.0 From nobody Mon Sep 28 20:06:51 2026 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8DF242A141 for ; Mon, 17 Aug 2026 19:26:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786994776; cv=none; b=mKv4MX+jCjQXw9CvEBf4xPhPoC6042O1RA4Ie1OyG/yKvQ0vL1eoSxnBQ1+bxMHeZ5CEJUDnEg04T8rCN+aMYc/BjMON+u0ytZuhtuABgFgKfrqYFTJ4Dntw5bESvwuhY/jQIiq3kYr+CML2rPF3G0b8aK74lHn7djriE5MFGuU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786994776; c=relaxed/simple; bh=DVgizKVpuB08U7drflvR/Nm9xyLIrxGf4hC+AIIeucU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nlOjiYEMCSB5YY6kj6NV6gc1Z2lNKDbP8NIsOAxawdvEovEfskDHceNrjhr3VvLqZjhiObY7LwoF0H1CIjSze05B0WpMmO5I9BYKIlWKL7exE4fgTz9wRbz8LLGZksjT4SDaEDzfBa0nsqRX5UMKgayo/LnRXpEd55Pu/hJv864= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=SFbx3p/0; arc=none smtp.client-ip=209.85.214.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="SFbx3p/0" Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-2cc61541f8cso2838245ad.0 for ; Mon, 17 Aug 2026 12:26:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1786994774; x=1787599574; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=DnkWDGpHcDpKI6ZJE2YuZxstTmPwSlwlz2aFP0o410o=; b=SFbx3p/07jQI0SvdSXIF8yC8RZvRKYnCN/EltB0vMLy0zOhKVdkcMPOSKFVwL42wOm qeg5oaifBjh18YwDqcAbTMTYWT1MpUL4C8ERVv47Or8ZoxqQEhPz8PGIQmz/N1IuFG0N hLhF7QePDxLD3MAaeZNYWe46xvZzeiIeL9GCRjIrEWXAfj8qUCOYSKdo7QW77SzJhipu owSj0zaEoB2btjiEoenyqZ0E1vPYXFMYS56Pb3VPQ8M1JY0cLkAoKnHxLi7ADRuaIWgc TiLOGWjObtenPWhM5wjYSOpDZowkwDapb720qZRN7tCYxSWy5FutRjroWTD4ReFozpbi cOGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786994774; x=1787599574; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=DnkWDGpHcDpKI6ZJE2YuZxstTmPwSlwlz2aFP0o410o=; b=AR1BEjIk2+hM9D8BB9CWE+kcRoLSenJzVeOYlGzRo/ZJXO80HFJD/gMq/G19Ix8JIZ bi93VBgS9Fn6ZFk40M8frUfX9ykwbnRHXQHVDEOK3lSQCDKeGY9EKIVXQtk15oRBjnYa 6CbybiJVL5PfyNc8XkCVg0Hny8OPlc39Cnqo2OjcNbfTfjU3no4gBiKBRUpSyCMZ9UT4 4OzVWSVh6FVVp9SzYQmg6bTrhr3bdhRVSfJ8m7JVLsFoklqplUZYpoSzhTcd7NbjXp7c 2CuVq/05RhaDLcXwNAtm0E6tuq8Dl2wHa90azLSR4RRQsdQdez3XPRtci+g+M3oTt+7O qOOQ== X-Forwarded-Encrypted: i=1; AHgh+RpNjYSTcZX5jXupi/oBRlwfiVYYsj+rhEdOBLSA39B4WJi9NVQwA+aM6rVlpUQJf1ULaEFYH4vBGOdlpKw=@vger.kernel.org X-Gm-Message-State: AOJu0YyAHZMeaIECSR7jdcIeuOBgmjRZeQlk3CL+lTkIrRuQZ80PWYjF CJsO7iM32bTMbh5zCM4RXwFV9xmCFaBdfjFAezpwXlNMG0NV3dAoi8/K9voe4Vrn X-Gm-Gg: AR+sD13JoDckwpDPQMEym9em1PvC7tlxnX7+W1tIqD4bHgIWZkqupnQwOg7xbxCP706 wKQVdplk+501bqRfLnDACHwflrUl7/vjz3vQQ5YnXlYN0zLAV7qCFV9GuBJPpHnF8Gcssz+FcjX e5Xa1AY+6UgzkMQ2rP/N7s/f27jxBTUv08X/Q0VmaySyYNDh6OX7XaucnA1HMh52nxZN/FrmyCt OF92xRFA3t3XzlNQdB3gOdX9932l0QjATWCpN/mlVsu9XZViO9hLkQgHAUJ1I8Eox5LnUGEf0e1 bW2+6No/SyF00Ab6PhKbWhEEXRFv21sRcdkhCCVKIjeilIhoXTpflZh0cOymvorsRK07TRPr450 pFEHym9IpYshZCvMIFHVsNmPKexf/vfSY4WR8UDunp5RdM9TvHHfW8W1t1g1Cf5siVcBFv4irFH GHnEVewzgO04zgzPq11oSsDJbu0tyNPXhsidyBfEyKW71p8HEaz//0xdAVD7hqyTeIYIdO41XNF 0NEt/1mHT6lbpt75pJLmsl4n3fsPSMYPzb5i5XUB6ehtFDyVt7MgHorCoz1f/euICrg1zWQkjSD GnrgmDjBdA== X-Received: by 2002:a17:903:3bcb:b0:2c0:d94f:50c7 with SMTP id d9443c01a7336-2d5cac820d6mr11280805ad.7.1786994773992; Mon, 17 Aug 2026 12:26:13 -0700 (PDT) Received: from iku.example.org ([2401:4900:1c06:2735:f886:32ae:1e17:ec13]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-326798cb9f5sm10218757eec.13.2026.08.17.12.26.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Aug 2026 12:26:13 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Michael Turquette , Stephen Boyd , Brian Masney , Guenter Roeck , Wim Van Sebroeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v4 3/7] arm64: dts: renesas: r9a09g087: Adjust CPG register region sizes Date: Mon, 17 Aug 2026 20:25:36 +0100 Message-ID: <20260817192540.423994-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260817192540.423994-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260817192540.423994-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Increase the size of both CPG register regions from 64 KiB to 128 KiB. On the RZ/N2H SoC, the CPG/MSSR block is a multi-function block where, apart from clock and reset handling, it supports other features including clock monitoring, write protection, and peripheral configuration registers. Expand the mapped register regions to cover the entire register space of this block so these additional features can be utilized. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v3->v4: - No change v2->v3: - new patch --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g087.dtsi index d5b3eb6c1736..813bb0cb021c 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -1078,8 +1078,8 @@ xspi1: spi@801c1000 { =20 cpg: clock-controller@80280000 { compatible =3D "renesas,r9a09g087-cpg-mssr"; - reg =3D <0 0x80280000 0 0x10000>, - <0 0x81280000 0 0x10000>; + reg =3D <0 0x80280000 0 0x20000>, + <0 0x81280000 0 0x20000>; clocks =3D <&extal_clk>; clock-names =3D "extal"; #clock-cells =3D <2>; --=20 2.43.0 From nobody Mon Sep 28 20:06:51 2026 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D727F43C7DF for ; Mon, 17 Aug 2026 19:26:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786994783; cv=none; b=A9lquPIp7VJrjS+nBX0cixzYtU7cokHc8VQl2Qukcl5Q+WckPGMrBV3gSdNjADP2hlQzr2cMkBaquFIocEh8ehMmrEkAs2RZPvioaAuLjzbMLhDffQtVtFCa6r5/vrSjSIp45znwmmH2lyZ4IDtaXloJaGPeB33WFlqXpmOGCXU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786994783; c=relaxed/simple; bh=DWmvPVkIJY6ptLO3/hrCszDHtdNs2FV+Izbm1KSLWQE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fNlzJ71G4qoLxv6UFpLTRTeR7bk1ENjrQNDkJnuib1AszATf1QamxwaU4xXKB5i1lgtQBhbiJeT/7pERfk3VD9nNNwjY0mGAFr0udfaTP4YOkU5MFmEg0Uv4WpOrrBWiz9+u4SLSox0UVRqsBkDy/5Bc2cD4cJAmdt1fmnTAo7I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=JOdwBfrS; arc=none smtp.client-ip=209.85.214.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="JOdwBfrS" Received: by mail-pl1-f171.google.com with SMTP id d9443c01a7336-2d5655cc850so23183615ad.3 for ; Mon, 17 Aug 2026 12:26:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1786994781; x=1787599581; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=fgj2TWG+XmWQLneXONmNV+5Ec6rSceleu5gtE3hIg3M=; b=JOdwBfrSVwBxmWN+36TpJoseXe6rOBPq+X+rh0YIVYxNWShob/rPONGvkzQWAxlFHa 3UL6kiUQZOdXgz4WrW/xNd9BMJW6HHm0I2efH9mDV5EgtjqwBC5l2+1YxD2AYW9zNj6I PZ3xnw92vVCvC7qjQrYEPI6m9iekbVIDhQjyOptkLQdL104QQC9hfHOZJSwuqPNtL56o eGa55wQuPfWDjRxZCWFzMDxYvg+DxV3txxWHPfRJ7RJyOgUWfoXyAPPEE+z2BswbGjmM 0v+ZJHsaDwCn6odxsruaV9pgY2fQxGZDb1s7+gvczbHQ/2c9CdzJ+RtSnZ/vMiEFhh8Z 7IXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786994781; x=1787599581; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=fgj2TWG+XmWQLneXONmNV+5Ec6rSceleu5gtE3hIg3M=; b=guII1WMzMqS3IYT/L8KunGFV1nqKn2GpXaho5eG5i6x0pDc/Qi/OTJUZk+0z7dvIE2 u90eUyzbIFVAjt7tciJk3gApKd6PVQ/q0595dRCaQt6HwfYvBmEXIC2EfgpskiQIJ0WH SUG/6ymK7ukVizOKH2JgTsPOBUTrENQBM6r3kLco9iBjfvo/M70zIZsZ3g+WsI+oInlZ sjJnlv3KgB/EKWuEIePPnblzk7O1CfVMSsX6D0GF+0NgEFGHboqZEUsiMc/mCHISyyN5 ZQWTxHyanpUpJceMmriW4ffFpNGoYXNBBivb5Emh1l1n3+6gkp5Zp6u68oVLD2yofNOC 08iw== X-Forwarded-Encrypted: i=1; AHgh+RoNNgTke/cZT+TUfTrQto6KSMBgYWZubXPxHItyKVNq/TWLVV6LfTd1DKemCQaOnVH63nuXRJKXrPWDvHo=@vger.kernel.org X-Gm-Message-State: AOJu0YzS9Yq7Y5++6klFJ7hehaNJqFEHHTyubZjlxPkUUGhl8aNMrFTw LRI7aTLXytmGetzCdzCt3hVBQKPh18j4w+X4lLUCZmRz3mR8w78IKPi2 X-Gm-Gg: AR+sD136aaKUP/BZ8kcmNm5/ceNro2qbzq2vLbj3PQQZIWsLFvzPmFk6WlNX2KKOBfx 75r5zr2AiOuAWUUp0oad/dY7Uf5egk1WoqVRr2Vua3rTSteNV1/tzy3SP9n7YgIo3qEHteO+yzZ rwVRgv/y6ToYDVHqPpCSUlFz+GwzEfPo8L7s0ZlAbM4dWfCczsKufFxhgJnlKHSIc9UCMOuSo10 ixZLIfk4bmoZbRcTgPyf1RZKal+qSPVdUSE0gZY8r0ZiKlQmQbMOcyowvEwF/34qBXKIwA8jpy4 7EFT3abeBwOihpqMvlBcR0c8Nv38sOhrA2OkCmMlPaDjk3sfang70op04CCeczNFfGe2mbTO9l2 vJLoP9GWfEmLcpYQGckwGp+gNzWHW7SB3xusPFXUEAcsWqpMgQ8iGRywe1myFVE14fEz5GIGGRm 2YjPVXSBQFsEA2+q69Um7ppO+TELcnuGbNKXyCx3GaiczU8mDuZX3tidZO7U+OFgooI/DPXKBTd GtO1sw2OegmkyyBakc8FJWXjOS0R22Fn1W92EjZl5kRqkS+ZZT99LaSL5/7E2ebW2B+u4Fbr2FZ q/cnUgjcnw== X-Received: by 2002:a17:903:1ae5:b0:2ca:caa5:9c04 with SMTP id d9443c01a7336-2d5c547cc04mr26002355ad.23.1786994781034; Mon, 17 Aug 2026 12:26:21 -0700 (PDT) Received: from iku.example.org ([2401:4900:1c06:2735:f886:32ae:1e17:ec13]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-326798cb9f5sm10218757eec.13.2026.08.17.12.26.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Aug 2026 12:26:20 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Michael Turquette , Stephen Boyd , Brian Masney , Guenter Roeck , Wim Van Sebroeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v4 4/7] dt-bindings: watchdog: renesas,r9a09g057-wdt: Add CPG/MSSR syscon support Date: Mon, 17 Aug 2026 20:25:37 +0100 Message-ID: <20260817192540.423994-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260817192540.423994-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260817192540.423994-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar On the Renesas RZ/T2H SoC, the Watchdog Timer Control Register (WDTDCR) resides within the CPG/MSSR block rather than the WDT address space itself. Previously, this was handled by including a second register range in the "reg" property. However, this is architecturally incorrect as the CPG/MSSR block consists of two distinct regions (0x80280000 and 0x81280000) that contain registers for multiple peripheral blocks. Since the CPG/MSSR block is a multi-function block, introduce the "renesas,sysc" phandle-array property to allow the WDT driver to access its control register via this shared regmap. Mark the use of a second "reg" entry as deprecated in favor of the new phandle-array approach for SoCs that require WDTDCR access. Signed-off-by: Lad Prabhakar Reviewed-by: Rob Herring (Arm) Reviewed-by: Geert Uytterhoeven --- v3->v4: - Added RB tag from Rob. v2->v3: - Updated property name to "renesas,sysc" - Updated description about deprecation and use of the new phandle-array property. - Updated commit message v1->v2: - No change. --- .../watchdog/renesas,r9a09g057-wdt.yaml | 29 +++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-w= dt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.= yaml index 975c5aa4d747..322b6921c147 100644 --- a/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.yaml @@ -48,6 +48,17 @@ properties: resets: maxItems: 1 =20 + renesas,sysc: + description: + System controller registers control the start/stop of the WDT, and h= alt debug. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to system controller + - description: watchdog IP instance index + minimum: 0 + maximum: 5 + timeout-sec: true =20 required: @@ -73,15 +84,29 @@ allOf: minItems: 2 clock-names: minItems: 2 + renesas,sysc: false else: properties: clocks: maxItems: 1 clock-names: maxItems: 1 - reg: - minItems: 2 resets: false + allOf: + - if: + required: + - renesas,sysc + then: + properties: + reg: + maxItems: 1 + else: + properties: + reg: + description: Deprecated. Use the renesas,sysc property alo= ng with + the watchdog IP instance index instead. + minItems: 2 + deprecated: true =20 additionalProperties: false =20 --=20 2.43.0 From nobody Mon Sep 28 20:06:51 2026 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7A14432BCD for ; Mon, 17 Aug 2026 19:26:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786994790; cv=none; b=iz8OWo20lHFENJhmA3EZmaqFgJKyQz1eAIw3/U0HznPM6okZrDfCXSMXapS7Eu2y7IqnVTSvXj/hl//gbnY6gD9hI1+TwR2IiVP2zHNUdo1g1o2RNkqefXiB2YYKc8Pofi7/oF7WjBWt9QFk+OjFXYThndJ3ztZgwCukVhNFTHQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786994790; c=relaxed/simple; bh=5Sea9MSDaveuQGC5x66kS1vUpcBCUa4zSrlhRTuadrk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ARgI/WV7mvONAkb4cLZ+MX7af1vlo+qTje780jqFyJCIwuMjjUmY6X6MNLcZjzCPDEU0qtnrgl30v0KGSnEqBBCo0dZesNzYyuKw1AmczNn8cfxodwsqfZCCwjdMggLDjqNlut+isHKWrNFksDTOyMMAnPq/8RByomCQPIqY3kc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=pmcDscJD; arc=none smtp.client-ip=209.85.214.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="pmcDscJD" Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-2d5cad1a6baso3007255ad.3 for ; Mon, 17 Aug 2026 12:26:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1786994788; x=1787599588; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=e1c+ZIyIJcvcVaUrDb5n7yyU/XX4DNS072WISoEr2to=; b=pmcDscJDxLD2MhSOt3Su5/TRgyasd19vcf/Mp63Yf3ZcGYNEIzku9ayZvonWBB8RWO kygfAMCjLM8/ayG6xq0h3vqmlD7kbr2NQvV/VMX+dWepRTWY7625osbQuxLZrQBBJVhB vHR2CVm6bkIy1hi7khxNy6vA8ZOeYA61GKD19HN7Ghlr0sUuuxlKsyK5PTQ0+PgJv+CC ufowpPbb4zy4+JE0Ojlri+cnJ7VFYDnW8yISZkTyE3yFaAqVXPCQkqHTxsFDiO5bZfYj vsmFLAT5wYhgzFLaqT6l2zP3OB0YR71kH+DsNDIGnXy7QLu3IFD3TSw/QNNVr8QIYQSl e0qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786994788; x=1787599588; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=e1c+ZIyIJcvcVaUrDb5n7yyU/XX4DNS072WISoEr2to=; b=U3dqP1REyRbJ/Z/FDC/KfTgxj3Y9rJv2RiaQkgr5nSKcq01dEdT43Zw7h7bQUFCVUI 8TI6o0I+80J9UCwj4GDwSAdNVcJ4HX8W8oNc0LTJprqTIsbD4yTDaHXsklX7wXAlUUhH L27Ym4cyKRTHcmTJZX12Khexpln76HJS7HZbZrpESoALlhqcFMq5/xqIVLoTCJ9g9bf2 8bslZ10vZ9KFgPK8tARyKmO3/gWthxOfmjSib08fgbN0jGNVw9XVBU7DUo7NA34DGrt8 LthUfgyQtXgUlnZbrJBK/+8CilXVLjig3h9RQREsApp2fYdZjL0xTpRkvl+Vhqqrr9Yu rRWw== X-Forwarded-Encrypted: i=1; AHgh+Rrqq1W++R3/PiPFTA/7i6Rs04JkE98bcdvzT3VGmzZeONyaq3fcleqN3dNc/bmAUqzXpN/2ddgJdnuQwl8=@vger.kernel.org X-Gm-Message-State: AOJu0YzUgcJv7HpoLV/gVyA7tnem9AzItOOqKtHwNYCg4QjBz5Iv2R1z kF2TM8jA9q4Q2p2II7Uo5PEWkB2pPRXxKY40yylAIGsxNanU7hv/YG7y X-Gm-Gg: AR+sD10ccfo9hz8Hk28/DeNCsTfwOp97us6Ebv6rBwmcNKHB3hY0NurTqz0X+WDkw7q tzFxDinrFl8H0vXwQX+eKgFBeTT83Bm+aurclHvyjoBAUI4Y5vRnweciyqtviSNqB4MDqR/eMeG rWI1X91nl0AFqGPJ2xMVC+qN7rQchKeHft4eCbfsU8KBFgzraRRF3CeuTasD7BBcfADLn/bcbx2 oPJMIsJntZnh0MMRFY+5hsDtgurzkhHGSAnbObhWOBUX/8Tmb70p8tuzf2UdTXS7WWVzBLA/swE LPUCk81AuXKfX+9UGZ66MtDpHusitXSRBLlvyHsZ+ZbN1IYcrt6Lb6a+afoOhOE99WA9eSjUOEa b2nYVIji4ddjJ1Pph7uAnzCASNuRKXWbexICQx9V8sW6O5LUmRJr0+HhSgMfSbpLzoXj/63nYZb iUMStWMvIQBSn89SeNL/uEosFI8jd1JQVTkhhgGJJB3x1GwQfnBe7+WNhAdw2vIXVSFVCkAgaa1 HR2JTfv+NxjGcatO8XDlDbln3/pTeJi7pimgk0vRR5PItsMd11y/+PVjk+7Im6IcjSYwA1hFgma 0rsQUoddOQ== X-Received: by 2002:a17:902:f64c:b0:2ce:b7b7:30e3 with SMTP id d9443c01a7336-2d5c53bf80amr23810365ad.17.1786994788023; Mon, 17 Aug 2026 12:26:28 -0700 (PDT) Received: from iku.example.org ([2401:4900:1c06:2735:f886:32ae:1e17:ec13]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-326798cb9f5sm10218757eec.13.2026.08.17.12.26.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Aug 2026 12:26:27 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Michael Turquette , Stephen Boyd , Brian Masney , Guenter Roeck , Wim Van Sebroeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v4 5/7] watchdog: rzv2h: Add syscon support for WDTDCR Date: Mon, 17 Aug 2026 20:25:38 +0100 Message-ID: <20260817192540.423994-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260817192540.423994-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260817192540.423994-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar On RZ/T2H and RZ/N2H SoCs, the WDTDCR (WDT Debug Control Register) resides in the second register region of the CPG/MSSR block. Since this multi-function block is shared with other peripherals, it is exposed via a syscon regmap interface. Look up the SYSC regmap using the optional "renesas,sysc" property and derive the WDTDCR offset from the watchdog instance index. Retain the existing MMIO-based access method when the "renesas,sysc" property is absent to preserve compatibility with existing DT's. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v3->v4: - No change v2->v3: - Made use of the new "renesas,sysc" phandle-array property to access the WDTDCR register via the CPG/MSSR syscon node. - Updated commit message v1->v2: - No change. --- drivers/watchdog/Kconfig | 1 + drivers/watchdog/rzv2h_wdt.c | 56 +++++++++++++++++++++++++++++------- 2 files changed, 46 insertions(+), 11 deletions(-) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index f7d0a0c2c0ef..3c4fc9916d8c 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -1046,6 +1046,7 @@ config RENESAS_RZV2HWDT depends on ARCH_RENESAS || COMPILE_TEST depends on PM || COMPILE_TEST select WATCHDOG_CORE + select MFD_SYSCON help This driver adds watchdog support for the integrated watchdogs in the Renesas RZ/{G3E,V2H(P)} SoCs. These watchdogs can be used to reset a diff --git a/drivers/watchdog/rzv2h_wdt.c b/drivers/watchdog/rzv2h_wdt.c index 8af2f33b5680..04ea962da837 100644 --- a/drivers/watchdog/rzv2h_wdt.c +++ b/drivers/watchdog/rzv2h_wdt.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -44,6 +45,11 @@ =20 #define WDT_DEFAULT_TIMEOUT 60U =20 +#define RZT2H_WDT_MAX_INSTANCES 6 + +#define RZT2H_SYS_BLOCK1(n) (BIT(16) | (0x5100 + (n) * 4)) +#define RZT2H_WDTDCR_OFFSET(n) RZT2H_SYS_BLOCK1(n) + static bool nowayout =3D WATCHDOG_NOWAYOUT; module_param(nowayout, bool, 0); MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (defau= lt=3D" @@ -64,14 +70,19 @@ struct rzv2h_of_data { bool wdtdcr; }; =20 +struct rzv2h_sysc_wdtdcr { + struct regmap *regmap; + unsigned int offset; +}; + struct rzv2h_wdt_priv { void __iomem *base; - struct regmap *wdtdcr_regmap; struct clk *pclk; struct clk *oscclk; struct reset_control *rstc; struct watchdog_device wdev; const struct rzv2h_of_data *of_data; + struct rzv2h_sysc_wdtdcr sysc; }; =20 static int rzv2h_wdt_ping(struct watchdog_device *wdev) @@ -90,12 +101,16 @@ static int rzv2h_wdt_ping(struct watchdog_device *wdev) =20 static int rzt2h_wdt_wdtdcr_count_stop(struct rzv2h_wdt_priv *priv) { - return regmap_set_bits(priv->wdtdcr_regmap, WDTDCR, WDTDCR_WDTSTOPCTRL); + struct rzv2h_sysc_wdtdcr *sysc =3D &priv->sysc; + + return regmap_set_bits(sysc->regmap, sysc->offset, WDTDCR_WDTSTOPCTRL); } =20 static int rzt2h_wdt_wdtdcr_count_start(struct rzv2h_wdt_priv *priv) { - return regmap_clear_bits(priv->wdtdcr_regmap, WDTDCR, WDTDCR_WDTSTOPCTRL); + struct rzv2h_sysc_wdtdcr *sysc =3D &priv->sysc; + + return regmap_clear_bits(sysc->regmap, sysc->offset, WDTDCR_WDTSTOPCTRL); } =20 static void rzv2h_wdt_setup(struct watchdog_device *wdev, u16 wdtcr) @@ -284,17 +299,36 @@ static const struct regmap_config rzv2h_wdtdcr_regmap= _config =3D { static int rzt2h_wdt_wdtdcr_init(struct platform_device *pdev, struct rzv2h_wdt_priv *priv) { - void __iomem *wdtdcr; + struct device_node *np =3D pdev->dev.of_node; + bool syscon_present =3D of_property_present(np, "renesas,sysc"); + struct rzv2h_sysc_wdtdcr *sysc =3D &priv->sysc; int ret; =20 - wdtdcr =3D devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(wdtdcr)) - return PTR_ERR(wdtdcr); + if (syscon_present) { + unsigned int wdt_index; =20 - priv->wdtdcr_regmap =3D devm_regmap_init_mmio(&pdev->dev, wdtdcr, - &rzv2h_wdtdcr_regmap_config); - if (IS_ERR(priv->wdtdcr_regmap)) - return PTR_ERR(priv->wdtdcr_regmap); + sysc->regmap =3D syscon_regmap_lookup_by_phandle_args(np, "renesas,sysc", + 1, &wdt_index); + if (IS_ERR(sysc->regmap)) + return PTR_ERR(sysc->regmap); + + if (wdt_index >=3D RZT2H_WDT_MAX_INSTANCES) + return -EINVAL; + + sysc->offset =3D RZT2H_WDTDCR_OFFSET(wdt_index); + } else { + void __iomem *wdtdcr; + + wdtdcr =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(wdtdcr)) + return PTR_ERR(wdtdcr); + + sysc->regmap =3D devm_regmap_init_mmio(&pdev->dev, wdtdcr, + &rzv2h_wdtdcr_regmap_config); + if (IS_ERR(sysc->regmap)) + return PTR_ERR(sysc->regmap); + sysc->offset =3D WDTDCR; + } =20 ret =3D pm_runtime_resume_and_get(&pdev->dev); if (ret) --=20 2.43.0 From nobody Mon Sep 28 20:06:51 2026 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC12B43C7DF for ; Mon, 17 Aug 2026 19:26:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786994797; cv=none; b=uqyYFZqb8DRufVugPMLI+TlWtCzb3cbxLqFGGqufQ+5nG3acg4yHOr4Fwbyiv+h58Tx/7kWlPsRpDxynQLCno2PmXTeQWk9p8VX2tH10Xpho4ELW2Ds6uGWNlAZn8nbuVZQGzGgWBwxMFvMN1Czc/Z/Ep1AA9PQiJPXg+CLJLpA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786994797; c=relaxed/simple; bh=sIvlwinupomxM3a2hWMmImtBO5VxdZ7EwFqpLwq+WFM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iENCTAFKZ60Ux+etzVq3CPKj5yWgbiHNkam3omnGj3NpxsUr5ahSHCwTZL+L8gMAs36FN6d+Jq5IsOLOCmAcsAoVaChtwsXefOP2tqI11ESM6Hu1MSQzyvcAbIef1bACJ6AvtYDqH/GnpGi95sgy5ozXns8Um7x9gAJhyVodZ6s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Tve+i3WF; arc=none smtp.client-ip=209.85.214.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Tve+i3WF" Received: by mail-pl1-f171.google.com with SMTP id d9443c01a7336-2cc891373e0so49380315ad.2 for ; Mon, 17 Aug 2026 12:26:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1786994795; x=1787599595; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=7ami9imt6GO00xjWzOm9H3fAjKzP3fMTgY6VhTdgPoQ=; b=Tve+i3WFWTnxLlhj2GPm3LSBnbGoO3pF0i3oRyRtM+T48AmZfrBaY+JbMZd9pAYLec xczMVuFJQHE0XsJ8JV66nV9+MV7y4m5gtR2USrLFDnK0Ommh3+flW6e8/dLYuU/f7H75 PVZTSfdh6Un+QEaLI7uOvT6yGRqKFbOA4rppDnokPS8NMHuICkOXM/ZvI2GUTbhuijAy 8Iq8eS/V9xnXQXB7wkxu5IoSivcyvxxbcRqNrrtAn7SVxo+GMuFu0xw4R8pr6wtVdM1E Hz7RECjZpUG7/VvlWONX3inJCEv2Y/f/PTiNgqM0NlX7eWuoM+VFk2XOcEeaxe9j6DuS KTIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786994795; x=1787599595; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=7ami9imt6GO00xjWzOm9H3fAjKzP3fMTgY6VhTdgPoQ=; b=rs9byKC0LABrgdDoguGLrihHGVBO2JJuOV2jGr/mJEi8anjYm/IYDeKUy45W5MWHgr bCwK44THgf3/BJ2U4e/20a6GnG5C4/KtrI9hzyQThg5J4TTrLsN6If+m8o+n2ot/waOo aBDKj3Vfh/YJ4Z5xnxMndCQpy5jLbFG1Lw6CyILQ28E7AMjsu/21iZoG+Wp2cjQIZ35/ QwaBvcQMDT4ph5mxI/GUfEN36WhNkiB3oiJHE2QMCKpoK9swPx9+iUAGTwpfDp415RHx AbyygRDNnwN/BB+eMXUMZBcbymGb8okwEU83LY+TMA9EC0jcoW/8NrHGlZT0bSIh6mYM Kw4Q== X-Forwarded-Encrypted: i=1; AHgh+RrOO677vnAFIhEIqo+YHZrYWTa7GqMi8EWmasLtYe6RnnwXaYrmzJS6aMS3L6r+z2GMhUU8irA2Np3vIkk=@vger.kernel.org X-Gm-Message-State: AOJu0YyXc2Pk/Ngev48Zyt/zZ2MI6m2+D9fAs9Zempw5CNvmfj/H1183 eHvYeGTduzwGpVbqy7ZER1MeAH9MHuCmH/OZ3VnCY0n8ayXXG8xdQeb9 X-Gm-Gg: AR+sD13CmPr5P0gnLH389AdCCeSp/CwhK3CyOlzYqnrMLgl7Iu1h+8zBVInAxuLbmY8 g62EFaNmwtwyVAme2NHmycW+fvdVTTzHIDsGIlR6yoReK8ZxsX2lNSJAgXXNnAMe82nTzclsu0g Kb0mPAnBvI1vKM0Ox1HIALyyL9TaglxhDNrs0dip5xMcOQf0f/Bxaqo9XUmxbA77vzGPAubQ/SY n7VpIw9wYP4GYZRxmommeSXdkCCN6x3KmeuhgkwRm0SvcKp1uoXnU6J6cmSn69CHfAnWLAGB8nx gs+y1m4B/zrqPXdwUKNZkMjWqvYF+q4EdLc52Xtmt4l/8ubLpvVIMuOKYhJY7IcgSXR5w1WhSLF 6KtF8FkZS70nORzcZaDAp8jnMBkayg1QSd/9rxld82aA8aqg1Wi5wpIfWfehXezF3QBKb/fEljU Q4vCm4TuDOM86bSbtPZI1dHsUOe7h+aUFKqdXC9wm7ivDC7iwAkbj/UMtYosRkI630CeTiGDNSZ rmv98JJIAmOTlg0x2XxDRMGC0NW2QopHw+MywspuyReSc2DEjKTYggzkRk4ipa/tyIf0MFVuxNW Ya4cYDpTCl4= X-Received: by 2002:a17:903:3885:b0:2ca:e62c:9e96 with SMTP id d9443c01a7336-2d3b0d78794mr281621245ad.5.1786994795153; Mon, 17 Aug 2026 12:26:35 -0700 (PDT) Received: from iku.example.org ([2401:4900:1c06:2735:f886:32ae:1e17:ec13]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-326798cb9f5sm10218757eec.13.2026.08.17.12.26.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Aug 2026 12:26:34 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Michael Turquette , Stephen Boyd , Brian Masney , Guenter Roeck , Wim Van Sebroeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v4 6/7] arm64: dts: renesas: r9a09g077: Use CPG/MSSR syscon for WDTDCR access Date: Mon, 17 Aug 2026 20:25:39 +0100 Message-ID: <20260817192540.423994-7-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260817192540.423994-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260817192540.423994-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar The WDTDCR registers for wdt0-wdt5 reside in the second register region of the CPG/MSSR block. This multi-function block is now exposed via a unified syscon regmap interface. Replace the direct mapping of the individual WDTDCR registers with the new "renesas,sysc" phandle property pointing to the CPG/MSSR block syscon node. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v3->v4: - No change v2->v3: - Renamed the "renesas,sys" property to "renesas,sysc" - Updated commit message v1->v2: - No change. --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 24 +++++++++++----------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g077.dtsi index de20bed2797b..80910e0bd977 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -327,61 +327,61 @@ channel1 { =20 wdt0: watchdog@80082000 { compatible =3D "renesas,r9a09g077-wdt"; - reg =3D <0 0x80082000 0 0x400>, - <0 0x81295100 0 0x04>; + reg =3D <0 0x80082000 0 0x400>; clocks =3D <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; clock-names =3D "pclk"; power-domains =3D <&cpg>; + renesas,sysc =3D <&cpg 0>; status =3D "disabled"; }; =20 wdt1: watchdog@80082400 { compatible =3D "renesas,r9a09g077-wdt"; - reg =3D <0 0x80082400 0 0x400>, - <0 0x81295104 0 0x04>; + reg =3D <0 0x80082400 0 0x400>; clocks =3D <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; clock-names =3D "pclk"; power-domains =3D <&cpg>; + renesas,sysc =3D <&cpg 1>; status =3D "disabled"; }; =20 wdt2: watchdog@80082800 { compatible =3D "renesas,r9a09g077-wdt"; - reg =3D <0 0x80082800 0 0x400>, - <0 0x81295108 0 0x04>; + reg =3D <0 0x80082800 0 0x400>; clocks =3D <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; clock-names =3D "pclk"; power-domains =3D <&cpg>; + renesas,sysc =3D <&cpg 2>; status =3D "disabled"; }; =20 wdt3: watchdog@80082c00 { compatible =3D "renesas,r9a09g077-wdt"; - reg =3D <0 0x80082c00 0 0x400>, - <0 0x8129510c 0 0x04>; + reg =3D <0 0x80082c00 0 0x400>; clocks =3D <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; clock-names =3D "pclk"; power-domains =3D <&cpg>; + renesas,sysc =3D <&cpg 3>; status =3D "disabled"; }; =20 wdt4: watchdog@80083000 { compatible =3D "renesas,r9a09g077-wdt"; - reg =3D <0 0x80083000 0 0x400>, - <0 0x81295110 0 0x04>; + reg =3D <0 0x80083000 0 0x400>; clocks =3D <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; clock-names =3D "pclk"; power-domains =3D <&cpg>; + renesas,sysc =3D <&cpg 4>; status =3D "disabled"; }; =20 wdt5: watchdog@80083400 { compatible =3D "renesas,r9a09g077-wdt"; - reg =3D <0 0x80083400 0 0x400>, - <0 0x81295114 0 0x04>; + reg =3D <0 0x80083400 0 0x400>; clocks =3D <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; clock-names =3D "pclk"; power-domains =3D <&cpg>; + renesas,sysc =3D <&cpg 5>; status =3D "disabled"; }; =20 --=20 2.43.0 From nobody Mon Sep 28 20:06:51 2026 Received: from mail-pg1-f173.google.com (mail-pg1-f173.google.com [209.85.215.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED9D04248CF for ; Mon, 17 Aug 2026 19:26:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786994805; cv=none; b=QwWQAnNOAqvNRNt64xEEnqlc7JLv5Lj4v726/2r6mmmS8zGgtYw9svnyEaEV5qkXMx5243Vx4F5f7ZRVw912C608im1sdfpbUTuAkBXLUSaX6lmeSEHI6CK+GPifGjYQDlLr+64s36uBRHsFWOTJ+Rz309BMDmNhKwl4sjuaRhA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786994805; c=relaxed/simple; bh=NdEBnCUmI8vcYieObvf0+R8QSjffR1RfAbs59Qz31Tk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JiFHT1+kEoNzrlyBRbghPhFbOlY+/RN9PFm8crWByKpf4wU11O00Hfx84j6rcftKAC6KK3tHruuuU6sTk2/Rqcw1oImi8BPgHI7nqyQFRq1azE/Ntx83W4SYwEzsIHTZFg9sEAk+xsZr5eK/sQFiOu14VbPgQgarsPhluYF+FCI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Jl2dhQhe; arc=none smtp.client-ip=209.85.215.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Jl2dhQhe" Received: by mail-pg1-f173.google.com with SMTP id 41be03b00d2f7-c9cf07d2df6so2333508a12.2 for ; Mon, 17 Aug 2026 12:26:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1786994802; x=1787599602; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=8JDfCvRVlnDBvbOdUSOi/Q4nr+3vb687RKt9hvjxArk=; b=Jl2dhQheuNrwubvdWus4MPnDpjK1XeduDhXOesEw2fqw9i5gr17+OjVam1Rg3UvMkP aeZcoLX/avqt8ScGTubj/gQkXVs82LSanCje1Smi+kaN8zc/JvfPMyxH7G47TpSEDexy JAYG640Cb0fBtrSdCss9Lhk+QeIYBqn0lbFMGnrk5rbVFAWSHrBLQgZgZyUO2SX0gs2H nZbjrQu9we6s4+GmL00DKT8HbKKVLDNbIQEhwvFKUyndK5YqsbMyO0nRqsy8WbJmA6w9 PCfmCWkQsNMHKvF4VKdcKHARtvgKRfvVCzWCTqDmTDVLfHcrJoKyV6vFSqJdpAk7F/1m xRDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786994802; x=1787599602; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=8JDfCvRVlnDBvbOdUSOi/Q4nr+3vb687RKt9hvjxArk=; b=IDZpczd806qs2cwjj6+aQpQGOI/Q8w3lF+vMa0XL43nFCBuB/Cd4jTTeb4RQ+y50iS FdkeMWf5KJJxx1TdzlF/gjHPR7LRoir/TztGXZ5pn2WTTuUToIojot71M4wDu5p0m5Np /BYACSyWjYKOxLboPI0QYwvBTTQOV2nybaORUm7pHK3CbBAoidzapLRi9mKglXyEah1l ClSXAOsFDzoh27hTu2SWT/1dS7f05zAGkVcPTrnZvJw3NFyhSxsUQ6yA8XXENM3yp+SS 4O15kZFDGuaJFb8JHlAHsu1kdPx9LhjwF3Otapred1kb15eU+sDUo9mQCZ82ygi/HzKh bO7A== X-Forwarded-Encrypted: i=1; AHgh+RpS9jdBP9du3VAk7pdYAg4Va0+wwnkgz4yHdj/irFGfgmHiiPCHxnrFG6gmvx8oCgaYq9FSa8MbheNFRHE=@vger.kernel.org X-Gm-Message-State: AOJu0Yx3cIhkEVtjjTbbaaP1/6ySAqIT/llKBEgmKbz0aa95JR2cVL+p kWk+2DYnqKa1+Vj2xEeYnpZbn5jke+muXNml8oqp931fNIanFAOJYcU5KmVaCdGy X-Gm-Gg: AR+sD11BdsWCp8++3CVClx0obUo0HxMEzQwsvkShztMoJvA1EtF8+Nlz2RTD8swC6xx RgzovExyC1wKGAjZlHEobbaVMnRoZozZ0WH/F9UbzY/HdtmMIjlE9dYs89Zvkg//CCfNdtRqpp+ GGvSpmAGl1lG+TLsKzNdXFg4Ylnr17yuNNeKJkD2Zgps+CryjnSBGixoW6XKXpdVig7MiU7QfOd b7+GSI30v2gyawg6yOmlVE/4UqKZqgjAAEA3IuUAsdDlc3KuanJnI4cLV6uS2M9X8mtY3HGGVlV sZvg2DDv7ArKJ0yzGLzMc/u/pen6ciuILjS4Qp6kOTQdxvEa9VLGyv4q2KabsfSyRUxv3OzSBYB +5cnPeGpf+mo6FMIgHe++bg8hxqQzmpwr/5VUiv9nxHGasdpi/DYr+drA6QiD9SFXAodnx7Chlr jghNWuLEzhUWYl76yTdNggp9IkcjJPNLB28vWO01b1qy8ZF/AHDEanIhx6VsjE+fGui3FPc7ubY cTQ4yr9ze2cG8v5Mx442SzxMlx3FUO95vEdCyuPCu5UGn+ENdCyHYA1lc75+ABXoi/TwYhat3uj BKAaIMJJaA== X-Received: by 2002:a05:6a21:134b:b0:3c3:875d:7053 with SMTP id adf61e73a8af0-3ccda403574mr3047275637.8.1786994802009; Mon, 17 Aug 2026 12:26:42 -0700 (PDT) Received: from iku.example.org ([2401:4900:1c06:2735:f886:32ae:1e17:ec13]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-326798cb9f5sm10218757eec.13.2026.08.17.12.26.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Aug 2026 12:26:41 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Michael Turquette , Stephen Boyd , Brian Masney , Guenter Roeck , Wim Van Sebroeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v4 7/7] arm64: dts: renesas: r9a09g087: Use CPG/MSSR syscon for WDTDCR access Date: Mon, 17 Aug 2026 20:25:40 +0100 Message-ID: <20260817192540.423994-8-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260817192540.423994-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260817192540.423994-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar The WDTDCR registers for wdt0-wdt5 reside in the second register region of the CPG/MSSR block. This multi-function block is now exposed via a unified syscon regmap interface. Replace the direct mapping of the individual WDTDCR registers with the new "renesas,sysc" phandle property pointing to the CPG/MSSR block syscon node. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v3->v4: - No change v2->v3: - Renamed the "renesas,sys" property to "renesas,sysc" - Updated commit message v1->v2: - No change. --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 24 +++++++++++----------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g087.dtsi index 813bb0cb021c..3ede2e89cf67 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -327,61 +327,61 @@ channel1 { =20 wdt0: watchdog@80082000 { compatible =3D "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; - reg =3D <0 0x80082000 0 0x400>, - <0 0x81295100 0 0x04>; + reg =3D <0 0x80082000 0 0x400>; clocks =3D <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; clock-names =3D "pclk"; power-domains =3D <&cpg>; + renesas,sysc =3D <&cpg 0>; status =3D "disabled"; }; =20 wdt1: watchdog@80082400 { compatible =3D "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; - reg =3D <0 0x80082400 0 0x400>, - <0 0x81295104 0 0x04>; + reg =3D <0 0x80082400 0 0x400>; clocks =3D <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; clock-names =3D "pclk"; power-domains =3D <&cpg>; + renesas,sysc =3D <&cpg 1>; status =3D "disabled"; }; =20 wdt2: watchdog@80082800 { compatible =3D "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; - reg =3D <0 0x80082800 0 0x400>, - <0 0x81295108 0 0x04>; + reg =3D <0 0x80082800 0 0x400>; clocks =3D <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; clock-names =3D "pclk"; power-domains =3D <&cpg>; + renesas,sysc =3D <&cpg 2>; status =3D "disabled"; }; =20 wdt3: watchdog@80082c00 { compatible =3D "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; - reg =3D <0 0x80082c00 0 0x400>, - <0 0x8129510c 0 0x04>; + reg =3D <0 0x80082c00 0 0x400>; clocks =3D <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; clock-names =3D "pclk"; power-domains =3D <&cpg>; + renesas,sysc =3D <&cpg 3>; status =3D "disabled"; }; =20 wdt4: watchdog@80083000 { compatible =3D "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; - reg =3D <0 0x80083000 0 0x400>, - <0 0x81295110 0 0x04>; + reg =3D <0 0x80083000 0 0x400>; clocks =3D <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; clock-names =3D "pclk"; power-domains =3D <&cpg>; + renesas,sysc =3D <&cpg 4>; status =3D "disabled"; }; =20 wdt5: watchdog@80083400 { compatible =3D "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; - reg =3D <0 0x80083400 0 0x400>, - <0 0x81295114 0 0x04>; + reg =3D <0 0x80083400 0 0x400>; clocks =3D <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; clock-names =3D "pclk"; power-domains =3D <&cpg>; + renesas,sysc =3D <&cpg 5>; status =3D "disabled"; }; =20 --=20 2.43.0