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charset="utf-8" struct rzt2h_pinctrl::used_irqs is supposed to be indexed based on the parent IRQ number. Do the translation using rzt2h_gpio_irq_map and clear it properly. Cc: stable@kernel.org Fixes: 829dde3369a9 ("pinctrl: renesas: rzt2h: Add GPIO IRQ chip to handle = interrupts") Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzt2h.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzt2h.c b/drivers/pinctrl/rene= sas/pinctrl-rzt2h.c index eb70aee39f1a..a37f1e399446 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c @@ -1050,8 +1050,13 @@ static void rzt2h_gpio_irq_domain_free(struct irq_do= main *domain, unsigned int v irq_hw_number_t hwirq =3D irqd_to_hwirq(d); u8 port =3D RZT2H_PIN_ID_TO_PORT(hwirq); u8 pin =3D RZT2H_PIN_ID_TO_PIN(hwirq); + u8 parent_irq; =20 - if (test_and_clear_bit(hwirq - RZT2H_INTERRUPTS_START, pctrl->used_irqs)) + parent_irq =3D rzt2h_gpio_irq_map[hwirq]; + if (parent_irq < RZT2H_INTERRUPTS_START) + return; + + if (test_and_clear_bit(parent_irq - RZT2H_INTERRUPTS_START, pctrl->used_i= rqs)) rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, false); 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charset="utf-8" rzt2h_gpio_irq_domain_free() calls rzt2h_pinctrl_set_gpio_en() with false leaving the pin in interrupt function instead of returning it to GPIO mode. Pass true to rzt2h_pinctrl_set_gpio_en() to take the pin out of interrupt function after we're done using it as an IRQ. rzt2h_pinctrl_set_pfc_mode() switches the pin to Hi-Z, losing the previous PM value. Save the PM value before switching to Hi-Z, and restore it after the IRQ is freed. Cc: stable@kernel.org Fixes: 829dde3369a9 ("pinctrl: renesas: rzt2h: Add GPIO IRQ chip to handle = interrupts") Signed-off-by: Cosmin Tanislav --- drivers/pinctrl/renesas/pinctrl-rzt2h.c | 42 +++++++++++++++++++++---- 1 file changed, 36 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzt2h.c b/drivers/pinctrl/rene= sas/pinctrl-rzt2h.c index a37f1e399446..82fe9b5e8f72 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c @@ -96,6 +96,7 @@ struct rzt2h_pinctrl { struct gpio_chip gpio_chip; struct pinctrl_gpio_range gpio_range; DECLARE_BITMAP(used_irqs, RZT2H_INTERRUPTS_NUM); + u8 saved_pm[RZT2H_INTERRUPTS_NUM]; raw_spinlock_t lock; /* lock read/write registers */ struct mutex mutex; /* serialize adding groups and functions */ bool safety_port_enabled; @@ -170,6 +171,25 @@ static int rzt2h_validate_pin(struct rzt2h_pinctrl *pc= trl, unsigned int offset) return (pincfg & BIT(pin)) ? 0 : -EINVAL; } =20 +static u8 rzt2h_pin_read_pm(struct rzt2h_pinctrl *pctrl, u8 port, u8 pin) +{ + u16 reg =3D rzt2h_pinctrl_readw(pctrl, port, PM(port)); + + return field_get(PM_PIN_MASK(pin), reg); +} + +static void rzt2h_pin_write_pm(struct rzt2h_pinctrl *pctrl, u8 port, u8 pi= n, u8 pm) +{ + u16 reg; + + guard(raw_spinlock_irqsave)(&pctrl->lock); + + reg =3D rzt2h_pinctrl_readw(pctrl, port, PM(port)); + reg &=3D ~PM_PIN_MASK(pin); + reg |=3D (u16)pm << (pin * 2); + rzt2h_pinctrl_writew(pctrl, port, reg, PM(port)); +} + static void rzt2h_pinctrl_set_gpio_en(struct rzt2h_pinctrl *pctrl, u8 port, u8 pin, bool en) { @@ -1023,16 +1043,23 @@ static int rzt2h_gpio_child_to_parent_hwirq(struct = gpio_chip *gc, struct rzt2h_pinctrl *pctrl =3D gpiochip_get_data(gc); u8 port =3D RZT2H_PIN_ID_TO_PORT(child); u8 pin =3D RZT2H_PIN_ID_TO_PIN(child); - u8 parent_irq; + u8 parent_irq, irq_idx; =20 parent_irq =3D rzt2h_gpio_irq_map[child]; if (parent_irq < RZT2H_INTERRUPTS_START) return -EINVAL; =20 - if (test_and_set_bit(parent_irq - RZT2H_INTERRUPTS_START, - pctrl->used_irqs)) + irq_idx =3D parent_irq - RZT2H_INTERRUPTS_START; + if (test_and_set_bit(irq_idx, pctrl->used_irqs)) return -EBUSY; =20 + /* + * rzt2h_pinctrl_set_pfc_mode() sets PM to Hi-Z before switching to the + * interrupt function, losing the previous PM value. + * Save it so it can be restored when the IRQ is freed. + */ + pctrl->saved_pm[irq_idx] =3D rzt2h_pin_read_pm(pctrl, port, pin); + rzt2h_pinctrl_set_pfc_mode(pctrl, port, pin, PFC_FUNC_INTERRUPT); =20 *parent =3D parent_irq; @@ -1050,14 +1077,17 @@ static void rzt2h_gpio_irq_domain_free(struct irq_d= omain *domain, unsigned int v irq_hw_number_t hwirq =3D irqd_to_hwirq(d); u8 port =3D RZT2H_PIN_ID_TO_PORT(hwirq); u8 pin =3D RZT2H_PIN_ID_TO_PIN(hwirq); - u8 parent_irq; + u8 parent_irq, irq_idx; =20 parent_irq =3D rzt2h_gpio_irq_map[hwirq]; if (parent_irq < RZT2H_INTERRUPTS_START) return; =20 - if (test_and_clear_bit(parent_irq - RZT2H_INTERRUPTS_START, pctrl->used_i= rqs)) - rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, false); + irq_idx =3D parent_irq - RZT2H_INTERRUPTS_START; + if (test_and_clear_bit(irq_idx, pctrl->used_irqs)) { + rzt2h_pin_write_pm(pctrl, port, pin, pctrl->saved_pm[irq_idx]); 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charset="utf-8" When exporting a GPIO using the deprecated sysfs GPIO API, gpio_is_visible() calls gpiod_to_irq() to determine whether a GPIO is IRQ-capable, which ends up using struct gpio_irq_chip::child_to_parent_hwirq(). When using the GPIO character device, it is possible to request a line and to dynamically switch between using it as an IRQ or as a GPIO, by updating the edge detector. The current struct gpio_irq_chip::child_to_parent_hwirq() implementation makes the assumption that it will only be called with the intention of setting up the IRQ permanently, and that it will only be released when the IRQ domain is freed. Since we now know that this is not the case, take the following steps in order to properly handle that case. Implement struct irq_chip::irq_{request,release}_resources() based on the default GPIOCHIP_IRQ_RESOURCE_HELPERS implementations. Move the IRQ setup and release logic inside them. Keep the mapping logic inside ::child_to_parent_hwirq() to be able to provide a proper HW IRQ number, but do not actually setup the IRQ. Remove rzt2h_gpio_irq_domain_free() as its only purpose was to free the acquired IRQs. Cc: stable@kernel.org Fixes: 829dde3369a9 ("pinctrl: renesas: rzt2h: Add GPIO IRQ chip to handle = interrupts") Signed-off-by: Cosmin Tanislav --- drivers/pinctrl/renesas/pinctrl-rzt2h.c | 79 +++++++++++++++---------- 1 file changed, 49 insertions(+), 30 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzt2h.c b/drivers/pinctrl/rene= sas/pinctrl-rzt2h.c index 82fe9b5e8f72..287cacbcb37b 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c @@ -1020,32 +1020,17 @@ static int rzt2h_gpio_irq_set_wake(struct irq_data = *d, unsigned int on) return 0; } =20 -static const struct irq_chip rzt2h_gpio_irqchip =3D { - .name =3D "rzt2h-gpio", - .irq_disable =3D rzt2h_gpio_irq_disable, - .irq_enable =3D rzt2h_gpio_irq_enable, - .irq_mask =3D irq_chip_mask_parent, - .irq_unmask =3D irq_chip_unmask_parent, - .irq_set_type =3D irq_chip_set_type_parent, - .irq_set_wake =3D rzt2h_gpio_irq_set_wake, - .irq_eoi =3D irq_chip_eoi_parent, - .irq_set_affinity =3D irq_chip_set_affinity_parent, - .flags =3D IRQCHIP_IMMUTABLE, - GPIOCHIP_IRQ_RESOURCE_HELPERS, -}; - -static int rzt2h_gpio_child_to_parent_hwirq(struct gpio_chip *gc, - unsigned int child, - unsigned int child_type, - unsigned int *parent, - unsigned int *parent_type) +static int rzt2h_gpio_irq_request_resources(struct irq_data *d) { + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct rzt2h_pinctrl *pctrl =3D gpiochip_get_data(gc); - u8 port =3D RZT2H_PIN_ID_TO_PORT(child); - u8 pin =3D RZT2H_PIN_ID_TO_PIN(child); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + u8 port =3D RZT2H_PIN_ID_TO_PORT(hwirq); + u8 pin =3D RZT2H_PIN_ID_TO_PIN(hwirq); u8 parent_irq, irq_idx; + int ret; =20 - parent_irq =3D rzt2h_gpio_irq_map[child]; + parent_irq =3D rzt2h_gpio_irq_map[hwirq]; if (parent_irq < RZT2H_INTERRUPTS_START) return -EINVAL; =20 @@ -1062,18 +1047,21 @@ static int rzt2h_gpio_child_to_parent_hwirq(struct = gpio_chip *gc, =20 rzt2h_pinctrl_set_pfc_mode(pctrl, port, pin, PFC_FUNC_INTERRUPT); =20 - *parent =3D parent_irq; - *parent_type =3D child_type; + ret =3D gpiochip_lock_as_irq(gc, hwirq); + if (ret) { + clear_bit(parent_irq - RZT2H_INTERRUPTS_START, pctrl->used_irqs); + rzt2h_pin_write_pm(pctrl, port, pin, pctrl->saved_pm[irq_idx]); + rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, true); + return ret; + } =20 return 0; } =20 -static void rzt2h_gpio_irq_domain_free(struct irq_domain *domain, unsigned= int virq, - unsigned int nr_irqs) +static void rzt2h_gpio_irq_release_resources(struct irq_data *d) { - struct irq_data *d =3D irq_domain_get_irq_data(domain, virq); struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); - struct rzt2h_pinctrl *pctrl =3D container_of(gc, struct rzt2h_pinctrl, gp= io_chip); + struct rzt2h_pinctrl *pctrl =3D gpiochip_get_data(gc); irq_hw_number_t hwirq =3D irqd_to_hwirq(d); u8 port =3D RZT2H_PIN_ID_TO_PORT(hwirq); u8 pin =3D RZT2H_PIN_ID_TO_PIN(hwirq); @@ -1089,7 +1077,39 @@ static void rzt2h_gpio_irq_domain_free(struct irq_do= main *domain, unsigned int v rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, true); } =20 - irq_domain_free_irqs_common(domain, virq, nr_irqs); + gpiochip_unlock_as_irq(gc, hwirq); +} + +static const struct irq_chip rzt2h_gpio_irqchip =3D { + .name =3D "rzt2h-gpio", + .irq_disable =3D rzt2h_gpio_irq_disable, + .irq_enable =3D rzt2h_gpio_irq_enable, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_set_type =3D irq_chip_set_type_parent, + .irq_set_wake =3D rzt2h_gpio_irq_set_wake, + .irq_eoi =3D irq_chip_eoi_parent, + .irq_request_resources =3D rzt2h_gpio_irq_request_resources, + .irq_release_resources =3D rzt2h_gpio_irq_release_resources, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_IMMUTABLE, +}; + +static int rzt2h_gpio_child_to_parent_hwirq(struct gpio_chip *gc, + unsigned int child, + unsigned int child_type, + unsigned int *parent, + unsigned int *parent_type) +{ + u8 parent_irq =3D rzt2h_gpio_irq_map[child]; + + if (parent_irq < RZT2H_INTERRUPTS_START) + return -EINVAL; + + *parent =3D parent_irq; + *parent_type =3D child_type; + + return 0; } =20 static void rzt2h_gpio_init_irq_valid_mask(struct gpio_chip *gc, @@ -1157,7 +1177,6 @@ static int rzt2h_gpio_register(struct rzt2h_pinctrl *= pctrl) girq->parent_domain =3D parent_domain; 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charset="utf-8" rzt2h_gpio_get() only reports a level for pins in input or output mode and returns -EINVAL otherwise. When a pin is requested as an interrupt it is switched to IRQ function and its I/O mode is set to Hi-Z, so its value can no longer be read. gpiolib calls gpiod_get_value_cansleep() to determine the edge's direction when a line is watched with GPIO_V2_LINE_FLAG_EDGE_BOTH. Non-zero values are translated to a rising edge, zero to a falling edge. Since gpiod_get_value_cansleep() ends up calling rzt2h_gpio_get() which returns -EINVAL when the pin is in IRQ function, every edge is reported as rising. When using the IRQ function, the input buffers are enabled and the PINm registers reflect the live state of the input. Report the input level even when the pin is used as an IRQ. Cc: stable@kernel.org Fixes: 829dde3369a9 ("pinctrl: renesas: rzt2h: Add GPIO IRQ chip to handle = interrupts") Signed-off-by: Cosmin Tanislav --- drivers/pinctrl/renesas/pinctrl-rzt2h.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzt2h.c b/drivers/pinctrl/rene= sas/pinctrl-rzt2h.c index 287cacbcb37b..b8d5b6af5be4 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c @@ -171,6 +171,23 @@ static int rzt2h_validate_pin(struct rzt2h_pinctrl *pc= trl, unsigned int offset) return (pincfg & BIT(pin)) ? 0 : -EINVAL; } =20 +static bool rzt2h_pin_mode_is_peripheral(struct rzt2h_pinctrl *pctrl, u8 p= ort, u8 bit) +{ + return rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit); +} + +static u8 rzt2h_pin_read_pfc(struct rzt2h_pinctrl *pctrl, u8 port, u8 pin) +{ + u64 reg64 =3D rzt2h_pinctrl_readq(pctrl, port, PFC(port)); + + return field_get(PFC_PIN_MASK(pin), reg64); +} + +static bool rzt2h_pin_read_input(struct rzt2h_pinctrl *pctrl, u8 port, u8 = bit) +{ + return rzt2h_pinctrl_readb(pctrl, port, PIN(port)) & BIT(bit); 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charset="utf-8" Wire up struct gpio_chip::set_config to allow GPIO settings via pinctrl. Signed-off-by: Cosmin Tanislav Reviewed-by: Bartosz Golaszewski Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzt2h.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzt2h.c b/drivers/pinctrl/rene= sas/pinctrl-rzt2h.c index b8d5b6af5be4..3e33543953a1 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c @@ -1192,6 +1192,7 @@ static int rzt2h_gpio_register(struct rzt2h_pinctrl *= pctrl) chip->direction_output =3D rzt2h_gpio_direction_output; chip->get =3D rzt2h_gpio_get; chip->set =3D rzt2h_gpio_set; + chip->set_config =3D gpiochip_generic_config; chip->label =3D dev_name(dev); =20 if (of_property_present(np, "interrupt-controller")) { --=20 2.55.0 From nobody Mon Sep 28 20:09:33 2026 Received: from TY3P286CU002.outbound.protection.outlook.com (mail-japaneastazon11010036.outbound.protection.outlook.com [52.101.229.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1ACF93B14A4; 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Tue, 18 Aug 2026 03:58:25 +0900 (JST) From: Cosmin Tanislav To: Geert Uytterhoeven , Linus Walleij , Bartosz Golaszewski , Cosmin Tanislav Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/7] pinctrl: renesas: rzt2h: remove unused struct rzt2h_pinctrl::gpio_range Date: Mon, 17 Aug 2026 21:56:59 +0300 Message-ID: <20260817185700.322370-7-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260817185700.322370-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20260817185700.322370-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYO1EPF00005020:EE_|OS9PR01MB12342:EE_ X-MS-Office365-Filtering-Correlation-Id: f37789d7-736f-4668-fcb6-08defc91865e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700016|23010399003|22082099003|56012099006|18002099003|11063799006|10067099003; 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charset="utf-8" The struct rzt2h_pinctrl::gpio_range field is unused and seems to be a vestige of calling pinctrl_add_gpio_range(). Remove it. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzt2h.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzt2h.c b/drivers/pinctrl/rene= sas/pinctrl-rzt2h.c index 3e33543953a1..525ccea344bd 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c @@ -94,7 +94,6 @@ struct rzt2h_pinctrl { void __iomem *base0, *base1; struct device *dev; struct gpio_chip gpio_chip; - struct pinctrl_gpio_range gpio_range; DECLARE_BITMAP(used_irqs, RZT2H_INTERRUPTS_NUM); u8 saved_pm[RZT2H_INTERRUPTS_NUM]; raw_spinlock_t lock; /* lock read/write registers */ @@ -1151,7 +1150,6 @@ static void rzt2h_gpio_init_irq_valid_mask(struct gpi= o_chip *gc, =20 static int rzt2h_gpio_register(struct rzt2h_pinctrl *pctrl) { - struct pinctrl_gpio_range *range =3D &pctrl->gpio_range; struct gpio_chip *chip =3D &pctrl->gpio_chip; struct device_node *np =3D pctrl->dev->of_node; struct irq_domain *parent_domain; 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charset="utf-8" The PMCm peripheral-mode test, the PFCm function read, the PINm input read, the PMm write, and the PMm read are open-coded in several places. Reuse the already existing helpers. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzt2h.c | 39 +++++++++---------------- 1 file changed, 13 insertions(+), 26 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzt2h.c b/drivers/pinctrl/rene= sas/pinctrl-rzt2h.c index 525ccea344bd..d7f02fbb6a12 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c @@ -229,7 +229,7 @@ static void rzt2h_pinctrl_set_pfc_mode(struct rzt2h_pin= ctrl *pctrl, =20 reg64 =3D rzt2h_pinctrl_readq(pctrl, port, PFC(port)); /* Check if pin is already configured to the desired function */ - if ((rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(pin)) && + if (rzt2h_pin_mode_is_peripheral(pctrl, port, pin) && field_get(PFC_PIN_MASK(pin), reg64) =3D=3D func) return; =20 @@ -783,15 +783,7 @@ static int rzt2h_gpio_request(struct gpio_chip *chip, = unsigned int offset) static void rzt2h_gpio_set_direction(struct rzt2h_pinctrl *pctrl, u32 port, u8 bit, bool output) { - u16 reg; - - guard(raw_spinlock_irqsave)(&pctrl->lock); - - reg =3D rzt2h_pinctrl_readw(pctrl, port, PM(port)); - reg &=3D ~PM_PIN_MASK(bit); - - reg |=3D (output ? PM_OUTPUT : PM_INPUT) << (bit * 2); - rzt2h_pinctrl_writew(pctrl, port, reg, PM(port)); + rzt2h_pin_write_pm(pctrl, port, bit, output ? PM_OUTPUT : PM_INPUT); } =20 static int rzt2h_gpio_get_direction(struct gpio_chip *chip, unsigned int o= ffset) @@ -799,9 +791,8 @@ static int rzt2h_gpio_get_direction(struct gpio_chip *c= hip, unsigned int offset) struct rzt2h_pinctrl *pctrl =3D gpiochip_get_data(chip); u8 port =3D RZT2H_PIN_ID_TO_PORT(offset); u8 bit =3D RZT2H_PIN_ID_TO_PIN(offset); - u64 reg64; - u16 reg; int ret; + u8 pm; =20 ret =3D rzt2h_validate_pin(pctrl, offset); if (ret) @@ -809,7 +800,7 @@ static int rzt2h_gpio_get_direction(struct gpio_chip *c= hip, unsigned int offset) =20 guard(raw_spinlock_irqsave)(&pctrl->lock); =20 - if (rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit)) { + if (rzt2h_pin_mode_is_peripheral(pctrl, port, bit)) { /* * When a GPIO is being requested as an IRQ, the pinctrl * framework expects to be able to read the GPIO's direction. @@ -819,19 +810,16 @@ static int rzt2h_gpio_get_direction(struct gpio_chip = *chip, unsigned int offset) * called to enable the IRQ function. * Default to input direction for IRQ function. */ - reg64 =3D rzt2h_pinctrl_readq(pctrl, port, PFC(port)); - reg64 =3D (reg64 >> (bit * 8)) & PFC_MASK; - if (reg64 =3D=3D PFC_FUNC_INTERRUPT) + if (rzt2h_pin_read_pfc(pctrl, port, bit) =3D=3D PFC_FUNC_INTERRUPT) return GPIO_LINE_DIRECTION_IN; =20 return -EINVAL; } =20 - reg =3D rzt2h_pinctrl_readw(pctrl, port, PM(port)); - reg =3D (reg >> (bit * 2)) & PM_MASK; - if (reg & PM_OUTPUT) + pm =3D rzt2h_pin_read_pm(pctrl, port, bit); + if (pm & PM_OUTPUT) return GPIO_LINE_DIRECTION_OUT; - if (reg & PM_INPUT) + if (pm & PM_INPUT) return GPIO_LINE_DIRECTION_IN; =20 return -EINVAL; @@ -861,7 +849,7 @@ static int rzt2h_gpio_get(struct gpio_chip *chip, unsig= ned int offset) struct rzt2h_pinctrl *pctrl =3D gpiochip_get_data(chip); u8 port =3D RZT2H_PIN_ID_TO_PORT(offset); u8 bit =3D RZT2H_PIN_ID_TO_PIN(offset); - u16 reg; + u8 pm; =20 if (rzt2h_pin_mode_is_peripheral(pctrl, port, bit)) { if (rzt2h_pin_read_pfc(pctrl, port, bit) =3D=3D PFC_FUNC_INTERRUPT) @@ -870,11 +858,10 @@ static int rzt2h_gpio_get(struct gpio_chip *chip, uns= igned int offset) return -EINVAL; } =20 - reg =3D rzt2h_pinctrl_readw(pctrl, port, PM(port)); - reg =3D (reg >> (bit * 2)) & PM_MASK; - if (reg & PM_INPUT) - return !!(rzt2h_pinctrl_readb(pctrl, port, PIN(port)) & BIT(bit)); - if (reg & PM_OUTPUT) + pm =3D rzt2h_pin_read_pm(pctrl, port, bit); + if (pm & PM_INPUT) + return rzt2h_pin_read_input(pctrl, port, bit); + if (pm & PM_OUTPUT) return !!(rzt2h_pinctrl_readb(pctrl, port, P(port)) & BIT(bit)); =20 return -EINVAL; --=20 2.55.0