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Sun, 16 Aug 2026 14:56:04 -0700 (PDT) From: Bhargav Joshi Date: Mon, 17 Aug 2026 03:25:25 +0530 Subject: [PATCH v3 1/2] ARM: dts: ti: keystone-k2l: Rename ti,davinci-spi-num-cs to num-cs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260817-ti-davinci-spi-v3-1-23844cfb5e6a@gmail.com> References: <20260817-ti-davinci-spi-v3-0-23844cfb5e6a@gmail.com> In-Reply-To: <20260817-ti-davinci-spi-v3-0-23844cfb5e6a@gmail.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Nishanth Menon , Santosh Shilimkar Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, goledhruva@gmail.com, m-chawdhry@ti.com, daniel.baluta@gmail.com, simona.toaca@nxp.com, j.bhargav.u@gmail.com X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786917340; l=1081; i=j.bhargav.u@gmail.com; h=from:subject:message-id; bh=YnPAhvKumj4atfxnTtYZIxnxE4cgoSSko47sbyyrNKo=; b=Dgl2753Re5cUEaNKLNQeCEOIJ4woQyHiL5DlRhR78W0nm1I83BcVXEpjbecipodC4myjHLxZQ 1eYV5BuJPKrD6y9slJXTnlyaKg0etdOl/bHLONKGwVlTAfZ1Cq8u5Rn X-Developer-Key: i=j.bhargav.u@gmail.com; a=ed25519; pk=IqNDwUZKECEA+n8wXctFLBbYL9NhFstZNbOznm/nX1k= Property ti,davinci-spi-num-cs is present in the SPI nodes of keystone-k2l.dtsi, but it has never been documented in the bindings or matched by driver. Driver relies on standard num-cs property instead. Use standard property num-cs instad of davinci-spi-num-cs. Signed-off-by: Bhargav Joshi --- arch/arm/boot/dts/ti/keystone/keystone-k2l.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/ti/keystone/keystone-k2l.dtsi b/arch/arm/boo= t/dts/ti/keystone/keystone-k2l.dtsi index 330b437b667f..39a846d7f8a4 100644 --- a/arch/arm/boot/dts/ti/keystone/keystone-k2l.dtsi +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2l.dtsi @@ -401,15 +401,15 @@ mdio: mdio@26200f00 { }; =20 &spi0 { - ti,davinci-spi-num-cs =3D <5>; + num-cs =3D <5>; }; =20 &spi1 { - ti,davinci-spi-num-cs =3D <3>; + num-cs =3D <3>; }; =20 &spi2 { - ti,davinci-spi-num-cs =3D <5>; + num-cs =3D <5>; /* Pin muxed. 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Sun, 16 Aug 2026 14:56:16 -0700 (PDT) From: Bhargav Joshi Date: Mon, 17 Aug 2026 03:25:26 +0530 Subject: [PATCH v3 2/2] dt-bindings: spi: ti,davinci-spi: convert to DT schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260817-ti-davinci-spi-v3-2-23844cfb5e6a@gmail.com> References: <20260817-ti-davinci-spi-v3-0-23844cfb5e6a@gmail.com> In-Reply-To: <20260817-ti-davinci-spi-v3-0-23844cfb5e6a@gmail.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Nishanth Menon , Santosh Shilimkar Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, goledhruva@gmail.com, m-chawdhry@ti.com, daniel.baluta@gmail.com, simona.toaca@nxp.com, j.bhargav.u@gmail.com X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786917340; l=9742; i=j.bhargav.u@gmail.com; h=from:subject:message-id; bh=/zVpg1CccNxq2uZbj+73+VsP1dk+Mxi9XXjr+VzDYGI=; b=ZliuSqiZHLfwNTHgXM1xP7wJBe0D+XLjexZuqtkvFbJgWUR8nOfdQl5N/B//QqumPoZbyENqv Svaujf+lZgYC9AKThC3jLG1nMm1efu9I/AT9OPu8NjvmMbhrgilNANN X-Developer-Key: i=j.bhargav.u@gmail.com; a=ed25519; pk=IqNDwUZKECEA+n8wXctFLBbYL9NhFstZNbOznm/nX1k= Convert the TI DaVinci/Keystone SPI controller binding from text format to DT schema. Changes during the conversion: - Create a separate ti,davinci-spi-peripheral-props.yaml schema to properly define the ti,spi-wdelay peripheral property. - Add missing dmas and dma-names properties. - Add constraints to ti,spi-wdelay based on the 6-bit width of the SPIFMTn.WDELAY hardware register field. Signed-off-by: Bhargav Joshi Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/spi/spi-davinci.txt | 100 ----------------- .../bindings/spi/spi-peripheral-props.yaml | 1 + .../spi/ti,davinci-spi-peripheral-props.yaml | 25 +++++ .../devicetree/bindings/spi/ti,davinci-spi.yaml | 124 +++++++++++++++++= ++++ 4 files changed, 150 insertions(+), 100 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/spi-davinci.txt b/Docume= ntation/devicetree/bindings/spi/spi-davinci.txt deleted file mode 100644 index f012888656ec..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-davinci.txt +++ /dev/null @@ -1,100 +0,0 @@ -Davinci SPI controller device bindings - -Links on DM: -Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf -dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf -OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf - -Required properties: -- #address-cells: number of cells required to define a chip select - address on the SPI bus. Should be set to 1. -- #size-cells: should be zero. -- compatible: - - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family - - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family - - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC - family -- reg: Offset and length of SPI controller register space -- num-cs: Number of chip selects. This includes internal as well as - GPIO chip selects. -- ti,davinci-spi-intr-line: interrupt line used to connect the SPI - IP to the interrupt controller within the SoC. Possible values - are 0 and 1. Manual says one of the two possible interrupt - lines can be tied to the interrupt controller. Set this - based on a specific SoC configuration. -- interrupts: interrupt number mapped to CPU. -- clocks: spi clk phandle - For 66AK2G this property should be set per binding, - Documentation/devicetree/bindings/clock/ti,sci-clk.yaml - -SoC-specific Required Properties: - -The following are mandatory properties for Keystone 2 66AK2G SoCs only: - -- power-domains: Should contain a phandle to a PM domain provider node - and an args specifier containing the SPI device id - value. This property is as per the binding, - -Optional: -- cs-gpios: gpio chip selects - For example to have 3 internal CS and 2 GPIO CS, user could define - cs-gpios =3D <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>; - where first three are internal CS and last two are GPIO CS. - -Optional properties for slave devices: -SPI slave nodes can contain the following properties. -Not all SPI Peripherals from Texas Instruments support this. -Please check SPI peripheral documentation for a device before using these. - -- ti,spi-wdelay : delay between transmission of words - (SPIFMTn.WDELAY, SPIDAT1.WDEL) must be specified in number of SPI module - clock periods. - - delay =3D WDELAY * SPI_module_clock_period + 2 * SPI_module_clock_period - -Below is timing diagram which shows functional meaning of -"ti,spi-wdelay" parameter. - - +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ -SPI_CLK | | | | | | | | | | | | | | | | - +----------+ +-+ +-+ +-+ +-+ +---------------------------+ +-+ +-+ +- - -SPI_SOMI/SIMO+-----------------+ +----------- - +----------+ word1 +---------------------------+word2 - +-----------------+ +----------- - WDELAY - <--------------------------> - -Example of a NOR flash slave device (n25q032) connected to DaVinci -SPI controller device over the SPI bus. - -spi0:spi@20bf0000 { - #address-cells =3D <1>; - #size-cells =3D <0>; - compatible =3D "ti,dm6446-spi"; - reg =3D <0x20BF0000 0x1000>; - num-cs =3D <4>; - ti,davinci-spi-intr-line =3D <0>; - interrupts =3D <338>; - clocks =3D <&clkspi>; - - flash: flash@0 { - #address-cells =3D <1>; - #size-cells =3D <1>; - compatible =3D "st,m25p32"; - spi-max-frequency =3D <25000000>; - reg =3D <0>; - ti,spi-wdelay =3D <8>; - - partition@0 { - label =3D "u-boot-spl"; - reg =3D <0x0 0x80000>; - read-only; - }; - - partition@1 { - label =3D "test"; - reg =3D <0x80000 0x380000>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yam= l b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 880a9f624566..cb5d608998e1 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -155,5 +155,6 @@ allOf: - $ref: fsl,dspi-peripheral-props.yaml# - $ref: samsung,spi-peripheral-props.yaml# - $ref: nvidia,tegra210-quad-peripheral-props.yaml# + - $ref: ti,davinci-spi-peripheral-props.yaml# =20 additionalProperties: true diff --git a/Documentation/devicetree/bindings/spi/ti,davinci-spi-periphera= l-props.yaml b/Documentation/devicetree/bindings/spi/ti,davinci-spi-periphe= ral-props.yaml new file mode 100644 index 000000000000..1060f176c6cb --- /dev/null +++ b/Documentation/devicetree/bindings/spi/ti,davinci-spi-peripheral-props= .yaml @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/ti,davinci-spi-peripheral-props.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI DaVinci/Keystone SPI Peripheral Properties + +maintainers: + - Bartosz Golaszewski + +description: + Peripheral-specific properties for SPI devices attached to a TI + DaVinci/Keystone SPI controller. + +properties: + ti,spi-wdelay: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 63 + description: + delay between transmission of words (SPIFMTn.WDELAY, SPIDAT1.WDEL) + must be specified in number of SPI module clock periods. + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/spi/ti,davinci-spi.yaml b/Do= cumentation/devicetree/bindings/spi/ti,davinci-spi.yaml new file mode 100644 index 000000000000..5bf74f3ca588 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/ti,davinci-spi.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/ti,davinci-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI DaVinci/Keystone SPI Controller + +maintainers: + - Bartosz Golaszewski + +properties: + compatible: + oneOf: + - enum: + - ti,da830-spi + - ti,keystone-spi + - ti,dm6441-spi + - items: + - const: ti,keystone-spi + - const: ti,dm6441-spi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + description: + Should contain a phandle to a PM domain provider node + and an args specifier containing the SPI device id + value. + + num-cs: + minimum: 1 + default: 1 + description: + Number of chip selects supported by the controller. This + includes both internal and GPIO chip selects. + + ti,davinci-spi-intr-line: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + Interrupt line used to connect the SPI IP to the interrupt + controller within the SoC. The SPI peripheral can route its + interrupt output to one of two lines (INT0 or INT1). Set + this based on the SoC-specific wiring to the interrupt + controller. + + dmas: + items: + - description: RX DMA channel + - description: TX DMA channel + + dma-names: + items: + - const: rx + - const: tx + + "#address-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - ti,davinci-spi-intr-line + - num-cs + - "#address-cells" + - "#size-cells" + +allOf: + - $ref: spi-controller.yaml# + - if: + properties: + compatible: + const: ti,keystone-spi + then: + required: + - power-domains + +unevaluatedProperties: false + +examples: + - | + spi@20bf0000 { + compatible =3D "ti,keystone-spi","ti,dm6441-spi"; + reg =3D <0x20bf0000 0x1000>; + num-cs =3D <4>; + ti,davinci-spi-intr-line =3D <0>; + interrupts =3D <338>; + clocks =3D <&clkspi>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + flash@0 { + compatible =3D "jedec,spi-nor"; + spi-max-frequency =3D <25000000>; + reg =3D <0>; + ti,spi-wdelay =3D <8>; + }; + }; + + - | + spi@41000 { + compatible =3D "ti,da830-spi"; + reg =3D <0x41000 0x1000>; + num-cs =3D <6>; + ti,davinci-spi-intr-line =3D <1>; + interrupts =3D <20>; + dmas =3D <&edma0 14 0>, <&edma0 15 0>; + dma-names =3D "rx", "tx"; + clocks =3D <&psc0 4>; + power-domains =3D <&psc0 4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; --=20 2.55.0