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Signed-off-by: Kim Seer Paller --- Documentation/ABI/testing/sysfs-bus-iio | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/te= sting/sysfs-bus-iio index a4f5595722ad..a0f9aada5c62 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio +++ b/Documentation/ABI/testing/sysfs-bus-iio @@ -762,6 +762,8 @@ What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_po= werdown_mode What: /sys/bus/iio/devices/iio:deviceX/out_voltage_powerdown_mode What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_powerdown_mode What: /sys/bus/iio/devices/iio:deviceX/out_altvoltage_powerdown_mode +What: /sys/bus/iio/devices/iio:deviceX/out_currentY_powerdown_mode +What: /sys/bus/iio/devices/iio:deviceX/out_current_powerdown_mode KernelVersion: 2.6.38 Contact: linux-iio@vger.kernel.org Description: @@ -774,6 +776,7 @@ Description: 6kohm_to_gnd: connected to ground via a 6kOhm resistor, 7.7kohm_to_gnd: connected to ground via a 7.7kOhm resistor, 10kohm_to_gnd: connected to ground via a 10kOhm resistor, + 15kohm_to_gnd: connected to ground via a 15kOhm resistor, 16kohm_to_gnd: connected to ground via a 16kOhm resistor, 20kohm_to_gnd: connected to ground via a 20kOhm resistor, 32kohm_to_gnd: connected to ground via a 32kOhm resistor, @@ -802,6 +805,8 @@ What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_po= werdown What: /sys/bus/iio/devices/iio:deviceX/out_voltage_powerdown What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_powerdown What: /sys/bus/iio/devices/iio:deviceX/out_altvoltage_powerdown +What: /sys/bus/iio/devices/iio:deviceX/out_currentY_powerdown +What: /sys/bus/iio/devices/iio:deviceX/out_current_powerdown KernelVersion: 2.6.38 Contact: linux-iio@vger.kernel.org Description: --=20 2.34.1 From nobody Mon Sep 28 21:55:12 2026 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 985053A7F45; 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Signed-off-by: Kim Seer Paller --- .../devicetree/bindings/iio/dac/adi,ad5710r.yaml | 143 +++++++++++++++++= ++++ MAINTAINERS | 1 + 2 files changed, 144 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad5710r.yaml b/D= ocumentation/devicetree/bindings/iio/dac/adi,ad5710r.yaml new file mode 100644 index 000000000000..259866ca87cf --- /dev/null +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad5710r.yaml @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/dac/adi,ad5710r.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD5710R/AD5711R 8-channel 12-/16-bit Configurable ID= AC/VDAC + +maintainers: + - Kim Seer Paller + +description: | + The AD5710R (16-bit) and AD5711R (12-bit) are 8-channel, low-power, + configurable current/voltage output digital-to-analog converters (DACs) = with + an on-chip 2.5V, 3ppm/=C2=B0C reference. Each channel can be independent= ly + configured as a voltage output (0V to VREF or 0V to 2 x VREF) or a curre= nt + output (0mA to 50mA). These devices operate from a single 2.7V to 5.5V + supply and are guaranteed monotonic by design. + + Datasheet can be found here: + https://www.analog.com/media/en/technical-documentation/data-sheets/ad57= 11r-ad5710r.pdf + +properties: + compatible: + enum: + - adi,ad5710r + - adi,ad5711r + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 20000000 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + vdd-supply: + description: Power Supply Input. + + iovdd-supply: + description: Digital Power Supply Input. + + io-channels: + description: + ADC channel used to monitor internal die temperature, output voltage= s, and + current of a selected channel via the MUXOUT pin. + maxItems: 1 + + ref-supply: + description: + Reference Input/Output. The voltage at the REF pin sets the full-sca= le + range of all channels. If not provided the internal reference is use= d and + also provided on the VREF pin. + + reset-gpios: + description: + Active low signal that is falling edge sensitive. When it is deasser= ted, + the digital core initialization is performed and all DAC registers e= xcept + the Interface Configuration A register are reset to their default va= lues. + maxItems: 1 + + ldac-gpios: + description: + LDAC pin to be used as a hardware trigger to update the DAC channels= . If + not present, the DAC channels are updated by Software LDAC. + maxItems: 1 + + adi,range-double: + description: + Configure the output range for all channels. If the property is pres= ent, + the output will range from 0V to 2 x Vref. If the property is not pr= esent, + the output will range from 0V to Vref. + type: boolean + +patternProperties: + "^channel@[0-7]$": + $ref: /schemas/iio/dac/dac.yaml# + type: object + description: + Represents the external channels which are connected to the DAC. + + properties: + reg: + description: Channel number + minimum: 0 + maximum: 7 + + adi,ch-func: + description: + Channel output type. Use CH_FUNC_VOLTAGE_OUTPUT for voltage + output or CH_FUNC_CURRENT_OUTPUT for current output. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2] + + required: + - reg + - adi,ch-func + + unevaluatedProperties: false + +required: + - compatible + - reg + - vdd-supply + - iovdd-supply + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + dac@0 { + compatible =3D "adi,ad5710r"; + reg =3D <0>; + spi-max-frequency =3D <1000000>; + vdd-supply =3D <&vdd>; + iovdd-supply =3D <&iovdd>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + channel@0 { + reg =3D <0>; + adi,ch-func =3D ; + }; + + channel@1 { + reg =3D <1>; + adi,ch-func =3D ; + }; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 3c5084fec202..bed05d0cccb7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1444,6 +1444,7 @@ L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/dac/adi,ad3530r.yaml +F: Documentation/devicetree/bindings/iio/dac/adi,ad5710r.yaml F: drivers/iio/dac/ad3530r.c =20 ANALOG DEVICES INC AD3552R DRIVER --=20 2.34.1 From nobody Mon Sep 28 21:55:12 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8AEB83B05A6; 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Drop AD3530R_REG_VAL_MASK and AD3530R_DAC_MAX_VAL, which hardcoded the 16-bit width and are now unused. Reviewed-by: Nuno S=C3=A1 Signed-off-by: Kim Seer Paller --- drivers/iio/dac/ad3530r.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/iio/dac/ad3530r.c b/drivers/iio/dac/ad3530r.c index 06b7f280f61b..97483534f8c3 100644 --- a/drivers/iio/dac/ad3530r.c +++ b/drivers/iio/dac/ad3530r.c @@ -61,14 +61,12 @@ #define AD3530R_SLD_TRIG_A BIT(7) #define AD3530R_OUTPUT_CONTROL_RANGE BIT(2) #define AD3530R_REFERENCE_CONTROL_SEL BIT(0) -#define AD3530R_REG_VAL_MASK GENMASK(15, 0) #define AD3530R_OP_MODE_CHAN_MSK(chan) (GENMASK(1, 0) << 2 * (chan)) =20 #define AD3530R_SW_RESET (BIT(7) | BIT(0)) #define AD3530R_INTERNAL_VREF_mV 2500 #define AD3530R_LDAC_PULSE_US 100 =20 -#define AD3530R_DAC_MAX_VAL GENMASK(15, 0) #define AD3530R_CH_PER_REG 4 #define AD3530R_CH_PER_BANK 8 #define AD3531R_MAX_CHANNELS 4 @@ -99,6 +97,7 @@ struct ad3530r_chip_info { unsigned int num_channels; unsigned int num_banks; unsigned int num_op_mode_regs; + unsigned int resolution; bool internal_ref_support; }; =20 @@ -310,7 +309,7 @@ static int ad3530r_dac_write(struct ad3530r_state *st, = unsigned int chan, int ret; =20 guard(mutex)(&st->lock); - st->buf =3D cpu_to_be16(val); + st->buf =3D cpu_to_be16(val << (16 - st->chip_info->resolution)); =20 ret =3D regmap_bulk_write(st->regmap, st->chip_info->input_ch_reg(chan), &st->buf, sizeof(st->buf)); @@ -340,12 +339,12 @@ static int ad3530r_read_raw(struct iio_dev *indio_dev, if (ret) return ret; =20 - *val =3D FIELD_GET(AD3530R_REG_VAL_MASK, be16_to_cpu(st->buf)); + *val =3D be16_to_cpu(st->buf) >> (16 - st->chip_info->resolution); =20 return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: *val =3D st->vref_mV; - *val2 =3D 16; + *val2 =3D st->chip_info->resolution; =20 return IIO_VAL_FRACTIONAL_LOG2; default: @@ -361,7 +360,7 @@ static int ad3530r_write_raw(struct iio_dev *indio_dev, =20 switch (info) { case IIO_CHAN_INFO_RAW: - if (val < 0 || val > AD3530R_DAC_MAX_VAL) + if (val < 0 || val > (1 << st->chip_info->resolution) - 1) return -EINVAL; =20 return ad3530r_dac_write(st, chan->channel, val); @@ -525,6 +524,7 @@ static const struct regmap_config ad3532r_regmap_config= =3D { =20 static const struct ad3530r_chip_info ad3530_chip =3D { .name =3D "ad3530", + .resolution =3D 16, .channels =3D ad3530r_channels, .regmap_config =3D &ad3530r_regmap_config, .num_channels =3D ARRAY_SIZE(ad3530r_channels), @@ -541,6 +541,7 @@ static const struct ad3530r_chip_info ad3530_chip =3D { =20 static const struct ad3530r_chip_info ad3530r_chip =3D { .name =3D "ad3530r", + .resolution =3D 16, .channels =3D ad3530r_channels, .regmap_config =3D &ad3530r_regmap_config, .num_channels =3D ARRAY_SIZE(ad3530r_channels), @@ -557,6 +558,7 @@ static const struct ad3530r_chip_info ad3530r_chip =3D { =20 static const struct ad3530r_chip_info ad3531_chip =3D { .name =3D "ad3531", + .resolution =3D 16, .channels =3D ad3531r_channels, .regmap_config =3D &ad3530r_regmap_config, .num_channels =3D ARRAY_SIZE(ad3531r_channels), @@ -573,6 +575,7 @@ static const struct ad3530r_chip_info ad3531_chip =3D { =20 static const struct ad3530r_chip_info ad3531r_chip =3D { .name =3D "ad3531r", + .resolution =3D 16, .channels =3D ad3531r_channels, .regmap_config =3D &ad3530r_regmap_config, .num_channels =3D ARRAY_SIZE(ad3531r_channels), @@ -589,6 +592,7 @@ static const struct ad3530r_chip_info ad3531r_chip =3D { =20 static const struct ad3530r_chip_info ad3532_chip =3D { .name =3D "ad3532", + .resolution =3D 16, .channels =3D ad3532r_channels, .regmap_config =3D &ad3532r_regmap_config, .num_channels =3D ARRAY_SIZE(ad3532r_channels), @@ -605,6 +609,7 @@ static const struct ad3530r_chip_info ad3532_chip =3D { =20 static const struct ad3530r_chip_info ad3532r_chip =3D { .name =3D "ad3532r", + .resolution =3D 16, .channels =3D ad3532r_channels, .regmap_config =3D &ad3532r_regmap_config, .num_channels =3D ARRAY_SIZE(ad3532r_channels), --=20 2.34.1 From nobody Mon Sep 28 21:55:12 2026 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB9C83B0583; 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Mon, 17 Aug 2026 02:37:56 -0400 From: Kim Seer Paller Date: Mon, 17 Aug 2026 14:37:14 +0800 Subject: [PATCH v3 4/4] iio: dac: ad3530r: add support for AD5710R/AD5711R Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260817-iio-ad5710r-upstream-v3-4-3a4bf7b9c78b@analog.com> References: <20260817-iio-ad5710r-upstream-v3-0-3a4bf7b9c78b@analog.com> In-Reply-To: <20260817-iio-ad5710r-upstream-v3-0-3a4bf7b9c78b@analog.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , "Andy Shevchenko" , Michael Hennerich , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Philipp Zabel" CC: , , , , Kim Seer Paller X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786948652; l=16793; i=kimseer.paller@analog.com; s=20250213; h=from:subject:message-id; bh=ujzeLjb7IQDx2MZIk3+Iyf8soPG/xscQHa6VJj5xQbk=; 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They share the AD3530R register map and access model, so fold them into this driver. Each channel is configured as voltage or current output from its DT channel@N node via adi,ch-func, building the iio_chan_spec dynamically. Voltage channels enable VMODE_EN and report the reference-derived scale, current channels report the 50 mA internal Iref scale. The powerdown mode is read-only and derived from the channel's configured type. Signed-off-by: Kim Seer Paller --- drivers/iio/dac/Kconfig | 1 + drivers/iio/dac/ad3530r.c | 285 ++++++++++++++++++++++++++++++++++++++++++= +--- 2 files changed, 270 insertions(+), 16 deletions(-) diff --git a/drivers/iio/dac/Kconfig b/drivers/iio/dac/Kconfig index 04c90d98f86f..83a35d35c199 100644 --- a/drivers/iio/dac/Kconfig +++ b/drivers/iio/dac/Kconfig @@ -16,6 +16,7 @@ config AD3530R - AD3530/AD3530R (8-channel) - AD3531/AD3531R (4-channel) - AD3532/AD3532R (16-channel) + - AD5710R/AD5711R (8-channel configurable IDAC/VDAC) =20 To compile this driver as a module, choose M here: the module will be called ad3530r. diff --git a/drivers/iio/dac/ad3530r.c b/drivers/iio/dac/ad3530r.c index 97483534f8c3..aebe4f11771b 100644 --- a/drivers/iio/dac/ad3530r.c +++ b/drivers/iio/dac/ad3530r.c @@ -3,6 +3,8 @@ * AD3530R/AD3530 8-channel, 16-bit Voltage Output DAC Driver * AD3531R/AD3531 4-channel, 16-bit Voltage Output DAC Driver * AD3532R/AD3532 16-channel, 16-bit Voltage Output DAC Driver + * AD5710R 8-channel, 16-bit Configurable IDAC/VDAC Driver + * AD5711R 8-channel, 12-bit Configurable IDAC/VDAC Driver * * Copyright 2025 Analog Devices Inc. */ @@ -27,6 +29,8 @@ #include #include =20 +#include + #define AD3530R_INTERFACE_CONFIG_A 0x00 #define AD3530R_OUTPUT_OPERATING_MODE_0 0x20 #define AD3530R_OUTPUT_OPERATING_MODE_1 0x21 @@ -39,6 +43,8 @@ #define AD3531R_SW_LDAC_TRIG_A 0xDD #define AD3531R_INPUT_CH 0xE3 =20 +#define AD5710R_CHN_VMODE_EN 0xFF + /* AD3532R/AD3532 bank 0 registers (channels 0-7) */ #define AD3532R_INTERFACE_CONFIG_A_0 0x1000 #define AD3532R_OUTPUT_OPERATING_MODE_0 0x1020 @@ -62,9 +68,11 @@ #define AD3530R_OUTPUT_CONTROL_RANGE BIT(2) #define AD3530R_REFERENCE_CONTROL_SEL BIT(0) #define AD3530R_OP_MODE_CHAN_MSK(chan) (GENMASK(1, 0) << 2 * (chan)) +#define AD5710R_CHN_VMODE_EN_BIT(chan) BIT(chan) =20 #define AD3530R_SW_RESET (BIT(7) | BIT(0)) #define AD3530R_INTERNAL_VREF_mV 2500 +#define AD5710R_INTERNAL_IREF_mA 50 #define AD3530R_LDAC_PULSE_US 100 =20 #define AD3530R_CH_PER_REG 4 @@ -99,6 +107,7 @@ struct ad3530r_chip_info { unsigned int num_op_mode_regs; unsigned int resolution; bool internal_ref_support; + bool channel_configurable; }; =20 struct ad3530r_state { @@ -152,6 +161,11 @@ static const char * const ad3532r_powerdown_modes[] = =3D { "three_state", }; =20 +static const char * const ad5710r_powerdown_modes[] =3D { + "15kohm_to_gnd", + "three_state", +}; + static int ad3530r_get_powerdown_mode(struct iio_dev *indio_dev, const struct iio_chan_spec *chan) { @@ -194,6 +208,26 @@ static const struct iio_enum ad3532r_powerdown_mode_en= um =3D { .set =3D ad3530r_set_powerdown_mode, }; =20 +static int ad5710r_get_powerdown_mode(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct ad3530r_state *st =3D iio_priv(indio_dev); + int ret; + + ret =3D regmap_test_bits(st->regmap, AD5710R_CHN_VMODE_EN, + AD5710R_CHN_VMODE_EN_BIT(chan->channel)); + if (ret < 0) + return ret; + + return !ret; +} + +static const struct iio_enum ad5710r_powerdown_mode_enum =3D { + .items =3D ad5710r_powerdown_modes, + .num_items =3D ARRAY_SIZE(ad5710r_powerdown_modes), + .get =3D ad5710r_get_powerdown_mode, +}; + static ssize_t ad3530r_get_dac_powerdown(struct iio_dev *indio_dev, uintptr_t private, const struct iio_chan_spec *chan, @@ -277,6 +311,61 @@ static ssize_t ad3532r_set_dac_powerdown(struct iio_de= v *indio_dev, return len; } =20 +static void ad5710r_get_op_mode_reg(unsigned int channel, unsigned int *re= g, + unsigned int *mask) +{ + unsigned int local_ch, reg_in_bank, ch_in_reg; + + local_ch =3D channel % AD3530R_CH_PER_BANK; + reg_in_bank =3D local_ch / AD3530R_CH_PER_REG; + ch_in_reg =3D local_ch % AD3530R_CH_PER_REG; + + *reg =3D AD3530R_OUTPUT_OPERATING_MODE_0 + reg_in_bank; + *mask =3D AD3530R_OP_MODE_CHAN_MSK(ch_in_reg); +} + +static ssize_t ad5710r_get_dac_powerdown(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) +{ + struct ad3530r_state *st =3D iio_priv(indio_dev); + unsigned int reg, mask; + int ret; + + ad5710r_get_op_mode_reg(chan->channel, ®, &mask); + + ret =3D regmap_test_bits(st->regmap, reg, field_prep(mask, 1)); + if (ret < 0) + return ret; + + return sysfs_emit(buf, "%d\n", ret); +} + +static ssize_t ad5710r_set_dac_powerdown(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct ad3530r_state *st =3D iio_priv(indio_dev); + unsigned int reg, mask; + bool powerdown; + int ret; + + ret =3D kstrtobool(buf, &powerdown); + if (ret) + return ret; + + ad5710r_get_op_mode_reg(chan->channel, ®, &mask); + + ret =3D regmap_update_bits(st->regmap, reg, mask, + field_prep(mask, powerdown)); + if (ret) + return ret; + + return len; +} + static int ad3530r_trigger_sw_ldac_reg(unsigned int channel) { return AD3530R_SW_LDAC_TRIG_A; @@ -343,7 +432,10 @@ static int ad3530r_read_raw(struct iio_dev *indio_dev, =20 return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: - *val =3D st->vref_mV; + if (chan->type =3D=3D IIO_CURRENT) + *val =3D AD5710R_INTERNAL_IREF_mA; + else + *val =3D st->vref_mV; *val2 =3D st->chip_info->resolution; =20 return IIO_VAL_FRACTIONAL_LOG2; @@ -419,6 +511,17 @@ static const struct iio_chan_spec_ext_info ad3532r_ext= _info[] =3D { { } }; =20 +static const struct iio_chan_spec_ext_info ad5710r_ext_info[] =3D { + { + .name =3D "powerdown", + .shared =3D IIO_SEPARATE, + .read =3D ad5710r_get_dac_powerdown, + .write =3D ad5710r_set_dac_powerdown, + }, + IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad5710r_powerdown_mode_enum), + { } +}; + #define AD3530R_CHAN(_chan, _ext_info) \ { \ .type =3D IIO_VOLTAGE, \ @@ -467,6 +570,17 @@ static const struct iio_chan_spec ad3532r_channels[] = =3D { AD3530R_CHAN(15, ad3532r_ext_info), }; =20 +static const struct iio_chan_spec ad5710r_channels[] =3D { + AD3530R_CHAN(0, ad5710r_ext_info), + AD3530R_CHAN(1, ad5710r_ext_info), + AD3530R_CHAN(2, ad5710r_ext_info), + AD3530R_CHAN(3, ad5710r_ext_info), + AD3530R_CHAN(4, ad5710r_ext_info), + AD3530R_CHAN(5, ad5710r_ext_info), + AD3530R_CHAN(6, ad5710r_ext_info), + AD3530R_CHAN(7, ad5710r_ext_info), +}; + static const unsigned int ad3530r_if_config[] =3D { AD3530R_INTERFACE_CONFIG_A, }; @@ -522,6 +636,12 @@ static const struct regmap_config ad3532r_regmap_confi= g =3D { .max_register =3D AD3532R_MAX_REG_ADDR, }; =20 +static const struct regmap_config ad5710r_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 8, + .max_register =3D AD5710R_CHN_VMODE_EN, +}; + static const struct ad3530r_chip_info ad3530_chip =3D { .name =3D "ad3530", .resolution =3D 16, @@ -537,6 +657,7 @@ static const struct ad3530r_chip_info ad3530_chip =3D { .num_banks =3D ARRAY_SIZE(ad3530r_if_config), .num_op_mode_regs =3D ARRAY_SIZE(ad3530r_op_mode), .internal_ref_support =3D false, + .channel_configurable =3D false, }; =20 static const struct ad3530r_chip_info ad3530r_chip =3D { @@ -554,6 +675,7 @@ static const struct ad3530r_chip_info ad3530r_chip =3D { .num_banks =3D ARRAY_SIZE(ad3530r_if_config), .num_op_mode_regs =3D ARRAY_SIZE(ad3530r_op_mode), .internal_ref_support =3D true, + .channel_configurable =3D false, }; =20 static const struct ad3530r_chip_info ad3531_chip =3D { @@ -571,6 +693,7 @@ static const struct ad3530r_chip_info ad3531_chip =3D { .num_banks =3D ARRAY_SIZE(ad3530r_if_config), .num_op_mode_regs =3D ARRAY_SIZE(ad3531r_op_mode), .internal_ref_support =3D false, + .channel_configurable =3D false, }; =20 static const struct ad3530r_chip_info ad3531r_chip =3D { @@ -588,6 +711,7 @@ static const struct ad3530r_chip_info ad3531r_chip =3D { .num_banks =3D ARRAY_SIZE(ad3530r_if_config), .num_op_mode_regs =3D ARRAY_SIZE(ad3531r_op_mode), .internal_ref_support =3D true, + .channel_configurable =3D false, }; =20 static const struct ad3530r_chip_info ad3532_chip =3D { @@ -605,6 +729,7 @@ static const struct ad3530r_chip_info ad3532_chip =3D { .num_banks =3D ARRAY_SIZE(ad3532r_if_config), .num_op_mode_regs =3D ARRAY_SIZE(ad3532r_op_mode), .internal_ref_support =3D false, + .channel_configurable =3D false, }; =20 static const struct ad3530r_chip_info ad3532r_chip =3D { @@ -622,8 +747,123 @@ static const struct ad3530r_chip_info ad3532r_chip = =3D { .num_banks =3D ARRAY_SIZE(ad3532r_if_config), .num_op_mode_regs =3D ARRAY_SIZE(ad3532r_op_mode), .internal_ref_support =3D true, + .channel_configurable =3D false, +}; + +static const struct ad3530r_chip_info ad5710r_chip =3D { + .name =3D "ad5710r", + .resolution =3D 16, + .regmap_config =3D &ad5710r_regmap_config, + .num_channels =3D ARRAY_SIZE(ad5710r_channels), + .sw_ldac_trig_reg =3D ad3530r_trigger_sw_ldac_reg, + .input_ch_reg =3D ad3530r_input_ch_reg, + .interface_config_a =3D ad3530r_if_config, + .output_control =3D ad3530r_out_ctrl, + .reference_control =3D ad3530r_ref_ctrl, + .op_mode =3D ad3530r_op_mode, + .num_banks =3D ARRAY_SIZE(ad3530r_if_config), + .num_op_mode_regs =3D ARRAY_SIZE(ad3530r_op_mode), + .internal_ref_support =3D true, + .channel_configurable =3D true, +}; + +static const struct ad3530r_chip_info ad5711r_chip =3D { + .name =3D "ad5711r", + .resolution =3D 12, + .regmap_config =3D &ad5710r_regmap_config, + .num_channels =3D ARRAY_SIZE(ad5710r_channels), + .sw_ldac_trig_reg =3D ad3530r_trigger_sw_ldac_reg, + .input_ch_reg =3D ad3530r_input_ch_reg, + .interface_config_a =3D ad3530r_if_config, + .output_control =3D ad3530r_out_ctrl, + .reference_control =3D ad3530r_ref_ctrl, + .op_mode =3D ad3530r_op_mode, + .num_banks =3D ARRAY_SIZE(ad3530r_if_config), + .num_op_mode_regs =3D ARRAY_SIZE(ad3530r_op_mode), + .internal_ref_support =3D true, + .channel_configurable =3D true, }; =20 +static int ad3530r_parse_channel_cfg(struct iio_dev *indio_dev) +{ + struct ad3530r_state *st =3D iio_priv(indio_dev); + struct device *dev =3D regmap_get_device(st->regmap); + struct iio_chan_spec *channels; + unsigned int num_chan, i; + int ret; + u32 reg; + + num_chan =3D device_get_child_node_count(dev); + if (!num_chan) + return dev_err_probe(dev, -ENODEV, "No channels configured\n"); + + channels =3D devm_kcalloc(dev, num_chan, sizeof(*channels), GFP_KERNEL); + if (!channels) + return -ENOMEM; + + i =3D 0; + device_for_each_child_node_scoped(dev, child) { + unsigned int mode_reg, mode_mask, ch_func; + enum iio_chan_type chan_type; + + ret =3D fwnode_property_read_u32(child, "reg", ®); + if (ret) + return dev_err_probe(dev, ret, + "Failed to read reg property of %pfwP\n", + child); + + if (reg >=3D st->chip_info->num_channels) + return dev_err_probe(dev, -EINVAL, + "reg out of range in %pfwP\n", + child); + + ret =3D fwnode_property_read_u32(child, "adi,ch-func", &ch_func); + if (ret) + return dev_err_probe(dev, ret, + "Missing adi,ch-func property for %pfwP\n", + child); + + switch (ch_func) { + case CH_FUNC_VOLTAGE_OUTPUT: + ret =3D regmap_set_bits(st->regmap, AD5710R_CHN_VMODE_EN, + AD5710R_CHN_VMODE_EN_BIT(reg)); + if (ret) + return dev_err_probe(dev, ret, + "Failed to set voltage output for %pfwP\n", + child); + + chan_type =3D IIO_VOLTAGE; + break; + case CH_FUNC_CURRENT_OUTPUT: + chan_type =3D IIO_CURRENT; + break; + default: + return dev_err_probe(dev, -EINVAL, + "Invalid adi,ch-func %u for %pfwP\n", + ch_func, child); + } + + channels[i] =3D ad5710r_channels[reg]; + channels[i].type =3D chan_type; + i++; + + ad5710r_get_op_mode_reg(reg, &mode_reg, &mode_mask); + + /* Enable the channel in normal operation mode */ + ret =3D regmap_update_bits(st->regmap, mode_reg, mode_mask, + field_prep(mode_mask, AD3530R_NORMAL_OP)); + if (ret) + return dev_err_probe(dev, ret, + "Failed to set normal operating mode for %pfwP\n", + child); + } + + indio_dev->channels =3D channels; + indio_dev->num_channels =3D num_chan; + + return 0; +} + static int ad3530r_set_reg_bank_bits(const struct ad3530r_state *st, const unsigned int *regs, unsigned int num_regs, @@ -656,8 +896,9 @@ static int ad3530r_write_reg_banks(const struct ad3530r= _state *st, return 0; } =20 -static int ad3530r_setup(struct ad3530r_state *st, int external_vref_uV) +static int ad3530r_setup(struct iio_dev *indio_dev, int external_vref_uV) { + struct ad3530r_state *st =3D iio_priv(indio_dev); const struct ad3530r_chip_info *chip_info =3D st->chip_info; struct device *dev =3D regmap_get_device(st->regmap); struct gpio_desc *reset_gpio; @@ -707,19 +948,29 @@ static int ad3530r_setup(struct ad3530r_state *st, in= t external_vref_uV) st->vref_mV =3D range_multiplier * AD3530R_INTERNAL_VREF_mV; } =20 - /* Set normal operating mode for all channels */ - val =3D FIELD_PREP(AD3530R_OP_MODE_CHAN_MSK(0), AD3530R_NORMAL_OP) | - FIELD_PREP(AD3530R_OP_MODE_CHAN_MSK(1), AD3530R_NORMAL_OP) | - FIELD_PREP(AD3530R_OP_MODE_CHAN_MSK(2), AD3530R_NORMAL_OP) | - FIELD_PREP(AD3530R_OP_MODE_CHAN_MSK(3), AD3530R_NORMAL_OP); + if (chip_info->channel_configurable) { + /* Channels and their operating mode are configured from DT */ + ret =3D ad3530r_parse_channel_cfg(indio_dev); + if (ret) + return ret; + } else { + /* Set normal operating mode for all channels */ + val =3D FIELD_PREP(AD3530R_OP_MODE_CHAN_MSK(0), AD3530R_NORMAL_OP) | + FIELD_PREP(AD3530R_OP_MODE_CHAN_MSK(1), AD3530R_NORMAL_OP) | + FIELD_PREP(AD3530R_OP_MODE_CHAN_MSK(2), AD3530R_NORMAL_OP) | + FIELD_PREP(AD3530R_OP_MODE_CHAN_MSK(3), AD3530R_NORMAL_OP); + + ret =3D ad3530r_write_reg_banks(st, chip_info->op_mode, + chip_info->num_op_mode_regs, val); + if (ret) + return ret; =20 - ret =3D ad3530r_write_reg_banks(st, st->chip_info->op_mode, - st->chip_info->num_op_mode_regs, val); - if (ret) - return ret; + for (unsigned int i =3D 0; i < chip_info->num_channels; i++) + st->chan[i].powerdown_mode =3D AD3530R_POWERDOWN_32K; =20 - for (unsigned int i =3D 0; i < st->chip_info->num_channels; i++) - st->chan[i].powerdown_mode =3D AD3530R_POWERDOWN_32K; + indio_dev->channels =3D chip_info->channels; + indio_dev->num_channels =3D chip_info->num_channels; + } =20 st->ldac_gpio =3D devm_gpiod_get_optional(dev, "ldac", GPIOD_OUT_LOW); if (IS_ERR(st->ldac_gpio)) @@ -777,15 +1028,13 @@ static int ad3530r_probe(struct spi_device *spi) if (!st->chip_info->internal_ref_support && external_vref_uV =3D=3D 0) return -ENODEV; =20 - ret =3D ad3530r_setup(st, external_vref_uV); + ret =3D ad3530r_setup(indio_dev, external_vref_uV); if (ret) return ret; =20 indio_dev->name =3D st->chip_info->name; indio_dev->info =3D &ad3530r_info; indio_dev->modes =3D INDIO_DIRECT_MODE; - indio_dev->channels =3D st->chip_info->channels; - indio_dev->num_channels =3D st->chip_info->num_channels; =20 return devm_iio_device_register(&spi->dev, indio_dev); } @@ -797,6 +1046,8 @@ static const struct spi_device_id ad3530r_id[] =3D { { .name =3D "ad3531r", .driver_data =3D (kernel_ulong_t)&ad3531r_chip }, { .name =3D "ad3532", .driver_data =3D (kernel_ulong_t)&ad3532_chip }, { .name =3D "ad3532r", .driver_data =3D (kernel_ulong_t)&ad3532r_chip }, + { .name =3D "ad5710r", .driver_data =3D (kernel_ulong_t)&ad5710r_chip }, + { .name =3D "ad5711r", .driver_data =3D (kernel_ulong_t)&ad5711r_chip }, { } }; MODULE_DEVICE_TABLE(spi, ad3530r_id); @@ -808,6 +1059,8 @@ static const struct of_device_id ad3530r_of_match[] = =3D { { .compatible =3D "adi,ad3531r", .data =3D &ad3531r_chip }, { .compatible =3D "adi,ad3532", .data =3D &ad3532_chip }, { .compatible =3D "adi,ad3532r", .data =3D &ad3532r_chip }, + { .compatible =3D "adi,ad5710r", .data =3D &ad5710r_chip }, + { .compatible =3D "adi,ad5711r", .data =3D &ad5711r_chip }, { } }; MODULE_DEVICE_TABLE(of, ad3530r_of_match); --=20 2.34.1