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Mon, 17 Aug 2026 10:27:37 +0000 (UTC) From: Aiden Isik via B4 Relay Date: Mon, 17 Aug 2026 11:27:30 +0100 Subject: [PATCH 1/2] arm64: dts: exynos: Add initial support for Exynos5515 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260817-for-next-lucky7-v1-1-42ffb2b71ba2@member.fsf.org> References: <20260817-for-next-lucky7-v1-0-42ffb2b71ba2@member.fsf.org> In-Reply-To: <20260817-for-next-lucky7-v1-0-42ffb2b71ba2@member.fsf.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , Alim Akhtar Cc: Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Aiden Isik X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6106; i=aidenisik@member.fsf.org; h=from:subject:message-id; bh=7HSvN4K/1Ytjbafu8H69/bmsHu5n2zlSouseQ4xC7D0=; b=owEBbQKS/ZANAwAIAUknAbLEetfrAcsmYgBqguIWVUl0RPPX9hR/1pk4/gb9C3Jeckmuz73IY jTkyt3GoIiJAjMEAAEIAB0WIQSDy8UkXGpc3JNbEaVJJwGyxHrX6wUCaoLiFgAKCRBJJwGyxHrX 68m2D/wOxLIqCkhMgZh35IMFdvET4yT8YsFYTaLNI7M55avdOWUrrJdG/hGs1EjjP7cpTA7CQkc D5BYcOABQzESbcUy2I79XUzLHm8MxX+A65FlNPx/0DI+7L7RfVcy/MlrHRViQOXlPNSsd1fxVHp 3FzO1rhiWHTpmBpbqtdX6Pb85nHPfl8IubCd4qr4QTG1QzcL5L+1AcA6KLZnrERVXL6gDLpCYLd 9fQTQ7Om5MuZSFL8TdBfPiaqi5jjt0eEqKnZhsoWFuya3SxvG0uop4NUVac4ViHMIlBf8RUbugn JtL6dja5VhrYkjbMGWRqBDxxDzokjDPfNGy7Aq0LCJAlX3KKT7w2U0NPTUGDX8H9l7wsebmLA2O +0s1cACe/Oi1eKf9J0QWGcDfc6JEHIp3D65sEraHWMZ3qZm5bVzqESvejjfRSznoylvP6bJ4sUn 1mD1TU7X3CObt9bJyuldq4itvZ3QMCVZwWHGUJZIHeTgTck6S+BhaEN62GZiViCSAQjIEteYVYQ WP0hCNtAWGowiHYLB8MerphnMhVc01PCz21SWA3bnTy5syOAGB1qMBssmyQA+VLgCHNKo4WG9IH JUn0uMuPp7Y5DZgK+2A0FgFWcDg9mCu1uPZgaiw6NkBLj8OPXjxHvYDLL2sLsJBas43G4NJgNB6 h3p0tMdIx+fQRBg== X-Developer-Key: i=aidenisik@member.fsf.org; a=openpgp; fpr=83CBC5245C6A5CDC935B11A5492701B2C47AD7EB X-Endpoint-Received: by B4 Relay for aidenisik@member.fsf.org/default with auth_id=956 X-Original-From: Aiden Isik Reply-To: aidenisik@member.fsf.org From: Aiden Isik The Exynos5515 is an ARMv8 wearable SoC, used in the following devices: - Samsung Galaxy Watch 4 (SM-R860/SM-R865/SM-R870/SM-R875) - Samsung Galaxy Watch 4 Classic (SM-R880/SM-R885/SM-R890/SM-R895) - Samsung Galaxy Watch FE (SM-R861/SM-R866) - Samsung Galaxy Watch 5 (SM-R900/SM-R905/SM-R910/SM-R915) - Samsung Galaxy Watch 5 Pro (SM-R920/SM-R925) - Samsung Galaxy Watch 6 (SM-R930/SM-R935/SM-R940/SM-R945) - Samsung Galaxy Watch 6 Classic (SM-R950/SM-R955/SM-R960/SM-R965) Add the following support for this SoC: - Both Cortex-A55 cores - ChipID - Generic timer - Watchdog timer - CMU_TOP, CMU_PERI, and CMU_FSYS clock management units The devices using this SoC suffer from the same issue as many other Samsung devices, where the stock bootloader does not configure CNTFRQ_EL0. To mitigate this, the correct frequency is hardcoded in the timer node. Signed-off-by: Aiden Isik --- arch/arm64/boot/dts/exynos/exynos5515.dtsi | 186 +++++++++++++++++++++++++= ++++ 1 file changed, 186 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5515.dtsi b/arch/arm64/boot/d= ts/exynos/exynos5515.dtsi new file mode 100644 index 000000000000..5584c1a3aaf4 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos5515.dtsi @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Samsung Exynos 5515 SoC device tree source + * + * Copyright (c) 2026 Aiden Isik + */ + +#include +#include + +/ { + compatible =3D "samsung,exynos5515"; + #address-cells =3D <2>; + interrupt-parent =3D <&gic>; + #size-cells =3D <1>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a55"; + reg =3D <0x0>; + device_type =3D "cpu"; + enable-method =3D "psci"; + }; + + cpu1: cpu@1 { + compatible =3D "arm,cortex-a55"; + reg =3D <0x100>; + device_type =3D "cpu"; + enable-method =3D "psci"; + }; + }; + + oscclk: osc-clock { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-output-names =3D "oscclk"; + }; + + pmu { + compatible =3D "arm,armv8-pmuv3"; + interrupt-affinity =3D <&cpu0>, + <&cpu1>; + interrupts =3D , + ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + cpu_off =3D <0x84000002>; + cpu_on =3D <0xc4000003>; + cpu_suspend =3D <0xc4000001>; + method =3D "smc"; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + ranges =3D <0x0 0x0 0x0 0x20000000>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + + chipid@10000000 { + compatible =3D "samsung,exynos5515-chipid", + "samsung,exynos850-chipid"; + reg =3D <0x10000000 0x100>; + }; + + sysreg_peri: syscon@10020000 { + compatible =3D "samsung,exynos5515-peri-sysreg", "syscon"; + reg =3D <0x10020000 0x10000>; + }; + + cmu_peri: clock-controller@10030000 { + compatible =3D "samsung,exynos5515-cmu-peri"; + reg =3D <0x10030000 0x10000>; + #clock-cells =3D <1>; + clocks =3D <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERI_BUS>, + <&cmu_top CLK_DOUT_CMU_PERI_IP>, + <&cmu_top CLK_DOUT_CMU_PERI_UART>; + clock-names =3D "oscclk", + "bus", + "ip", + "uart"; + samsung,sysreg =3D <&sysreg_peri>; + }; + + watchdog: watchdog@10050000 { + compatible =3D "samsung,exynos5515-wdt"; + reg =3D <0x10050000 0x100>; + clocks =3D <&cmu_peri CLK_GOUT_PERI_WDT0_PCLK>, + <&oscclk>; + clock-names =3D "watchdog", + "watchdog_src"; + interrupts =3D ; + samsung,syscon-phandle =3D <&pmu_system_controller>; + + status =3D "disabled"; + }; + + cmu_fsys: clock-controller@10400000 { + compatible =3D "samsung,exynos5515-cmu-fsys"; + reg =3D <0x10400000 0x10000>; + #clock-cells =3D <1>; + clocks =3D <&oscclk>, + <&cmu_top CLK_DOUT_CMU_FSYS_BUS>, + <&cmu_top CLK_DOUT_CMU_FSYS_MMC_CARD>, + <&cmu_top CLK_DOUT_CMU_FSYS_MMC_EMBD>, + <&cmu_top CLK_DOUT_CMU_FSYS_USB20DRD>; + clock-names =3D "oscclk", + "bus", + "mmc_card", + "mmc_embd", + "usb20drd"; + samsung,sysreg =3D <&sysreg_fsys>; + }; + + sysreg_fsys: syscon@10420000 { + compatible =3D "samsung,exynos5515-fsys-sysreg", "syscon"; + reg =3D <0x10420000 0x10000>; + }; + + pmu_system_controller: system-controller@12860000 { + compatible =3D "samsung,exynos5515-pmu", + "samsung,exynos7-pmu", + "syscon"; + reg =3D <0x12860000 0x10000>; + }; + + cmu_top: clock-controller@15410000 { + compatible =3D "samsung,exynos5515-cmu-top"; + reg =3D <0x15410000 0x10000>; + #clock-cells =3D <1>; + clocks =3D <&oscclk>; + clock-names =3D "oscclk"; + samsung,sysreg =3D <&sysreg_top>; + }; + + sysreg_top: syscon@15430000 { + compatible =3D "samsung,exynos5515-top-sysreg", "syscon"; + reg =3D <0x15430000 0x10000>; + }; + + gic: interrupt-controller@15600000 { + compatible =3D "arm,gic-400"; + reg =3D <0x15601000 0x1000>, + <0x15602000 0x1000>, + <0x15604000 0x2000>, + <0x15606000 0x2000>; + #address-cells =3D <0>; + #interrupt-cells =3D <3>; + interrupt-controller; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + /* + * Non-updatable, broken stock Samsung bootloader does not + * configure CNTFRQ_EL0 + */ + clock-frequency =3D <26000000>; + interrupts =3D , + , + , + , + ; + }; +}; + +#include "arm/samsung/exynos-syscon-restart.dtsi" --=20 2.54.0 From nobody Mon Sep 28 21:05:33 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6A703F5BFD; Mon, 17 Aug 2026 10:27:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786962457; cv=none; b=JJlRpHvjKHPPX0vx65404KRMetDiu16g3uu1M1YCj5CIOlINYpfypWnDUHZaYaQt5pkHqtanIyxrG7he04vv86lBsPUnWyaDylOkl2MNS2qhr8D0xahnJZxPcnU7CZdrwf5BQId+oseP3SDFlU9zGrQGSKbO+uQ7WpLBJAWlc3c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786962457; c=relaxed/simple; bh=aXNeoCFaEVwQtDMP5NSAWhQPbrkHKS7cNH2dCz5g/xk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Mon, 17 Aug 2026 10:27:37 +0000 (UTC) From: Aiden Isik via B4 Relay Date: Mon, 17 Aug 2026 11:27:31 +0100 Subject: [PATCH 2/2] arm64: dts: exynos: Add initial support for Samsung Galaxy Watch FE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260817-for-next-lucky7-v1-2-42ffb2b71ba2@member.fsf.org> References: <20260817-for-next-lucky7-v1-0-42ffb2b71ba2@member.fsf.org> In-Reply-To: <20260817-for-next-lucky7-v1-0-42ffb2b71ba2@member.fsf.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , Alim Akhtar Cc: Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Aiden Isik X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4016; i=aidenisik@member.fsf.org; h=from:subject:message-id; bh=JgUcx630PdrXwT+rYg8sAdnC41ZQqTbtWy02gE4KOCk=; b=owEBbQKS/ZANAwAIAUknAbLEetfrAcsmYgBqguIWkOz1uAqkN1RMWuX/bwAA7pFKR/QXpcUV1 FDoxjS8J3eJAjMEAAEIAB0WIQSDy8UkXGpc3JNbEaVJJwGyxHrX6wUCaoLiFgAKCRBJJwGyxHrX 61UDEACqb+I9SWraGW9VWgeX4597H/yzaceuVXbn/6MwjY8P5jO9hMIcPR2wem//z10LLXT5aDD 03mWmgoZlRjEvBdljtoksFDMWC1lAMME8OIXNaXU2N06TgVDbw28E+9Xe+zab0i+QF547kwQBDu aa1fCG1XW0NQ163hWuMeDFbkPRekvtPmw5Db2OOCsHli7CdP9a77KwDdhE/88I8Zfa0MsYd2SCs XF5Pa02f5yfwyLdz+inRZJ9Pd+RD6UKOT/TawSeH2vUX1iFQAWyoTUGJaOXLu3Hz+RnSkqKc9cG B8yGpdhorC6z87NuZjkObSOallsfCFjykLiJJKhCi2a/xFK5OCCdYGS7rbmKjoV13Fn2R+YP73x emCZ9HKfiwYMRzktRGZeNdlpV844SSzzETH3sIkBcfE9w5/eI+vBPenWk7DJy+InOOAn9XxAhJU 9uVUVSHFw1MiRWqwuHcqQZwFHrYSWw1f4/HZTJmq6LeZj42IpTvnRbdvdAHUOqZdwb/1FW+x43p xRzvdIOwpObRWL4tCJpU4t0Gw007loBQO9kDRL48psNCcQ3UbW0M9Jo6n2DR7sB2RGFB7iO+NC4 Q4uwmpCYddnyDi7cc60cZryodftV5RFvGUC34IkeRntELGRSSOsIYMly794sIAln11gtE4DHNhq YKbNF9lhD97y/yg== X-Developer-Key: i=aidenisik@member.fsf.org; a=openpgp; fpr=83CBC5245C6A5CDC935B11A5492701B2C47AD7EB X-Endpoint-Received: by B4 Relay for aidenisik@member.fsf.org/default with auth_id=956 X-Original-From: Aiden Isik Reply-To: aidenisik@member.fsf.org From: Aiden Isik The Samsung Galaxy Watch FE (SM-R861/SM-R866), codenamed lucky7, is a smartwatch developed by Samsung and released in 2024. It has 1.5GiB RAM, 16GiB of eMMC storage, an Exynos5515 (W920) SoC, and a 396x396 display. Support for the following is added by this device tree: - Bootloader framebuffer - Memory Only the lowest 490MiB and highest 512MiB of memory are used for now. The 488MiB between the addresses of 0x9ea00000 and 0xbe680000 is excluded from the memory node due to a bug where if the kernel even knows about the existence of this memory, one or both cores will lock up and cause an RCU stall. Signed-off-by: Aiden Isik --- arch/arm64/boot/dts/exynos/exynos5515-lucky7.dts | 106 +++++++++++++++++++= ++++ 1 file changed, 106 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5515-lucky7.dts b/arch/arm64/= boot/dts/exynos/exynos5515-lucky7.dts new file mode 100644 index 000000000000..f91ea7e44cf8 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos5515-lucky7.dts @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Samsung Galaxy Watch FE (lucky7/SM-R861/SM-R866) device tree source + * + * Copyright (c) 2026 Aiden Isik + */ + +/dts-v1/; +#include "exynos5515.dtsi" + +/ { + compatible =3D "samsung,lucky7", "samsung,exynos5515"; + chassis-type =3D "watch"; + model =3D "Samsung Galaxy Watch FE (SM-R861/SM-R866)"; + + chosen { + ranges; + #address-cells =3D <2>; + #size-cells =3D <1>; + + framebuffer@9e0cf000 { + compatible =3D "simple-framebuffer"; + reg =3D <0x0 0x9e0cf000 (396 * 396 * 4)>; + format =3D "a8r8g8b8"; + height =3D <396>; + stride =3D <(396 * 4)>; + width =3D <396>; + }; + }; + + memory@80000000 { + /* + * Use the lowest 490MiB and highest 512MiB of memory. + * The 488MiB between the addresses of 0x9ea00000 and + * 0xbe680000 is currently unused due to any memory accesses + * in several ranges between those addresses causing the core + * performing the accesses to stall. + */ + reg =3D <0x0 0x80000000 0x1ea00000>, + /* Crashing memory at 0x9ea00000-0xbe680000 */ + /* Memory hole at 0xbe680000-0xc0000000 */ + <0x0 0xc0000000 0x20000000>; + device_type =3D "memory"; + }; + + reserved-memory { + ranges; + #address-cells =3D <2>; + #size-cells =3D <1>; + + framebuffer@9e0cf000 { + reg =3D <0x0 0x9e0cf000 (396 * 396 * 4)>; + no-map; + }; + + misc-rmem { + /* + * Some of these regions belong to memory-mapped + * devices, and will be assigned to drivers as support + * is added. + * + * Other regions belong to the TrustZone firmware + * and should never be touched. + */ + reg =3D <0x0 0x87000000 0x200000>, + <0x0 0x87fff000 0x1000>, + <0x0 0x8a000000 0x31000>, + <0x0 0x8d800000 0x180000>, + <0x0 0x8ffff000 0x33000>, + <0x0 0x90100000 0x200000>, + <0x0 0x98a00000 0x600000>, + <0x0 0x9a000000 0xc00000>, + <0x0 0x9b000000 0x400000>, + <0x0 0x9bd00000 0x208000>, + <0x0 0x9c000000 0x20000>, + <0x0 0xa0000000 0x10000>, + <0x0 0xa0010000 0x400000>, + <0x0 0xa0510000 0x1000>, + <0x0 0xa0900000 0x2000>, + <0x0 0xa0902000 0x1000>, + <0x0 0xa0910000 0x3c000>, + <0x0 0xb0000000 0x200000>, + <0x0 0xb1000000 0x200000>, + <0x0 0xbbfff000 0x1000000>, + <0x0 0xbcfff000 0x1000>, + <0x0 0xbd430000 0x1250000>, + <0x0 0xd0000000 0x5d00000>, + <0x0 0xdc444000 0x2bbc000>, + <0x0 0xdf005000 0x1000>, + <0x0 0xdf008000 0x1000>, + <0x0 0xdf009000 0x12000>, + <0x0 0xdf01b000 0x21000>, + <0x0 0xdf03c000 0x1000>, + <0x0 0xdf03d000 0xfc3000>; + no-map; + }; + }; +}; + +&oscclk { + clock-frequency =3D <26000000>; +}; + +&watchdog { + status =3D "okay"; +}; --=20 2.54.0