From nobody Mon Sep 28 22:31:00 2026 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A54903D47C8; Sun, 16 Aug 2026 21:39:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.251.229.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786916354; cv=none; b=MmcenetdQJta2Bbo5DtatCXemLugXDCtGmv9nrr3JxI+mkyA9xy871xSKggikNeJsJD0yD8hqlj0g8qZCGOFmoHLitFLOfiof3gvhBP3HvZkdSSuO43vdlKCuDE3Mcl7raoQRHd/7Z5ErSdNwNb0ICZHVu4B+pWx5PS+gH+tKsM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786916354; c=relaxed/simple; bh=VNyrFLfRxk7smbrIXcGk15w2vzONaz1kQ/UFayWAlok=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=O3ZR6EtPbSIakYljBfmeL+nZ6tTXBvWuH/Cr9TqegbDhAhwY9UV3oqcIqW5VMp2eb8xTj+tYxChe6A7dR7CWXZpLczH/PUA22EDR/Lkr9ndaD/eSgxB5/udxqCIibJKEkNhhVtyxh5chpIi9YPPeG1mQM7GquiAKH427Oi51ArI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com; spf=pass smtp.mailfrom=nabladev.com; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b=Uz6Z/DGK; arc=none smtp.client-ip=178.251.229.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nabladev.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b="Uz6Z/DGK" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 31B8911C1C0; Sun, 16 Aug 2026 23:39:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1786916346; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=txBnKCBqQRTdt+Nk6gIA5IiW+sEtrE2NAj8RLoyHUgY=; b=Uz6Z/DGKUNauOOSijlWWme5Ad5ptcspXiuVTJ04N7iwc0w8BKrowKzQ5wk8wmmTfMu+7Aq IxYvZJAHgUXfP7VVvMrsrTBg4a6mTVADfFG8njJWYKw7BM4Q2eo9d9vT4TfS8/Mgd4Ue6d 48bcz3wv4b5mGetXrCBvRWm69vrV8vXB+hsokEmmzbDa/PpkVOuklzClWWSaogb4fgfBdM m81W/OdWsVrMl+zgN+oaNQ163XDy6vWc0yF/54RoyJUNgM7hayBuAeim0PzN3z+u9USIFS JFiNbt9mKZy4bawsHfW7Gsx63BwtIaEJNlzeTv5oJD3eQw1m/i/Sjzb8Hbq5/Q== From: Marek Vasut To: linux-usb@vger.kernel.org Cc: Pankaj Dev , Rahul Kumar , Fabrice Gasnier , =?UTF-8?q?Cl=C3=A9ment=20Le=20Goffic?= , Marek Vasut , Alexandre Torgue , Christian Bruel , Conor Dooley , Greg Kroah-Hartman , Krzysztof Kozlowski , Maxime Coquelin , Neil Armstrong , Rob Herring , Rosen Penev , Thinh Nguyen , Vinod Koul , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 1/9] dt-bindings: phy: Document ST STM32MP25 USB2-FEMTO PHY Date: Sun, 16 Aug 2026 23:37:03 +0200 Message-ID: <20260816213849.1044073-2-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260816213849.1044073-1-marex@nabladev.com> References: <20260816213849.1044073-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 From: Pankaj Dev Document USB2 PHY for STM32MP25 USB2 controllers, which includes the USB2.0 host-only controller and USB 2.0 part of the DWC3 controller. Two such PHYs in total are present in STM32MP25 SoC, they both are slightly different, therefore they use different compatible string to discern them. Co-developed-by: Pankaj Dev Signed-off-by: Pankaj Dev Co-developed-by: Rahul Kumar Signed-off-by: Rahul Kumar Co-developed-by: Fabrice Gasnier Signed-off-by: Fabrice Gasnier Co-developed-by: Cl=C3=A9ment Le Goffic Signed-off-by: Cl=C3=A9ment Le Goffic Signed-off-by: Marek Vasut --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Thinh Nguyen Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- V2: - Fix up Sob/Cdb lines - Fix up compatible string in example - Use additionalProperties: false - Expand description: - Use clock-cells =3D <1> to discern OSC and future PLL clock from the = PHY --- .../bindings/phy/st,stm32-usb2phy.yaml | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/st,stm32-usb2phy.= yaml diff --git a/Documentation/devicetree/bindings/phy/st,stm32-usb2phy.yaml b/= Documentation/devicetree/bindings/phy/st,stm32-usb2phy.yaml new file mode 100644 index 0000000000000..ab6c943af9a25 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/st,stm32-usb2phy.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/st,stm32-usb2phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 MPU High-Speed USB PHY + +description: + USB2 PHY block in STM32 is attached to USB 2.0 Host controller and + USB 2.0 side of DWC3 DRD controller, and provides the USB LS/FS/HS + connectivity. Both PHYs are the FEMTO-PHY, but their configuration + bits in the system control register are different for each variant. + +maintainers: + - Fabrice Gasnier + - Marek Vasut + - Pankaj Dev + +properties: + compatible: + enum: + - st,stm32mp25-usb2phy1 + - st,stm32mp25-usb2phy2 + + "#phy-cells": + const: 0 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + vdd33-supply: + description: Phandle to regulator providing 3V3 power supply to the US= B2 HS PHY + + st,syscfg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: Phandle to system configuration controller. + items: + - items: + - description: phandle to syscfg + - description: USB2PHY control offset within syscfg + + "#clock-cells": + const: 1 + +required: + - compatible + - "#clock-cells" + - "#phy-cells" + - clocks + - resets + - st,syscfg + - vdd33-supply + +additionalProperties: false + +examples: + - | + #include + #include + + usb2_phy2: usb-phy { + compatible =3D "st,stm32mp25-usb2phy1"; + #clock-cells =3D <1>; + #phy-cells =3D <0>; + clocks =3D <&rcc CK_KER_USB2PHY2>; + resets =3D <&rcc USB2PHY2_R>; + st,syscfg =3D <&syscfg 0x2800>; + vdd33-supply =3D <&vdd33usb>; + }; --=20 2.53.0 From nobody Mon Sep 28 22:31:00 2026 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D8103E3156; Sun, 16 Aug 2026 21:39:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.251.229.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786916361; cv=none; b=lPsLaP8djr0ZT3+GN2YZGz8tmnevJMaBIPPkEVUK24c9eVGbxLB6vFrOGkEbObFdlVu6nunZl7HqnTIOIqlM9CAzepOZLnZev69sgIq+nEAhGpAnmBFCwfmqivRO5v5sBzZvwsInxvEZ0A1eZjUc1BvHIyNYZsd/bRtOKBnZ6yw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786916361; c=relaxed/simple; bh=EoDghl8luuDTMDVgj5v+o9gH7KSHzoBfpQ/pgIj9fj4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=n7gQ4ps7QqTFrGbrfhIQN7PQpA3xLsJBlh4qo2iNZz8y5kNoaaLpVRGLQnh6FEHWDpFYNU1o3ouyUa5Ro4sUVuL8vQ9+y5ly+Ys5wpcsGsRK0U+xfPS7VHQmZoW1LDIls6QctnxWKnR7pLaKrY4lOKnhfnEef3cREYKcIEoeBmU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com; spf=pass smtp.mailfrom=nabladev.com; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b=AXr3kur5; arc=none smtp.client-ip=178.251.229.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nabladev.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b="AXr3kur5" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A282611C1F1; Sun, 16 Aug 2026 23:39:10 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1786916351; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=L7RuMUZyVclBumVEf7nxbqPvSqw4jn08qflZg5JH9dU=; b=AXr3kur5pQpYUR8LwrfJmsFq4KnpFbK/Fr03dAD+6PSebVHio08F/5vZENWSKWn9LG7+8I efV1emjg/YgvOlVuA5OMn7mEeGn+ngS+Q2dRYPZgV0+8n+jeYzq7O93xwMulrr4OqKUXDj KvBiWMGesCUbCzvrRjyR9aq6uiSI2e+yqJoCNvBrUQJao8j1eqbmUfrL0DSTnR+OSUMsQP Sd1Tm/0xSUSdWp5/7U/wC8c0GBlwVy6Vu5dukQ8q0kiglwHknG2LKF1Vr4U4tTGx7sCxb/ FTfvQRKNsMwsJghqxyw1rVLUud9kc9/EkogWouhSNQ+B0wkY4z2ozAG17w6ZUA== From: Marek Vasut To: linux-usb@vger.kernel.org Cc: Pankaj Dev , Rahul Kumar , Fabrice Gasnier , Christian Bruel , Marek Vasut , Alexandre Torgue , Conor Dooley , Greg Kroah-Hartman , Krzysztof Kozlowski , Maxime Coquelin , Neil Armstrong , Rob Herring , Rosen Penev , Thinh Nguyen , Vinod Koul , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 2/9] phy: stm32: Add support for ST STM32MP25 USB2-FEMTO PHY Date: Sun, 16 Aug 2026 23:37:04 +0200 Message-ID: <20260816213849.1044073-3-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260816213849.1044073-1-marex@nabladev.com> References: <20260816213849.1044073-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" From: Pankaj Dev Add USB2 PHY driver for STM32MP25 USB2 controllers, which includes the USB2.0 host-only controller and USB 2.0 part of the DWC3 controller. Two such PHYs in total are present in STM32MP25 SoC, they both are slightly different, therefore they use different compatible string to discern them. Co-developed-by: Pankaj Dev Signed-off-by: Pankaj Dev Co-developed-by: Rahul Kumar Signed-off-by: Rahul Kumar Co-developed-by: Fabrice Gasnier Signed-off-by: Fabrice Gasnier Co-developed-by: Christian Bruel Signed-off-by: Christian Bruel Signed-off-by: Marek Vasut --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Thinh Nguyen Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- V2: - Fix up Sob/Cdb lines - Operate PHY as a syscon subnode --- drivers/phy/st/Kconfig | 10 + drivers/phy/st/Makefile | 1 + drivers/phy/st/phy-stm32-usb2phy.c | 361 +++++++++++++++++++++++++++++ 3 files changed, 372 insertions(+) create mode 100644 drivers/phy/st/phy-stm32-usb2phy.c diff --git a/drivers/phy/st/Kconfig b/drivers/phy/st/Kconfig index 49206185e5633..2835bb67bca9e 100644 --- a/drivers/phy/st/Kconfig +++ b/drivers/phy/st/Kconfig @@ -58,3 +58,13 @@ config PHY_STM32_USBPHYC used by an HS USB Host controller, and the second one is shared between an HS USB OTG controller and an HS USB Host controller, selected by a USB switch. + +config PHY_STM32_USB2PHY + tristate "STMicroelectronics STM32MP25 USB2.0 PHY Controller driver" + depends on ARCH_STM32 || COMPILE_TEST + depends on COMMON_CLK + select GENERIC_PHY + help + Enable this to support the High-Speed USB 2.0 transceivers that are + part of the STMicroelectronics STM32MP25 SoCs. The PHY itself is a + Synopsys FEMTO-PHY. diff --git a/drivers/phy/st/Makefile b/drivers/phy/st/Makefile index cb80e954ea9f0..4945df5ed78a8 100644 --- a/drivers/phy/st/Makefile +++ b/drivers/phy/st/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) +=3D phy-spear1340-mip= hy.o obj-$(CONFIG_PHY_STIH407_USB) +=3D phy-stih407-usb.o obj-$(CONFIG_PHY_STM32_COMBOPHY) +=3D phy-stm32-combophy.o obj-$(CONFIG_PHY_STM32_USBPHYC) +=3D phy-stm32-usbphyc.o +obj-$(CONFIG_PHY_STM32_USB2PHY) +=3D phy-stm32-usb2phy.o diff --git a/drivers/phy/st/phy-stm32-usb2phy.c b/drivers/phy/st/phy-stm32-= usb2phy.c new file mode 100644 index 0000000000000..a5cc7b855c61f --- /dev/null +++ b/drivers/phy/st/phy-stm32-usb2phy.c @@ -0,0 +1,361 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * STMicroelectronics STM32 USB2 PHY Controller driver + * Currently Only supported for STM32MP25 + * + * Copyright (C) 2022 STMicroelectronics + * Author(s): Pankaj Dev . + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SYSCFG_USB2PHY2CR_USB2PHY2CMN BIT(2) +#define SYSCFG_USB2PHY2CR_VBUSVALID BIT(4) +#define SYSCFG_USB2PHY2CR_VBUSVLDEXTSEL BIT(5) +#define SYSCFG_USB2PHY2CR_VBUSVLDEXT BIT(6) + +struct stm32_usb2phy { + struct phy *phy; + struct regmap *regmap; + struct device *dev; + struct reset_control *rstc; + struct clk *phyref; + struct regulator *vdd33; + struct clk_hw clk48_hw; + const struct stm32mp2_usb2phy_hw_data *hw_data; + atomic_t en_refcnt; + enum phy_mode mode; + u32 cr_offset; + bool is_init; +}; + +struct stm32mp2_usb2phy_hw_data { + u32 phyrefsel_mask; + bool is_usb2_host_only; +}; + +static int stm32_usb2phy_enable(struct stm32_usb2phy *phy_dev) +{ + const struct stm32mp2_usb2phy_hw_data *phy_data =3D phy_dev->hw_data; + unsigned long rate; + int refsel, ret; + + /* Check if a phy is already init or clk48 in use */ + if (atomic_inc_return(&phy_dev->en_refcnt) > 1) + return 0; + + rate =3D clk_get_rate(phy_dev->phyref); + if (rate =3D=3D 19200000) + refsel =3D 0; + else if (rate =3D=3D 20000000) + refsel =3D 1; + else if (rate =3D=3D 24000000) + refsel =3D 2; + else + return -EINVAL; + + ret =3D regmap_update_bits(phy_dev->regmap, + phy_dev->cr_offset, + phy_data->phyrefsel_mask, + field_prep(phy_data->phyrefsel_mask, refsel)); + if (ret) + return ret; + + if (phy_data->is_usb2_host_only) { + /* + * The clock should default to active after standby, as it is + * needed when resuming OHCI to access its registers. + * CMN is default reset to 1, so enforce it is cleared, when the + * clock enable request from OHCI driver comes at resume time. + */ + ret =3D regmap_clear_bits(phy_dev->regmap, phy_dev->cr_offset, + SYSCFG_USB2PHY2CR_USB2PHY2CMN); + if (ret) + return ret; + } + + ret =3D regulator_enable(phy_dev->vdd33); + if (ret) + return ret; + + ret =3D clk_prepare_enable(phy_dev->phyref); + if (ret) + goto error_regdis; + + ret =3D reset_control_deassert(phy_dev->rstc); + if (ret) + goto error_clkdis; + + return 0; + +error_clkdis: + clk_disable_unprepare(phy_dev->phyref); +error_regdis: + regulator_disable(phy_dev->vdd33); + + return ret; +} + +static int stm32_usb2phy_disable(struct stm32_usb2phy *phy_dev) +{ + int ret; + + /* Check if a phy is still init or clk48 in use */ + if (atomic_dec_return(&phy_dev->en_refcnt) > 0) + return 0; + + ret =3D reset_control_assert(phy_dev->rstc); + if (ret) + return ret; + + clk_disable_unprepare(phy_dev->phyref); + + return regulator_disable(phy_dev->vdd33); +} + +static int stm32_usb2phy_set_mode(struct phy *phy, enum phy_mode mode, int= submode) +{ + struct stm32_usb2phy *phy_dev =3D phy_get_drvdata(phy); + const struct stm32mp2_usb2phy_hw_data *phy_data =3D phy_dev->hw_data; + u32 val, mask =3D SYSCFG_USB2PHY2CR_USB2PHY2CMN; + int ret; + + if (mode =3D=3D PHY_MODE_USB_HOST) { + val =3D 0; + if (!phy_data->is_usb2_host_only) { + mask |=3D SYSCFG_USB2PHY2CR_VBUSVLDEXT | + SYSCFG_USB2PHY2CR_VBUSVALID; + if (submode !=3D USB_ROLE_NONE) + val |=3D SYSCFG_USB2PHY2CR_VBUSVALID; + } + } else if (mode =3D=3D PHY_MODE_USB_DEVICE) { + val =3D SYSCFG_USB2PHY2CR_USB2PHY2CMN | + SYSCFG_USB2PHY2CR_VBUSVLDEXTSEL; + mask |=3D SYSCFG_USB2PHY2CR_VBUSVALID | + SYSCFG_USB2PHY2CR_VBUSVLDEXTSEL | + SYSCFG_USB2PHY2CR_VBUSVLDEXT; + if (submode !=3D USB_ROLE_NONE) + val |=3D SYSCFG_USB2PHY2CR_VBUSVLDEXT; + } else { + return -EINVAL; + } + + ret =3D regmap_update_bits(phy_dev->regmap, phy_dev->cr_offset, mask, val= ); + if (ret) + return ret; + + phy_dev->mode =3D mode; + + return 0; +} + +static int stm32_usb2phy_init(struct phy *phy) +{ + struct stm32_usb2phy *phy_dev =3D phy_get_drvdata(phy); + int ret; + + ret =3D stm32_usb2phy_enable(phy_dev); + if (ret) + return ret; + + if (phy_dev->mode !=3D PHY_MODE_INVALID) { + ret =3D stm32_usb2phy_set_mode(phy, phy_dev->mode, USB_ROLE_NONE); + if (ret) { + stm32_usb2phy_disable(phy_dev); + return ret; + } + } + + phy_dev->is_init =3D true; + + return 0; +} + +static int stm32_usb2phy_exit(struct phy *phy) +{ + struct stm32_usb2phy *phy_dev =3D phy_get_drvdata(phy); + int ret; + + ret =3D stm32_usb2phy_disable(phy_dev); + if (ret) + return ret; + + phy_dev->is_init =3D false; + + return 0; +} + +static const struct phy_ops stm32_usb2phy_data =3D { + .init =3D stm32_usb2phy_init, + .exit =3D stm32_usb2phy_exit, + .set_mode =3D stm32_usb2phy_set_mode, + .owner =3D THIS_MODULE, +}; + +static int stm32_usb2phy_clk48_prepare(struct clk_hw *hw) +{ + struct stm32_usb2phy *phy_dev =3D container_of(hw, struct stm32_usb2phy, + clk48_hw); + + return stm32_usb2phy_enable(phy_dev); +} + +static void stm32_usb2phy_clk48_unprepare(struct clk_hw *hw) +{ + struct stm32_usb2phy *phy_dev =3D container_of(hw, struct stm32_usb2phy, + clk48_hw); + + stm32_usb2phy_disable(phy_dev); +} + +static unsigned long stm32_usb2phy_clk48_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return 48000000; +} + +static const struct clk_ops stm32_usb2phy_clk48_ops =3D { + .prepare =3D stm32_usb2phy_clk48_prepare, + .unprepare =3D stm32_usb2phy_clk48_unprepare, + .recalc_rate =3D stm32_usb2phy_clk48_recalc_rate, +}; + +static int stm32_usb2phy_probe(struct platform_device *pdev) +{ + struct clk_init_data init =3D { .ops =3D &stm32_usb2phy_clk48_ops }; + struct phy_provider *phy_provider; + struct device *dev =3D &pdev->dev; + struct stm32_usb2phy *phy_dev; + const __be32 *offset; + struct phy *phy; + int ret; + + phy_dev =3D devm_kzalloc(dev, sizeof(*phy_dev), GFP_KERNEL); + if (!phy_dev) + return -ENOMEM; + + phy_dev->dev =3D dev; + dev_set_drvdata(dev, phy_dev); + + phy_dev->rstc =3D devm_reset_control_get(dev, NULL); + if (IS_ERR(phy_dev->rstc)) + return dev_err_probe(dev, PTR_ERR(phy_dev->rstc), "Failed to get USB2PHY= reset\n"); + + phy_dev->phyref =3D devm_clk_get(dev, NULL); + if (IS_ERR(phy_dev->phyref)) + return dev_err_probe(dev, PTR_ERR(phy_dev->phyref), "Failed to get phyre= f clk\n"); + + phy_dev->vdd33 =3D devm_regulator_get_optional(dev, "vdd33"); + if (IS_ERR(phy_dev->vdd33)) + return dev_err_probe(dev, PTR_ERR(phy_dev->vdd33), "Failed to get vdd3v3= supply\n"); + + phy_dev->regmap =3D syscon_node_to_regmap(dev->of_node->parent); + if (IS_ERR(phy_dev->regmap)) + return dev_err_probe(dev, PTR_ERR(phy_dev->regmap), "Failed to get regma= p\n"); + + offset =3D of_get_address(dev->of_node, 0, NULL, NULL); + if (!offset) + return dev_err_probe(dev, -EINVAL, "Failed to get regmap offset\n"); + + phy_dev->cr_offset =3D be32_to_cpu(*offset); + + phy_dev->hw_data =3D device_get_match_data(dev); + + phy =3D devm_phy_create(dev, NULL, &stm32_usb2phy_data); + if (IS_ERR(phy)) + return dev_err_probe(dev, PTR_ERR(phy), "Failed to create PHY\n"); + + phy_dev->phy =3D phy; + phy_set_drvdata(phy, phy_dev); + + phy_provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (IS_ERR(phy_provider)) + return PTR_ERR(phy_provider); + + init.name =3D devm_kasprintf(dev, GFP_KERNEL, "clk_%s_48m", + of_node_full_name(dev->of_node)); + if (!init.name) + return -ENOMEM; + + phy_dev->clk48_hw.init =3D &init; + + ret =3D devm_clk_hw_register(phy_dev->dev, &phy_dev->clk48_hw); + if (ret) + return dev_err_probe(phy_dev->dev, ret, "Failed to register 48 MHz clock= \n"); + + ret =3D devm_of_clk_add_hw_provider(phy_dev->dev, of_clk_hw_simple_get, &= phy_dev->clk48_hw); + if (ret) + return dev_err_probe(phy_dev->dev, ret, "Failed to add 48 MHz clock prov= ider\n"); + + return 0; +} + +static int stm32_usb2phy_suspend(struct device *dev) +{ + struct stm32_usb2phy *phy_dev =3D dev_get_drvdata(dev); + + if (phy_dev->is_init) + return stm32_usb2phy_disable(phy_dev); + + return 0; +} + +static int stm32_usb2phy_resume(struct device *dev) +{ + struct stm32_usb2phy *phy_dev =3D dev_get_drvdata(dev); + + if (phy_dev->is_init) + return stm32_usb2phy_enable(phy_dev); + + return 0; +} + +/* STM32MP25xx USB 2.0 PHY attached to USB 2.0 Host controller */ +static const struct stm32mp2_usb2phy_hw_data stm32mp25_usb2phy1_hwdata =3D= { + .phyrefsel_mask =3D GENMASK(6, 4), + .is_usb2_host_only =3D true, +}; + +/* STM32MP25xx USB 2.0 PHY attached to USB 2.0 part of DWC3 controller */ +static const struct stm32mp2_usb2phy_hw_data stm32mp25_usb2phy2_hwdata =3D= { + .phyrefsel_mask =3D GENMASK(14, 12), + .is_usb2_host_only =3D false, +}; + +static const struct of_device_id stm32_usb2phy_of_match[] =3D { + { .compatible =3D "st,stm32mp25-usb2phy1", .data =3D &stm32mp25_usb2phy1_= hwdata }, + { .compatible =3D "st,stm32mp25-usb2phy2", .data =3D &stm32mp25_usb2phy2_= hwdata }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, stm32_usb2phy_of_match); + +static DEFINE_SIMPLE_DEV_PM_OPS(stm32_usb2phy_pm_ops, + stm32_usb2phy_suspend, stm32_usb2phy_resume); + +static struct platform_driver stm32_usb2phy_driver =3D { + .probe =3D stm32_usb2phy_probe, + .driver =3D { + .name =3D "stm32-usb2phy", + .of_match_table =3D stm32_usb2phy_of_match, + .pm =3D pm_sleep_ptr(&stm32_usb2phy_pm_ops) + } +}; + +module_platform_driver(stm32_usb2phy_driver); + +MODULE_AUTHOR("Pankaj Dev "); +MODULE_DESCRIPTION("STMicroelectronics Generic USB2PHY driver for stm32"); +MODULE_LICENSE("GPL"); --=20 2.53.0 From nobody Mon Sep 28 22:31:00 2026 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D05D3E3152; Sun, 16 Aug 2026 21:39:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.251.229.89 ARC-Seal: i=1; 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spf=pass smtp.mailfrom=nabladev.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b="JlmMipJY" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 02E5611C1E9; Sun, 16 Aug 2026 23:39:15 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1786916357; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=jJt7Jm9dS7j9+nHkmEwZyfgLjpjrq0IoWW70XFyDFMw=; b=JlmMipJYWFu50hMoEGIywKogQMbyPOoDgARWAYc+At18F4h07+HOt3ecGckmHhuBZb33oW TBLYWAM9eLJmAQx8JMo2uH5uxEEAYnIoEt0vMphwLPh0DNQnS6kSBh4095nSlnKBLgQpqW hAT8mY/6UP64AyzAT02vPMRXJpMW1iuVndThS0BUa1mCBNmMBZUn+P8P4faSDxVO+kG0LH mZgJrLoXjxl7DHSe7F+NP2yKDtYvBojl3fAkJlCdCjmlFFDH/goc9jS5S2vlaw7IPSZxAN zu+WBC6bZ8epiClcbWA0aU3WbEO5uyJDJG03ycUp3XkK/O1dfjW3TeTF6cQX3A== From: Marek Vasut To: linux-usb@vger.kernel.org Cc: Marek Vasut , Alexandre Torgue , Christian Bruel , Conor Dooley , Fabrice Gasnier , Greg Kroah-Hartman , Krzysztof Kozlowski , Maxime Coquelin , Neil Armstrong , Pankaj Dev , Rahul Kumar , Rob Herring , Rosen Penev , Thinh Nguyen , Vinod Koul , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 3/9] dt-bindings: usb: generic-ehci: Document access-controllers property Date: Sun, 16 Aug 2026 23:37:05 +0200 Message-ID: <20260816213849.1044073-4-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260816213849.1044073-1-marex@nabladev.com> References: <20260816213849.1044073-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Document the access-controllers for EHCI USB controllers in case access checks need to be performed to use them. Signed-off-by: Marek Vasut --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Thinh Nguyen Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- V2: No change --- Documentation/devicetree/bindings/usb/generic-ehci.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Docu= mentation/devicetree/bindings/usb/generic-ehci.yaml index ae9fb70d0212c..6bca56681cdfe 100644 --- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml +++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml @@ -80,6 +80,9 @@ properties: minItems: 1 maxItems: 2 =20 + access-controllers: + maxItems: 1 + dma-coherent: true =20 interrupts: --=20 2.53.0 From nobody Mon Sep 28 22:31:00 2026 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7986724E4A1; Sun, 16 Aug 2026 21:39:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.251.229.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786916370; cv=none; b=XDeKd0JcXX89fc+v0wC5lIzCDVBmdmG5OqUe7gqta33/2YpTklkWH59gxtj73U8/hJrwWy1HTzKH1DZfUB6FYI9jmZNmqjxmX/ngNDyA1gc8QiNbban9m3wdBzxjzBaEmjxLRYqTAdC3c0gnfjrJtK3wxUlkFh0Kpu86ON2/krs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786916370; c=relaxed/simple; bh=LyLwXSC3R4k+tjS84BP1Gz3scjxMixrmDDn9YxCTmvU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qYbuS3frySlZA7FLG7H+FwyJAIt4AOd0QWgmw8ehDAhzT/rVMJTlx7XL27CKbegfKp/GjpLZ+IlRhoAQg+cS6gzR6AkUAeGqZdkmNYTHT+toXhhLB/q8gqmwrDcgrdOcTp6ySjhHw1ihbWX8LCdKfks2E5RypqdP+VIwNTj5Wl0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com; spf=pass smtp.mailfrom=nabladev.com; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b=MaAIT7Ym; arc=none smtp.client-ip=178.251.229.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nabladev.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b="MaAIT7Ym" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 6045E11C1F4; Sun, 16 Aug 2026 23:39:21 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1786916362; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=QP/6fSBavnugcpPHEyvwMnqH3KyZ0x7/oTTOBjqzH5U=; b=MaAIT7YmCM5HPtGDMig+bYXE9l4yxgmOgCCAwVlnhpoPyUhMQ/DAqJ8wx3jS46vi8QwhzI GFbLw4GqOeEkQ/v3ZBAs8FjgrBoO9GpWJmgfuzqbSzhVwtKvRu+5hOeHsphHNYghwPsZax QhjKhKryhk10KlWAuF+1b3fb9WuFtpB8lInqdB4Gmnhgz7mj2WjMcp2KkHVX4gD8NsT5Sy HWtEWNQI1w4OYOXGWNTPiVNvp+/rTE47xUzlwN+Luhevi6yH4U3KFCwLfAurz4XJyz4EDO TUoDjqJyqrutnBlZiIR3Z+wKXYBnLuAZJBypnMLPLYE5yUgZcr9AuHHTAq8gbA== From: Marek Vasut To: linux-usb@vger.kernel.org Cc: Marek Vasut , Alexandre Torgue , Christian Bruel , Conor Dooley , Fabrice Gasnier , Greg Kroah-Hartman , Krzysztof Kozlowski , Maxime Coquelin , Neil Armstrong , Pankaj Dev , Rahul Kumar , Rob Herring , Rosen Penev , Thinh Nguyen , Vinod Koul , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 4/9] dt-bindings: usb: generic-ohci: Document access-controllers property Date: Sun, 16 Aug 2026 23:37:06 +0200 Message-ID: <20260816213849.1044073-5-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260816213849.1044073-1-marex@nabladev.com> References: <20260816213849.1044073-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Document the access-controllers for OHCI USB controllers in case access checks need to be performed to use them. Signed-off-by: Marek Vasut --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Thinh Nguyen Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- V2: No change --- Documentation/devicetree/bindings/usb/generic-ohci.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Docu= mentation/devicetree/bindings/usb/generic-ohci.yaml index 322808aaa2839..8e3522a3faa76 100644 --- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml +++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml @@ -65,6 +65,9 @@ properties: reg: maxItems: 1 =20 + access-controllers: + maxItems: 1 + dma-coherent: true =20 interrupts: --=20 2.53.0 From nobody Mon Sep 28 22:31:00 2026 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 447733E2746; Sun, 16 Aug 2026 21:39:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.251.229.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786916376; cv=none; b=FCuZlgR7AqoHfGkQlYMGb5MvLGgp8/9q10x5NZe08rMwh49+Kqq+vo0dAya0tVL+Zpyae8hCazoV0na8tG5q6NDRmO+NpozawPGiriuO7zTvmO8jzrGX62BQZ+hNyGO2h7ZJDDbqG1FrW99742l6GRzHGJvuLIWJQmE8JNicdg0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786916376; c=relaxed/simple; bh=CkekS3QCZ/697uYlWc/8+H356EROo43rSMP4oscrcJs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TzfRiZHS+rgUfCh9TQAxlr6h4mdwaxiIvcQMKV7NEeUMbWPzdgh2124FRCOKmKwKPI24dF6JImk5j1xiNMHba5gf2cA9TA4oZZ9Og53GwOHX324HkTKTiyqo4DW4EeMRz1KFKt9IcsQ45/1f6KG8LN+0MDYybRtlXtJOhp21Z/w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com; spf=pass smtp.mailfrom=nabladev.com; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b=d/sBAf5C; arc=none smtp.client-ip=178.251.229.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nabladev.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b="d/sBAf5C" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id BAAE611C1F1; Sun, 16 Aug 2026 23:39:26 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1786916367; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=/WPNd7bAkhsYaqHEPW2/1kC0IadD/2WCrHtK65muLRo=; b=d/sBAf5CX3dKn8/AGUW0OPKomcIFG0upXbclzPfvKOhL9MwcLJ4bmMnD3vvsQqWnEB2gZb mXkjcLPgunI8Z66UakjDHTQdfOYKIWB3kQwecd9FrMSOsnRCh3OlCHZiOdNYOjXiZMEasn xCFnULBf9RrYdvnQrdyn3FlNhwL4RZdqoYex4SoqMXZFyxiHbgrdpkjbNF/SCSBPNkXpI/ fPUmhafFVbxJH9NB2vqcdMLBEmTKkCxLoArt1ckoUV6sOwUC+N6biUxRF7e9oKKWW29nto ewzBzr1MS8nkDxsDIfV9+dwJxtygvElcV4OZ1iWxkZhvfwLladKU28Ax8BVOCA== From: Marek Vasut To: linux-usb@vger.kernel.org Cc: Marek Vasut , Pankaj Dev , =?UTF-8?q?Cl=C3=A9ment=20Le=20Goffic?= , Gatien Chevallier , Alexandre Torgue , Christian Bruel , Conor Dooley , Fabrice Gasnier , Greg Kroah-Hartman , Krzysztof Kozlowski , Maxime Coquelin , Neil Armstrong , Rahul Kumar , Rob Herring , Rosen Penev , Thinh Nguyen , Vinod Koul , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 5/9] dt-bindings: usb: dwc3: Document ST STM32MP2 DWC3 xHCI USB controller Date: Sun, 16 Aug 2026 23:37:07 +0200 Message-ID: <20260816213849.1044073-6-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260816213849.1044073-1-marex@nabladev.com> References: <20260816213849.1044073-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 The ST STM32MP2 SoC contains single instance of DWC3 USB controller with glue logic wrapper around it controlled by syscon. Document the glue logic and DWC3 controller. Co-developed-by: Pankaj Dev Signed-off-by: Pankaj Dev Co-developed-by: Cl=C3=A9ment Le Goffic Signed-off-by: Cl=C3=A9ment Le Goffic Co-developed-by: Gatien Chevallier Signed-off-by: Gatien Chevallier Signed-off-by: Marek Vasut --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Thinh Nguyen Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- V2: Fix up Sob/Cdb lines --- .../bindings/usb/st,stm32mp25-dwc3.yaml | 108 ++++++++++++++++++ 1 file changed, 108 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/st,stm32mp25-dwc3= .yaml diff --git a/Documentation/devicetree/bindings/usb/st,stm32mp25-dwc3.yaml b= /Documentation/devicetree/bindings/usb/st,stm32mp25-dwc3.yaml new file mode 100644 index 0000000000000..e377efef43503 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/st,stm32mp25-dwc3.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/st,stm32mp25-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 MPU DWC3 USB SoC controller + +description: + The STM32 MPU DWC3 USB SoC controller block supports both + Host(SS/HS/FS/LS) and Device(SS/HS/FS) mode operation + +maintainers: + - Fabrice Gasnier + - Marek Vasut + +properties: + compatible: + const: st,stm32mp25-dwc3 + + reg: + maxItems: 1 + + access-controllers: + maxItems: 1 + + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + items: + - const: ref + - const: bus_early + - const: suspend + + dr_mode: + $ref: /schemas/types.yaml#/definitions/string + enum: [host, peripheral, otg] + + interrupts: + maxItems: 1 + + phys: + minItems: 1 + maxItems: 2 + + phy-names: + minItems: 1 + items: + - const: usb2-phy + - const: usb3-phy + + resets: + minItems: 1 + + st,syscfg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: Phandle to system configuration controller. + items: + - items: + - description: phandle to syscfg + - description: USB3DR control offset within syscfg + + st,enable-port-power-control: + type: boolean + description: Enable Host-Mode Port Power Control (bit-3 of capability = param HCCPARAMS) + + st,ovrcur-active-low: + type: boolean + description: Over-Current signal polarity is active-low + + st,vbusen-active-low: + type: boolean + description: VBUS-ENABLE signal polarity is active-low + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - phys + - phy-names + - resets + - st,syscfg + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + usb3dr: usb@48300000 { + compatible =3D "st,stm32mp25-dwc3"; + reg =3D <0x48300000 0x100000>; + clocks =3D <&rcc CK_KER_USB2PHY2>, <&rcc CK_BUS_USB3DR>, <&rcc CK_= KER_USB2PHY2>; + clock-names =3D "ref", "bus_early", "suspend"; + interrupts =3D ; + phys =3D <&usb2_phy>, <&usb3_phy>; + phy-names =3D "usb2-phy", "usb3-phy"; + resets =3D <&rcc USB3DR_R>; + st,ovrcur-active-low; + st,syscfg =3D <&syscfg 0x4800>; + st,vbusen-active-low; + }; --=20 2.53.0 From nobody Mon Sep 28 22:31:00 2026 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D87D3E3140; Sun, 16 Aug 2026 21:39:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.251.229.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786916381; cv=none; b=MsVznRgm6fxTcldm6uYUjkXNvD1WpBkQRyYqhzF5v+w7iFuCoxK+uISV/aJv/MryARGHFo1eoHACe4sWsJuarpckVI43MtI7K6pb8ATnxbdT+bWP7ZXXTx4wkA7sFUTKxkkq4iCpOqaz2oVnjDc5Nv1jLFYTULV9EKyABLWO0vk= ARC-Message-Signature: i=1; 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Sun, 16 Aug 2026 23:39:32 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1786916373; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=8hmtfOL27pdP3gIcKVEn5KQYTM4Wl55vR9a4nrxZqs0=; b=YqU+CDwL76yPkmUXDi4CsuZ+KSVMQ/GB1bZA82mG/TFqhuSI8bkWEyAz03Xm7mh62oAJJP +2d8bofpJYNABaSGNrFjuYOpmK0V90GFDTWTFZ/tEblEXDuCwZZ1JNFSz6aiax0gFXx3uK Ygee1ULP00ACKFHhuKwH04oOWdxJjuVVHXtCXN1oOape/gSJjmxTUSNlFGMbIqjDsFBU1V V1DEAFqytu8eo5hzJg+AnFDT+i+qwa7Nybxn1VSOxUavnyn+aMUSld9UJthaqvwwtfvsAH EMO37tbqrQzvzEEHoyBwMVS/74z1jimWnW575qL8jRmM3XQqHpqJxOl0uOAytw== From: Marek Vasut To: linux-usb@vger.kernel.org Cc: Marek Vasut , Alexandre Torgue , Christian Bruel , Conor Dooley , Fabrice Gasnier , Greg Kroah-Hartman , Krzysztof Kozlowski , Maxime Coquelin , Neil Armstrong , Pankaj Dev , Rahul Kumar , Rob Herring , Rosen Penev , Thinh Nguyen , Vinod Koul , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 6/9] usb: dwc3: dwc3-generic-plat: Add ST STM32MP2 DWC3 xHCI USB controller glue Date: Sun, 16 Aug 2026 23:37:08 +0200 Message-ID: <20260816213849.1044073-7-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260816213849.1044073-1-marex@nabladev.com> References: <20260816213849.1044073-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The ST STM32MP2 SoC contains one instance of DWC3 USB controller with glue logic wrapper around it controlled by syscon. Extend the generic DWC3 platform driver with ST STM32MP2 glue logic specifics. Signed-off-by: Marek Vasut --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Thinh Nguyen Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- V2: No change --- drivers/usb/dwc3/dwc3-generic-plat.c | 44 ++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-g= eneric-plat.c index ca69ac0eb07ce..0946ed61647b6 100644 --- a/drivers/usb/dwc3/dwc3-generic-plat.c +++ b/drivers/usb/dwc3/dwc3-generic-plat.c @@ -22,6 +22,12 @@ #define EIC7700_HSP_AXI_LP_XM_CSYSREQ BIT(0) #define EIC7700_HSP_AXI_LP_XS_CSYSREQ BIT(16) =20 +#define STM32MP2_USB3DRCR_HOST_PORT_POWER_CONTROL_PRESENT BIT(0) +#define STM32MP2_USB3DRCR_OVRCUR_POLARITY BIT(1) +#define STM32MP2_USB3DRCR_VBUSEN_POLARITY BIT(2) +#define STM32MP2_USB3DRCR_USB2ONLYH BIT(3) +#define STM32MP2_USB3DRCR_USB2ONLYD BIT(4) + struct dwc3_generic { struct device *dev; struct dwc3 dwc; @@ -85,6 +91,38 @@ static int dwc3_spacemit_k1_init(struct dwc3_generic *dw= c3g) return 0; } =20 +static int dwc3_stm32mp25_init(struct dwc3_generic *dwc3g) +{ + struct device *dev =3D dwc3g->dev; + bool ovrcur_polarity_low =3D device_property_read_bool(dev, "st,ovrcur-ac= tive-low"); + bool prt_pwr_ctrl =3D device_property_read_bool(dev, "st,enable-port-powe= r-control"); + bool usb2only_conf =3D device_property_match_string(dev, "phy-names", "us= b3-phy") < 0; + bool vbusen_polarity_low =3D device_property_read_bool(dev, "st,vbusen-ac= tive-low"); + struct regmap *regmap; + u32 drcr; + + regmap =3D syscon_regmap_lookup_by_phandle_args(dev->of_node, "st,syscfg"= , 1, &drcr); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "No st,syscfg phandle specifi= ed\n"); + + return regmap_update_bits(regmap, drcr, + STM32MP2_USB3DRCR_HOST_PORT_POWER_CONTROL_PRESENT | + STM32MP2_USB3DRCR_OVRCUR_POLARITY | + STM32MP2_USB3DRCR_VBUSEN_POLARITY | + STM32MP2_USB3DRCR_USB2ONLYD | + STM32MP2_USB3DRCR_USB2ONLYH, + FIELD_PREP(STM32MP2_USB3DRCR_HOST_PORT_POWER_CONTROL_PRESENT, + prt_pwr_ctrl) | + FIELD_PREP(STM32MP2_USB3DRCR_OVRCUR_POLARITY, + ovrcur_polarity_low) | + FIELD_PREP(STM32MP2_USB3DRCR_VBUSEN_POLARITY, + vbusen_polarity_low) | + FIELD_PREP(STM32MP2_USB3DRCR_USB2ONLYD, + !!usb2only_conf) | + FIELD_PREP(STM32MP2_USB3DRCR_USB2ONLYH, + !!usb2only_conf)); +} + static int dwc3_generic_probe(struct platform_device *pdev) { const struct dwc3_generic_config *plat_config; @@ -231,12 +269,18 @@ static const struct dwc3_generic_config eic7700_dwc3 = =3D { .properties =3D DWC3_DEFAULT_PROPERTIES, }; =20 +static const struct dwc3_generic_config stm32mp25_dwc3 =3D { + .init =3D dwc3_stm32mp25_init, + .properties =3D DWC3_DEFAULT_PROPERTIES, +}; + static const struct of_device_id dwc3_generic_of_match[] =3D { { .compatible =3D "spacemit,k1-dwc3", &spacemit_k1_dwc3}, { .compatible =3D "spacemit,k3-dwc3", }, { .compatible =3D "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3}, { .compatible =3D "eswin,eic7700-dwc3", &eic7700_dwc3}, { .compatible =3D "starfive,jhb100-dwc3", }, + { .compatible =3D "st,stm32mp25-dwc3", &stm32mp25_dwc3 }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, dwc3_generic_of_match); --=20 2.53.0 From nobody Mon Sep 28 22:31:00 2026 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3C0C3E3140; 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arc=none smtp.client-ip=178.251.229.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nabladev.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b="JREXHs+O" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 81DE511C1F8; Sun, 16 Aug 2026 23:39:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1786916378; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=Q9gDiM6QYxKqsu9piMSKyZoacoS5srL/I072hg/wVSw=; b=JREXHs+O5VqJVUtcQDAD8mewPHR0G15PUgucUQkeebLlgllxiG0zrNrcCsShLMdr8EsSXN sUUuORcEQFBQaMbuByzxm2ZLB4FwKjoUFO+3eEu9dw+gjueNAO+kkfEcC5KZthuOzlXahJ lMC3aW3WZPyYB9hjqoueze8VPvuX/TGcsu5RqoFxpbhoh3OkRDvKWQMunWW2lj4yN4CovT UFtv4AsTWx4zxynMTW0acRtNLcQn+cdKeEIsJH5OXDbGxafen1aKLFvnELsMpANBPBxGjg c6wnRpl4Kx0Fp7Y8QAgr69/yemFDoUwuLKNX79FNhyOh7GZQUdGcEi6/eh9mlA== From: Marek Vasut To: linux-usb@vger.kernel.org Cc: Marek Vasut , Alexandre Torgue , Christian Bruel , Conor Dooley , Fabrice Gasnier , Greg Kroah-Hartman , Krzysztof Kozlowski , Maxime Coquelin , Neil Armstrong , Pankaj Dev , Rahul Kumar , Rob Herring , Rosen Penev , Thinh Nguyen , Vinod Koul , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 7/9] dt-bindings: arm: stm32: Switch st,stm32mp23/25-syscfg into simple-mfd Date: Sun, 16 Aug 2026 23:37:09 +0200 Message-ID: <20260816213849.1044073-8-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260816213849.1044073-1-marex@nabladev.com> References: <20260816213849.1044073-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The st,stm32mp23-syscfg and st,stm32mp25-syscfg can have subnodes, which represent the USB 2.0 FEMTO-PHY. Turn the syscfg into "simple-mfd" so the PHYs would get populated by the OS. Signed-off-by: Marek Vasut --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Thinh Nguyen Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- V2: New patch --- .../devicetree/bindings/arm/stm32/st,stm32-syscon.yaml | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.ya= ml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index 95d2319afe235..ef640443dd239 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -22,11 +22,12 @@ properties: - st,stm32mp151-pwr-mcu - st,stm32mp157-syscfg - st,stm32mp21-syscfg - - st,stm32mp23-syscfg - - st,stm32mp25-syscfg - const: syscon - items: - - const: st,stm32-tamp + - enum: + - st,stm32-tamp + - st,stm32mp23-syscfg + - st,stm32mp25-syscfg - const: syscon - const: simple-mfd =20 --=20 2.53.0 From nobody Mon Sep 28 22:31:00 2026 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE3FE3E3C50; Sun, 16 Aug 2026 21:39:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.251.229.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786916391; cv=none; b=Xk1RtAu9In5EhZMUTGvxDwwJZlx9j3fS2NA/kPmq5udnF00BCQwRHuZIH52Yhbx6jMcZHNf1rHOZSO8o9Gy9RRXcYM4egnasCrRVlTzfN99q2mNAKCCEIod9brzGa22iuozL1l0DmBpLvkAKIM5r0uRpbAK4HUqrDSao3rshcwY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786916391; c=relaxed/simple; bh=ILqOtREUc2kEgd0AwRM470TJfs46VN3Ex2W8Bjq8emw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DreN/3vALQ0dlOktNLZe3dhi6nIsjxKK5NJ07bmFfUwpT6zKK0iYDwQN+WXKXijDRntNzIKANMHssIJpJ7scHqDlcRMpp79xaWHyA6LLHY2RBLrwEjH2kKBEF8SE3RtCccXAi06vr1kdYE2vbPU9rJN428A/NWnO0/6ZdmHxZg0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com; spf=pass smtp.mailfrom=nabladev.com; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b=PIKW060o; arc=none smtp.client-ip=178.251.229.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nabladev.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b="PIKW060o" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id DC79D11C1F7; Sun, 16 Aug 2026 23:39:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1786916384; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=+wPXHTSPpg7pnN5GVVm7Pp5S8X+a4mA3zNhwatSUP3s=; b=PIKW060obDZpZOMAX0SIbJ8d15pQmi/80BYG3NAbJD18G79lf90mhKG1BPk2nZ3oGw6CJ4 JlSvINU//uFYYm3LeWDF7GUu2s8NcO0RtDxYL04XGJEGGFnChwBiqVE2K26LkKhbLFKaag m6wXaypaZ9vnG5yx2Vx101lpHKQ4nCItCoQGstXU0oUquHw+gySHeYC1krsgf8VHPQbUgq TEiR3XJiorzoo3kGzw/hvllvGUZNGu3BHZHogZLkd020gBLrhPCrfv4shhTGaCgeRYU77k TSPDQZMQOGwEE9wAvgrj35sLTw/Ein2l/Q6GLH8EUH9+1n5PuxNU4o+h5+caJA== From: Marek Vasut To: linux-usb@vger.kernel.org Cc: Marek Vasut , Alexandre Torgue , Francois Choleau , Christian Bruel , Conor Dooley , Fabrice Gasnier , Greg Kroah-Hartman , Krzysztof Kozlowski , Maxime Coquelin , Neil Armstrong , Pankaj Dev , Rahul Kumar , Rob Herring , Rosen Penev , Thinh Nguyen , Vinod Koul , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 8/9] arm64: dts: st: Add USB nodes on stm32mp231 Date: Sun, 16 Aug 2026 23:37:10 +0200 Message-ID: <20260816213849.1044073-9-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260816213849.1044073-1-marex@nabladev.com> References: <20260816213849.1044073-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Add USB controller and PHY nodes to stm32mp231 DT. This includes two USB 2.0 FEMTO PHYs, USB 2.0 host controller and DWC3 DRD controller nodes. Include missing COMBOPHY for the USB 3.0 controller. Co-developed-by: Alexandre Torgue Signed-off-by: Alexandre Torgue Co-developed-by: Francois Choleau Signed-off-by: Francois Choleau Signed-off-by: Marek Vasut --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Thinh Nguyen Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- V2: - Fix up Sob/Cdb lines - Move PHY into syscfg subnode - Turn st,stm32mp23-syscfg into simple-mfd - Use clock-cells =3D <1> to discern OSC and future PLL clock from the = PHY --- arch/arm64/boot/dts/st/stm32mp231.dtsi | 81 +++++++++++++++++++++++++- 1 file changed, 80 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/s= t/stm32mp231.dtsi index 4505fc0e3b537..fd232b4241125 100644 --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include =20 / { #address-cells =3D <2>; @@ -769,6 +770,21 @@ dcmipp: dcmipp@48030000 { status =3D "disabled"; }; =20 + combophy: phy@480c0000 { + compatible =3D "st,stm32mp25-combophy"; + reg =3D <0x480c0000 0x1000>; + #phy-cells =3D <1>; + clocks =3D <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>; + clock-names =3D "apb", "ker"; + resets =3D <&rcc USB3PCIEPHY_R>; + reset-names =3D "phy"; + access-controllers =3D <&rifsc 67>; + power-domains =3D <&cluster_pd>; + wakeup-source; + interrupts-extended =3D <&exti1 45 IRQ_TYPE_EDGE_FALLING>; + status =3D "disabled"; + }; + sdmmc1: mmc@48220000 { compatible =3D "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; reg =3D <0x48220000 0x400>, <0x44230400 0x8>; @@ -862,6 +878,47 @@ stmmac_axi_config_1: stmmac-axi-config { snps,wr_osr_lmt =3D <0x7>; }; }; + + usbh_ohci: usb@482e0000 { + compatible =3D "generic-ohci"; + reg =3D <0x482e0000 0x1000>; + access-controllers =3D <&rifsc 63>; + clocks =3D <&usb2_phy1 0>, <&rcc CK_BUS_USB2OHCI>; + interrupts =3D ; + phys =3D <&usb2_phy1>; + phy-names =3D "usb"; + resets =3D <&rcc USBH_R>; + status =3D "disabled"; + }; + + usbh_ehci: usb@482f0000 { + compatible =3D "generic-ehci"; + reg =3D <0x482f0000 0x1000>; + access-controllers =3D <&rifsc 63>; + clocks =3D <&usb2_phy1 0>, <&rcc CK_BUS_USB2EHCI>; + companion =3D <&usbh_ohci>; + interrupts =3D ; + phys =3D <&usb2_phy1>; + phy-names =3D "usb"; + resets =3D <&rcc USBH_R>; + status =3D "disabled"; + }; + + usb3dr: usb@48300000 { + compatible =3D "st,stm32mp25-dwc3"; + reg =3D <0x48300000 0x100000>; + access-controllers =3D <&rifsc 66>; + clocks =3D <&rcc CK_KER_USB2PHY2>, + <&rcc CK_BUS_USB3DR>, + <&rcc CK_KER_USB2PHY2>; + clock-names =3D "ref", "bus_early", "suspend"; + interrupts =3D ; + phys =3D <&usb2_phy2>, <&combophy PHY_TYPE_USB3>; + phy-names =3D "usb2-phy", "usb3-phy"; + resets =3D <&rcc USB3DR_R>; + st,syscfg =3D <&syscfg 0x4800>; + status =3D "disabled"; + }; }; =20 bsec: efuse@44000000 { @@ -1062,9 +1119,31 @@ exti1: interrupt-controller@44220000 { }; =20 syscfg: syscon@44230000 { - compatible =3D "st,stm32mp23-syscfg", "syscon"; + compatible =3D "st,stm32mp23-syscfg", "syscon", "simple-mfd"; reg =3D <0x44230000 0x10000>; #clock-cells =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + usb2_phy1: phy@2400 { + compatible =3D "st,stm32mp25-usb2phy1"; + reg =3D <0x2400 0x24>; + #phy-cells =3D <0>; + #clock-cells =3D <1>; + clocks =3D <&rcc CK_KER_USB2PHY1>; + resets =3D <&rcc USB2PHY1_R>; + status =3D "disabled"; + }; + + usb2_phy2: phy@2800 { + compatible =3D "st,stm32mp25-usb2phy2"; + reg =3D <0x2800 0xc>; + #phy-cells =3D <0>; + #clock-cells =3D <1>; + clocks =3D <&rcc CK_KER_USB2PHY2EN>; + resets =3D <&rcc USB2PHY2_R>; + status =3D "disabled"; + }; }; =20 pinctrl: pinctrl@44240000 { --=20 2.53.0 From nobody Mon Sep 28 22:31:00 2026 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 383793E3C50; Sun, 16 Aug 2026 21:39:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=reject dis=none) header.from=nabladev.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nabladev.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b="Gm/m/cKB" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 50D1711C1F5; Sun, 16 Aug 2026 23:39:48 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1786916389; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=C5dxW+LVwtKWFFmccbVivDDq2h7Iz5VikpIl0zxDNug=; b=Gm/m/cKBnnCbegZ+pXC3JxlFGgSI4uQg2kbJLhQUY0idXSJ9eHkzjOZHOqQ81MULLQg+js Uj178wM3p7mJVDas+yFwKEoMu6JhTbgD+4Xz1fhm5NYxvnpXqa2HpYgMFcmS6ON8Nrttqx W2LVox33jitkp4vCaNGKn/W8Qebd8ZatohKaIz1kdNifdqy6WdhRdM7zE5Mx1NtI5VtbhN 2IWGyxusv2dzbE54xKAMrpR1OuVSW4VBhvJfzKNCq+dv98ZhAJaMFx8yIy1dHwJduOJ4vi gpcvuWSu8C8zPmMjIkCGDLlBConLOtqoMMB0cSpfsZh1zx+f9wglUuaL+oiDpw== From: Marek Vasut To: linux-usb@vger.kernel.org Cc: Pankaj Dev , Marek Vasut , Alexandre Torgue , Christian Bruel , Conor Dooley , Fabrice Gasnier , Greg Kroah-Hartman , Krzysztof Kozlowski , Maxime Coquelin , Neil Armstrong , Rahul Kumar , Rob Herring , Rosen Penev , Thinh Nguyen , Vinod Koul , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 9/9] arm64: dts: st: Add USB nodes on stm32mp251 Date: Sun, 16 Aug 2026 23:37:11 +0200 Message-ID: <20260816213849.1044073-10-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260816213849.1044073-1-marex@nabladev.com> References: <20260816213849.1044073-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" From: Pankaj Dev Add USB controller and PHY nodes to stm32mp251 DT. This includes two USB 2.0 FEMTO PHYs, USB 2.0 host controller and DWC3 DRD controller nodes. Co-developed-by: Pankaj Dev Signed-off-by: Pankaj Dev Signed-off-by: Marek Vasut --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Thinh Nguyen Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- V2: - Fix up Sob/Cdb lines - Move PHY into syscfg subnode - Turn st,stm32mp25-syscfg into simple-mfd - Use clock-cells =3D <1> to discern OSC and future PLL clock from the = PHY --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 65 +++++++++++++++++++++++++- 1 file changed, 64 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 6e985f115b195..6b147ed0fd550 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1746,6 +1746,47 @@ stmmac_axi_config_1: stmmac-axi-config { }; }; =20 + usbh_ohci: usb@482e0000 { + compatible =3D "generic-ohci"; + reg =3D <0x482e0000 0x1000>; + access-controllers =3D <&rifsc 63>; + clocks =3D <&usb2_phy1 0>, <&rcc CK_BUS_USB2OHCI>; + interrupts =3D ; + phys =3D <&usb2_phy1>; + phy-names =3D "usb"; + resets =3D <&rcc USBH_R>; + status =3D "disabled"; + }; + + usbh_ehci: usb@482f0000 { + compatible =3D "generic-ehci"; + reg =3D <0x482f0000 0x1000>; + access-controllers =3D <&rifsc 63>; + clocks =3D <&usb2_phy1 0>, <&rcc CK_BUS_USB2EHCI>; + companion =3D <&usbh_ohci>; + interrupts =3D ; + phys =3D <&usb2_phy1>; + phy-names =3D "usb"; + resets =3D <&rcc USBH_R>; + status =3D "disabled"; + }; + + usb3dr: usb@48300000 { + compatible =3D "st,stm32mp25-dwc3"; + reg =3D <0x48300000 0x100000>; + access-controllers =3D <&rifsc 66>; + clocks =3D <&rcc CK_KER_USB2PHY2>, + <&rcc CK_BUS_USB3DR>, + <&rcc CK_KER_USB2PHY2>; + clock-names =3D "ref", "bus_early", "suspend"; + interrupts =3D ; + phys =3D <&usb2_phy2>, <&combophy PHY_TYPE_USB3>; + phy-names =3D "usb2-phy", "usb3-phy"; + resets =3D <&rcc USB3DR_R>; + st,syscfg =3D <&syscfg 0x4800>; + status =3D "disabled"; + }; + pcie_ep: pcie-ep@48400000 { compatible =3D "st,stm32mp25-pcie-ep"; reg =3D <0x48400000 0x100000>, @@ -2002,9 +2043,31 @@ exti1: interrupt-controller@44220000 { }; =20 syscfg: syscon@44230000 { - compatible =3D "st,stm32mp25-syscfg", "syscon"; + compatible =3D "st,stm32mp25-syscfg", "syscon", "simple-mfd"; reg =3D <0x44230000 0x10000>; #clock-cells =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + usb2_phy1: phy@2400 { + compatible =3D "st,stm32mp25-usb2phy1"; + reg =3D <0x2400 0x24>; + #phy-cells =3D <0>; + #clock-cells =3D <1>; + clocks =3D <&rcc CK_KER_USB2PHY1>; + resets =3D <&rcc USB2PHY1_R>; + status =3D "disabled"; + }; + + usb2_phy2: phy@2800 { + compatible =3D "st,stm32mp25-usb2phy2"; + reg =3D <0x2800 0xc>; + #phy-cells =3D <0>; + #clock-cells =3D <1>; + clocks =3D <&rcc CK_KER_USB2PHY2EN>; + resets =3D <&rcc USB2PHY2_R>; + status =3D "disabled"; + }; }; =20 pinctrl: pinctrl@44240000 { --=20 2.53.0