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Sun, 16 Aug 2026 10:16:56 -0700 (PDT) Received: from localhost.localdomain ([240a:4280:4800:1470:95d0:2f3e:656d:65de]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39339d00eafsm4607627a91.1.2026.08.16.10.16.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 16 Aug 2026 10:16:54 -0700 (PDT) From: Liu Zhenlong To: linux-pci@vger.kernel.org Cc: jacky_chou@aspeedtech.com, mani@kernel.org, bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org, linux-aspeed@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Liu Zhenlong Subject: [PATCH] PCI: aspeed: fix clk and phy leak in aspeed_pcie_port_init error paths Date: Mon, 17 Aug 2026 01:16:33 +0800 Message-ID: <20260816171633.15025-1-dragonliu2018@gmail.com> X-Mailer: git-send-email 2.55.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" aspeed_pcie_port_init() calls clk_prepare_enable() to enable the port clock, but if phy_init() or phy_set_mode_ext() fails afterwards, the function returns without calling clk_disable_unprepare(), leaking the clock reference on every probe failure. Additionally, when phy_set_mode_ext() fails, phy_init() has already succeeded, so phy_exit() is also missing, leaking the phy reference. Add the matching clk_disable_unprepare() to both error paths, and phy_exit() to the phy_set_mode_ext() failure path, mirroring the cleanup pattern in pci-aardvark. Compile-tested with gcc on arm64 defconfig using COMPILE_TEST; no hardware available for runtime testing. Fixes: 9aa0cb68fcc1 ("PCI: aspeed: Add ASPEED PCIe RC driver") Cc: stable@vger.kernel.org Assisted-by: Claude:claude-opus-5 Signed-off-by: Liu Zhenlong --- drivers/pci/controller/pcie-aspeed.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-aspeed.c b/drivers/pci/controller/= pcie-aspeed.c index 9aa9e14c6148..1fd663ea3bf8 100644 --- a/drivers/pci/controller/pcie-aspeed.c +++ b/drivers/pci/controller/pcie-aspeed.c @@ -761,16 +761,21 @@ static int aspeed_pcie_port_init(struct aspeed_pcie_p= ort *port) port->slot); =20 ret =3D phy_init(port->phy); - if (ret) + if (ret) { + clk_disable_unprepare(port->clk); return dev_err_probe(dev, ret, "failed to init phy pcie for slot (%d)\n", port->slot); + } =20 ret =3D phy_set_mode_ext(port->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); - if (ret) + if (ret) { + phy_exit(port->phy); + clk_disable_unprepare(port->clk); return dev_err_probe(dev, ret, "failed to set phy mode for slot (%d)\n", port->slot); + } =20 reset_control_deassert(port->perst); msleep(PCIE_RESET_CONFIG_WAIT_MS); --=20 2.55.0