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Sun, 16 Aug 2026 01:28:20 -0700 (PDT) From: Sreeshankar K To: andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: bmasney@redhat.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sreeshankar K Subject: [PATCH 1/2] clk: qcom: Add Global Clock Controller (GCC) driver for SM7250 Date: Sun, 16 Aug 2026 08:28:00 +0000 Message-ID: <20260816082801.5773-2-sreeshankar0910@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260816082801.5773-1-sreeshankar0910@gmail.com> References: <20260816082801.5773-1-sreeshankar0910@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the global clock controller found on SM7250 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by: Sreeshankar K --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-sm7250.c | 2347 +++++++++++++++++++++++++++++++++ 3 files changed, 2357 insertions(+) create mode 100644 drivers/clk/qcom/gcc-sm7250.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 7d84c2f1d..3e1eac14e 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1416,6 +1416,15 @@ config SM_GCC_7150 Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, SD/UFS, PCIe etc. =20 +config SM_GCC_7250 + tristate "SM7250 Global Clock Controller" + depends on ARM64 || COMPILE_TEST + select QCOM_GDSC + help + Support for the global clock controller on SM7250 devices. + Say Y if you want to use peripheral devices such as UART, + SPI, I2C, USB, SD/UFS, PCIe etc. + config SM_GCC_MILOS tristate "Milos Global Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 58f9a5eb6..18414089c 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -174,6 +174,7 @@ obj-$(CONFIG_SM_GCC_6125) +=3D gcc-sm6125.o obj-$(CONFIG_SM_GCC_6350) +=3D gcc-sm6350.o obj-$(CONFIG_SM_GCC_6375) +=3D gcc-sm6375.o obj-$(CONFIG_SM_GCC_7150) +=3D gcc-sm7150.o +obj-$(CONFIG_SM_GCC_7250) +=3D gcc-sm7250.o obj-$(CONFIG_SM_GCC_8150) +=3D gcc-sm8150.o obj-$(CONFIG_SM_GCC_8250) +=3D gcc-sm8250.o obj-$(CONFIG_SM_GCC_8350) +=3D gcc-sm8350.o diff --git a/drivers/clk/qcom/gcc-sm7250.c b/drivers/clk/qcom/gcc-sm7250.c new file mode 100644 index 000000000..3748dacab --- /dev/null +++ b/drivers/clk/qcom/gcc-sm7250.c @@ -0,0 +1,2347 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2026, Sreeshankar K + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + P_BI_TCXO, + P_GPLL0_OUT_EVEN, + P_GPLL0_OUT_MAIN, + P_GPLL6_OUT_MAIN, + P_GPLL9_OUT_MAIN, + P_SLEEP_CLK, +}; + +static struct clk_alpha_pll gpll0 =3D { + .offset =3D 0x0, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpll0", + .parent_data =3D &(const struct clk_parent_data){ + .fw_name =3D "bi_tcxo", + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpll0_out_even[] =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll0_out_even =3D { + .offset =3D 0x0, + .post_div_shift =3D 8, + .post_div_table =3D post_div_table_gpll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_gpll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gpll0_out_even", + .parent_hws =3D (const struct clk_hw*[]){ + &gpll0.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_lucid_ops, + }, +}; + +static struct clk_alpha_pll gpll6 =3D { + .offset =3D 0x13000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(6), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpll6", + .parent_data =3D &(const struct clk_parent_data){ + .fw_name =3D "bi_tcxo", + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll9 =3D { + .offset =3D 0x1c000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(9), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpll9", + .parent_data =3D &(const struct clk_parent_data){ + .fw_name =3D "bi_tcxo", + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ops, + }, + }, +}; + +static const struct parent_map gcc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_0[] =3D { + { .fw_name =3D "bi_tcxo" }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct clk_parent_data gcc_parent_data_0_ao[] =3D { + { .fw_name =3D "bi_tcxo_ao" }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_SLEEP_CLK, 5 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_1[] =3D { + { .fw_name =3D "bi_tcxo" }, + { .hw =3D &gpll0.clkr.hw }, + { .fw_name =3D "sleep_clk" }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data gcc_parent_data_2[] =3D { + { .fw_name =3D "bi_tcxo" }, +}; + +static const struct parent_map gcc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL6_OUT_MAIN, 2 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_3[] =3D { + { .fw_name =3D "bi_tcxo" }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll6.clkr.hw }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL9_OUT_MAIN, 2 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_4[] =3D { + { .fw_name =3D "bi_tcxo" }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll9.clkr.hw }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_5[] =3D { + { P_BI_TCXO, 0 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_5[] =3D { + { .fw_name =3D "bi_tcxo" }, + { .fw_name =3D "sleep_clk" }, +}; + +static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_cpuss_ahb_clk_src =3D { + .cmd_rcgr =3D 0x48010, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_cpuss_ahb_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_cpuss_ahb_clk_src", + .parent_data =3D gcc_parent_data_0_ao, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0_ao), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_gp1_clk_src =3D { + .cmd_rcgr =3D 0x64004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gp1_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_gp2_clk_src =3D { + .cmd_rcgr =3D 0x65004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gp2_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_gp3_clk_src =3D { + .cmd_rcgr =3D 0x66004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gp3_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] =3D { + F(9600000, P_BI_TCXO, 2, 0, 0), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pdm2_clk_src =3D { + .cmd_rcgr =3D 0x33010, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pdm2_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_pdm2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] =3D { + F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), + F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), + F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), + F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), + F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), + F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), + F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), + F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), + F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), + F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), + F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s0_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src =3D { + .cmd_rcgr =3D 0x17010, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s1_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src =3D { + .cmd_rcgr =3D 0x17140, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s1_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src =3D { + .cmd_rcgr =3D 0x17270, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s3_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src =3D { + .cmd_rcgr =3D 0x173a0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s4_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src =3D { + .cmd_rcgr =3D 0x174d0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s4_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s5_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src =3D { + .cmd_rcgr =3D 0x17600, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s5_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s0_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src =3D { + .cmd_rcgr =3D 0x18010, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s1_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src =3D { + .cmd_rcgr =3D 0x18140, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s1_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src =3D { + .cmd_rcgr =3D 0x18270, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s3_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src =3D { + .cmd_rcgr =3D 0x183a0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s4_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src =3D { + .cmd_rcgr =3D 0x184d0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s4_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s5_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src =3D { + .cmd_rcgr =3D 0x18600, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s5_clk_src_init, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] =3D { + F(144000, P_BI_TCXO, 16, 3, 25), + F(400000, P_BI_TCXO, 12, 1, 4), + F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3), + F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), + F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_apps_clk_src =3D { + .cmd_rcgr =3D 0x26024, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_sdcc1_apps_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc1_apps_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .flags =3D CLK_OPS_PARENT_ENABLE, + .ops =3D &clk_rcg2_floor_ops, + }, +}; + + +static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] =3D { + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src =3D { + .cmd_rcgr =3D 0x2600c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_sdcc1_ice_core_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc1_ice_core_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_OPS_PARENT_ENABLE, + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] =3D { + F(400000, P_BI_TCXO, 12, 1, 4), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc2_apps_clk_src =3D { + .cmd_rcgr =3D 0x1400c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_4, + .freq_tbl =3D ftbl_gcc_sdcc2_apps_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc2_apps_clk_src", + .parent_data =3D gcc_parent_data_4, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_4), + .flags =3D CLK_OPS_PARENT_ENABLE, + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] =3D { + F(400000, P_BI_TCXO, 12, 1, 4), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc4_apps_clk_src =3D { + .cmd_rcgr =3D 0x1600c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_sdcc4_apps_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc4_apps_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] =3D { + F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_axi_clk_src =3D { + .cmd_rcgr =3D 0x77024, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_ufs_phy_axi_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_axi_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] =3D { + F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), + F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src =3D { + .cmd_rcgr =3D 0x7706c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_ufs_phy_ice_core_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_ice_core_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x770a0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_ufs_phy_phy_aux_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] =3D { + F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), + F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src =3D { + .cmd_rcgr =3D 0x77084, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_ufs_phy_unipro_core_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_unipro_core_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] =3D { + F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), + F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb30_prim_master_clk_src =3D { + .cmd_rcgr =3D 0xf020, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_usb30_prim_master_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb30_prim_master_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src =3D { + .cmd_rcgr =3D 0xf038, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_ufs_phy_phy_aux_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb30_prim_mock_utmi_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0xf064, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_ufs_phy_phy_aux_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb3_prim_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_aggre_ufs_phy_axi_clk =3D { + .halt_reg =3D 0x770cc, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x770cc, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x770cc, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_aggre_ufs_phy_axi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_usb3_prim_axi_clk =3D { + .halt_reg =3D 0xf080, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xf080, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_aggre_usb3_prim_axi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk =3D { + .halt_reg =3D 0x38004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x38004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(10), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_boot_rom_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camera_hf_axi_clk =3D { + .halt_reg =3D 0xb028, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb028, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camera_hf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camera_sf_axi_clk =3D { + .halt_reg =3D 0xb02c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb02c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camera_sf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camera_xo_clk =3D { + .halt_reg =3D 0xb03c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xb03c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_camera_xo_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk =3D { + .halt_reg =3D 0xf07c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xf07c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_cfg_noc_usb3_prim_axi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cpuss_ahb_clk =3D { + .halt_reg =3D 0x48000, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(21), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_cpuss_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_cpuss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cpuss_gnoc_clk =3D { + .halt_reg =3D 0x48064, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x48064, + .enable_mask =3D BIT(29), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_cpuss_gnoc_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cpuss_rbcpr_clk =3D { + .halt_reg =3D 0x48004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x48004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_cpuss_rbcpr_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ddrss_gpu_axi_clk =3D { + .halt_reg =3D 0x71154, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x71154, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ddrss_gpu_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_gpll0_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(20), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_disp_gpll0_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gpll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_hf_axi_clk =3D { + .halt_reg =3D 0xb030, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb030, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_disp_hf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_sf_axi_clk =3D { + .halt_reg =3D 0xb034, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb034, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_disp_sf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_xo_clk =3D { + .halt_reg =3D 0xb040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xb040, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_disp_xo_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk =3D { + .halt_reg =3D 0x64000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x64000, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gp1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_gp1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk =3D { + .halt_reg =3D 0x65000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x65000, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gp2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_gp2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp3_clk =3D { + .halt_reg =3D 0x66000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x66000, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gp3_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_gp3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(15), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gpu_gpll0_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gpll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_div_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(16), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gpu_gpll0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gpll0_out_even.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_iref_clk =3D { + .halt_reg =3D 0x8c014, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8c014, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gpu_iref_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_memnoc_gfx_clk =3D { + .halt_reg =3D 0x7100c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7100c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gpu_memnoc_gfx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk =3D { + .halt_reg =3D 0x71018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x71018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_gpu_snoc_dvm_gfx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_axi_clk =3D { + .halt_reg =3D 0x4d008, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4d008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_npu_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_bwmon2_axi_clk =3D { + .halt_reg =3D 0x7000c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7000c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_npu_bwmon2_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_bwmon_axi_clk =3D { + .halt_reg =3D 0x70008, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x70008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_npu_bwmon_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_bwmon_cfg_ahb_clk =3D { + .halt_reg =3D 0x70004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x70004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_npu_bwmon_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_cfg_ahb_clk =3D { + .halt_reg =3D 0x4d004, + .halt_check =3D BRANCH_HALT, + .hwcg_reg =3D 0x4d004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x4d004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_npu_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_dma_clk =3D { + .halt_reg =3D 0x4d00c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x4d00c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_npu_dma_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_gpll0_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(18), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_npu_gpll0_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gpll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_gpll0_div_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(19), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_npu_gpll0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gpll0_out_even.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm2_clk =3D { + .halt_reg =3D 0x3300c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3300c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_pdm2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_pdm2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_ahb_clk =3D { + .halt_reg =3D 0x33004, + .halt_check =3D BRANCH_HALT, + .hwcg_reg =3D 0x33004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x33004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_pdm_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_xo4_clk =3D { + .halt_reg =3D 0x33008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x33008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_pdm_xo4_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_prng_ahb_clk =3D { + .halt_reg =3D 0x34004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(13), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_prng_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_camera_nrt_ahb_clk =3D { + .halt_reg =3D 0xb018, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xb018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xb018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qmip_camera_nrt_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_camera_rt_ahb_clk =3D { + .halt_reg =3D 0xb01c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xb01c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xb01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qmip_camera_rt_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_disp_ahb_clk =3D { + .halt_reg =3D 0xb020, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xb020, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xb020, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qmip_disp_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_rt_disp_ahb_clk =3D { + .halt_reg =3D 0xb07c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xb07c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xb07c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qmip_rt_disp_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_video_cvp_ahb_clk =3D { + .halt_reg =3D 0xb010, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xb010, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xb010, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qmip_video_cvp_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_video_vcodec_ahb_clk =3D { + .halt_reg =3D 0xb014, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xb014, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xb014, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qmip_video_vcodec_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_2x_clk =3D { + .halt_reg =3D 0x23008, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(9), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_core_2x_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_clk =3D { + .halt_reg =3D 0x23000, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(8), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_core_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s0_clk =3D { + .halt_reg =3D 0x1700c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(10), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_s0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s1_clk =3D { + .halt_reg =3D 0x1713c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(11), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_s1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s2_clk =3D { + .halt_reg =3D 0x1726c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(12), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_s2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s3_clk =3D { + .halt_reg =3D 0x1739c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(13), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_s3_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s4_clk =3D { + .halt_reg =3D 0x174cc, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(14), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_s4_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s5_clk =3D { + .halt_reg =3D 0x175fc, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(15), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap0_s5_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_core_2x_clk =3D { + .halt_reg =3D 0x23140, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(18), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_core_2x_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_core_clk =3D { + .halt_reg =3D 0x23138, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(19), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_core_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s0_clk =3D { + .halt_reg =3D 0x1800c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(22), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_s0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s1_clk =3D { + .halt_reg =3D 0x1813c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(23), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_s1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s2_clk =3D { + .halt_reg =3D 0x1826c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(24), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_s2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s3_clk =3D { + .halt_reg =3D 0x1839c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(25), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_s3_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s4_clk =3D { + .halt_reg =3D 0x184cc, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(26), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_s4_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s5_clk =3D { + .halt_reg =3D 0x185fc, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(27), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap1_s5_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk =3D { + .halt_reg =3D 0x17004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(6), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap_0_m_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk =3D { + .halt_reg =3D 0x17008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x17008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(7), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap_0_s_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk =3D { + .halt_reg =3D 0x18004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(20), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap_1_m_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk =3D { + .halt_reg =3D 0x18008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x18008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(21), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_qupv3_wrap_1_s_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ahb_clk =3D { + .halt_reg =3D 0x26004, + .halt_check =3D BRANCH_HALT, + .hwcg_reg =3D 0x26004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x26004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc1_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_apps_clk =3D { + .halt_reg =3D 0x26008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x26008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc1_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_sdcc1_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ice_core_clk =3D { + .halt_reg =3D 0x2603c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2603c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc1_ice_core_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_sdcc1_ice_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_ahb_clk =3D { + .halt_reg =3D 0x14008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x14008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc2_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_apps_clk =3D { + .halt_reg =3D 0x14004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x14004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc2_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_sdcc2_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc4_ahb_clk =3D { + .halt_reg =3D 0x16008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x16008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc4_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc4_apps_clk =3D { + .halt_reg =3D 0x16004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x16004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_sdcc4_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_sdcc4_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_1x_clkref_clk =3D { + .halt_reg =3D 0x8c000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8c000, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_1x_clkref_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_ahb_clk =3D { + .halt_reg =3D 0x77018, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x77018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x77018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_axi_clk =3D { + .halt_reg =3D 0x77010, + .halt_check =3D BRANCH_HALT, + .hwcg_reg =3D 0x77010, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x77010, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_axi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_ice_core_clk =3D { + .halt_reg =3D 0x77064, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x77064, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x77064, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_ice_core_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_ice_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_phy_aux_clk =3D { + .halt_reg =3D 0x7709c, + .halt_check =3D BRANCH_HALT, + .hwcg_reg =3D 0x7709c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7709c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk =3D { + .halt_reg =3D 0x77020, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x77020, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_rx_symbol_0_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk =3D { + .halt_reg =3D 0x770b8, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x770b8, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_rx_symbol_1_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk =3D { + .halt_reg =3D 0x7701c, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x7701c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_tx_symbol_0_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_unipro_core_clk =3D { + .halt_reg =3D 0x7705c, + .halt_check =3D BRANCH_HALT, + .hwcg_reg =3D 0x7705c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7705c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_ufs_phy_unipro_core_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_master_clk =3D { + .halt_reg =3D 0xf010, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xf010, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb30_prim_master_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_mock_utmi_clk =3D { + .halt_reg =3D 0xf01c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xf01c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb30_prim_mock_utmi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_sleep_clk =3D { + .halt_reg =3D 0xf018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xf018, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb30_prim_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_clkref_clk =3D { + .halt_reg =3D 0x8c010, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8c010, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb3_prim_clkref_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_aux_clk =3D { + .halt_reg =3D 0xf054, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xf054, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb3_prim_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_com_aux_clk =3D { + .halt_reg =3D 0xf058, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xf058, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb3_prim_phy_com_aux_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_pipe_clk =3D { + .halt_reg =3D 0xf05c, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0xf05c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb3_prim_phy_pipe_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_axi_clk =3D { + .halt_reg =3D 0xb080, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xb080, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_video_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_xo_clk =3D { + .halt_reg =3D 0xb038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xb038, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_video_xo_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc ufs_phy_gdsc =3D { + .gdscr =3D 0x77004, + .pd =3D { + .name =3D "ufs_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc usb30_prim_gdsc =3D { + .gdscr =3D 0xf004, + .pd =3D { + .name =3D "usb30_prim_gdsc", + }, + .pwrsts =3D PWRSTS_RET_ON, +}; + +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc =3D { + .gdscr =3D 0x7d050, + .pd =3D { + .name =3D "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D VOTABLE, +}; + +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc =3D { + .gdscr =3D 0x7d058, + .pd =3D { + .name =3D "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D VOTABLE, +}; + +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc =3D { + .gdscr =3D 0x7d054, + .pd =3D { + .name =3D "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D VOTABLE, +}; + +static struct clk_regmap *gcc_sm7250_clocks[] =3D { + [GCC_AGGRE_UFS_PHY_AXI_CLK] =3D &gcc_aggre_ufs_phy_axi_clk.clkr, + [GCC_AGGRE_USB3_PRIM_AXI_CLK] =3D &gcc_aggre_usb3_prim_axi_clk.clkr, + [GCC_BOOT_ROM_AHB_CLK] =3D &gcc_boot_rom_ahb_clk.clkr, + [GCC_CAMERA_HF_AXI_CLK] =3D &gcc_camera_hf_axi_clk.clkr, + [GCC_CAMERA_SF_AXI_CLK] =3D &gcc_camera_sf_axi_clk.clkr, + [GCC_CAMERA_XO_CLK] =3D &gcc_camera_xo_clk.clkr, + [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] =3D &gcc_cfg_noc_usb3_prim_axi_clk.clkr, + [GCC_CPUSS_AHB_CLK] =3D &gcc_cpuss_ahb_clk.clkr, + [GCC_CPUSS_AHB_CLK_SRC] =3D &gcc_cpuss_ahb_clk_src.clkr, + [GCC_CPUSS_GNOC_CLK] =3D &gcc_cpuss_gnoc_clk.clkr, + [GCC_CPUSS_RBCPR_CLK] =3D &gcc_cpuss_rbcpr_clk.clkr, + [GCC_DDRSS_GPU_AXI_CLK] =3D &gcc_ddrss_gpu_axi_clk.clkr, + [GCC_DISP_GPLL0_CLK_SRC] =3D &gcc_disp_gpll0_clk_src.clkr, + [GCC_DISP_HF_AXI_CLK] =3D &gcc_disp_hf_axi_clk.clkr, + [GCC_DISP_SF_AXI_CLK] =3D &gcc_disp_sf_axi_clk.clkr, + [GCC_DISP_XO_CLK] =3D &gcc_disp_xo_clk.clkr, + [GCC_GP1_CLK] =3D &gcc_gp1_clk.clkr, + [GCC_GP1_CLK_SRC] =3D &gcc_gp1_clk_src.clkr, + [GCC_GP2_CLK] =3D &gcc_gp2_clk.clkr, + [GCC_GP2_CLK_SRC] =3D &gcc_gp2_clk_src.clkr, + [GCC_GP3_CLK] =3D &gcc_gp3_clk.clkr, + [GCC_GP3_CLK_SRC] =3D &gcc_gp3_clk_src.clkr, + [GCC_GPU_GPLL0_CLK_SRC] =3D &gcc_gpu_gpll0_clk_src.clkr, + [GCC_GPU_GPLL0_DIV_CLK_SRC] =3D &gcc_gpu_gpll0_div_clk_src.clkr, + [GCC_GPU_IREF_CLK] =3D &gcc_gpu_iref_clk.clkr, + [GCC_GPU_MEMNOC_GFX_CLK] =3D &gcc_gpu_memnoc_gfx_clk.clkr, + [GCC_GPU_SNOC_DVM_GFX_CLK] =3D &gcc_gpu_snoc_dvm_gfx_clk.clkr, + [GCC_NPU_AXI_CLK] =3D &gcc_npu_axi_clk.clkr, + [GCC_NPU_BWMON2_AXI_CLK] =3D &gcc_npu_bwmon2_axi_clk.clkr, + [GCC_NPU_BWMON_AXI_CLK] =3D &gcc_npu_bwmon_axi_clk.clkr, + [GCC_NPU_BWMON_CFG_AHB_CLK] =3D &gcc_npu_bwmon_cfg_ahb_clk.clkr, + [GCC_NPU_CFG_AHB_CLK] =3D &gcc_npu_cfg_ahb_clk.clkr, + [GCC_NPU_DMA_CLK] =3D &gcc_npu_dma_clk.clkr, + [GCC_NPU_GPLL0_CLK_SRC] =3D &gcc_npu_gpll0_clk_src.clkr, + [GCC_NPU_GPLL0_DIV_CLK_SRC] =3D &gcc_npu_gpll0_div_clk_src.clkr, + [GCC_PDM2_CLK] =3D &gcc_pdm2_clk.clkr, + [GCC_PDM2_CLK_SRC] =3D &gcc_pdm2_clk_src.clkr, + [GCC_PDM_AHB_CLK] =3D &gcc_pdm_ahb_clk.clkr, + [GCC_PDM_XO4_CLK] =3D &gcc_pdm_xo4_clk.clkr, + [GCC_PRNG_AHB_CLK] =3D &gcc_prng_ahb_clk.clkr, + [GCC_QMIP_CAMERA_NRT_AHB_CLK] =3D &gcc_qmip_camera_nrt_ahb_clk.clkr, + [GCC_QMIP_CAMERA_RT_AHB_CLK] =3D &gcc_qmip_camera_rt_ahb_clk.clkr, + [GCC_QMIP_DISP_AHB_CLK] =3D &gcc_qmip_disp_ahb_clk.clkr, + [GCC_QMIP_RT_DISP_AHB_CLK] =3D &gcc_qmip_rt_disp_ahb_clk.clkr, + [GCC_QMIP_VIDEO_CVP_AHB_CLK] =3D &gcc_qmip_video_cvp_ahb_clk.clkr, + [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] =3D &gcc_qmip_video_vcodec_ahb_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_2X_CLK] =3D &gcc_qupv3_wrap0_core_2x_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_CLK] =3D &gcc_qupv3_wrap0_core_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK] =3D &gcc_qupv3_wrap0_s0_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK_SRC] =3D &gcc_qupv3_wrap0_s0_clk_src.clkr, + [GCC_QUPV3_WRAP0_S1_CLK] =3D &gcc_qupv3_wrap0_s1_clk.clkr, + [GCC_QUPV3_WRAP0_S1_CLK_SRC] =3D &gcc_qupv3_wrap0_s1_clk_src.clkr, + [GCC_QUPV3_WRAP0_S2_CLK] =3D &gcc_qupv3_wrap0_s2_clk.clkr, + [GCC_QUPV3_WRAP0_S2_CLK_SRC] =3D &gcc_qupv3_wrap0_s2_clk_src.clkr, + [GCC_QUPV3_WRAP0_S3_CLK] =3D &gcc_qupv3_wrap0_s3_clk.clkr, + [GCC_QUPV3_WRAP0_S3_CLK_SRC] =3D &gcc_qupv3_wrap0_s3_clk_src.clkr, + [GCC_QUPV3_WRAP0_S4_CLK] =3D &gcc_qupv3_wrap0_s4_clk.clkr, + [GCC_QUPV3_WRAP0_S4_CLK_SRC] =3D &gcc_qupv3_wrap0_s4_clk_src.clkr, + [GCC_QUPV3_WRAP0_S5_CLK] =3D &gcc_qupv3_wrap0_s5_clk.clkr, + [GCC_QUPV3_WRAP0_S5_CLK_SRC] =3D &gcc_qupv3_wrap0_s5_clk_src.clkr, + [GCC_QUPV3_WRAP1_CORE_2X_CLK] =3D &gcc_qupv3_wrap1_core_2x_clk.clkr, + [GCC_QUPV3_WRAP1_CORE_CLK] =3D &gcc_qupv3_wrap1_core_clk.clkr, + [GCC_QUPV3_WRAP1_S0_CLK] =3D &gcc_qupv3_wrap1_s0_clk.clkr, + [GCC_QUPV3_WRAP1_S0_CLK_SRC] =3D &gcc_qupv3_wrap1_s0_clk_src.clkr, + [GCC_QUPV3_WRAP1_S1_CLK] =3D &gcc_qupv3_wrap1_s1_clk.clkr, + [GCC_QUPV3_WRAP1_S1_CLK_SRC] =3D &gcc_qupv3_wrap1_s1_clk_src.clkr, + [GCC_QUPV3_WRAP1_S2_CLK] =3D &gcc_qupv3_wrap1_s2_clk.clkr, + [GCC_QUPV3_WRAP1_S2_CLK_SRC] =3D &gcc_qupv3_wrap1_s2_clk_src.clkr, + [GCC_QUPV3_WRAP1_S3_CLK] =3D &gcc_qupv3_wrap1_s3_clk.clkr, + [GCC_QUPV3_WRAP1_S3_CLK_SRC] =3D &gcc_qupv3_wrap1_s3_clk_src.clkr, + [GCC_QUPV3_WRAP1_S4_CLK] =3D &gcc_qupv3_wrap1_s4_clk.clkr, + [GCC_QUPV3_WRAP1_S4_CLK_SRC] =3D &gcc_qupv3_wrap1_s4_clk_src.clkr, + [GCC_QUPV3_WRAP1_S5_CLK] =3D &gcc_qupv3_wrap1_s5_clk.clkr, + [GCC_QUPV3_WRAP1_S5_CLK_SRC] =3D &gcc_qupv3_wrap1_s5_clk_src.clkr, + [GCC_QUPV3_WRAP_0_M_AHB_CLK] =3D &gcc_qupv3_wrap_0_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_0_S_AHB_CLK] =3D &gcc_qupv3_wrap_0_s_ahb_clk.clkr, + [GCC_QUPV3_WRAP_1_M_AHB_CLK] =3D &gcc_qupv3_wrap_1_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_1_S_AHB_CLK] =3D &gcc_qupv3_wrap_1_s_ahb_clk.clkr, + [GCC_SDCC1_AHB_CLK] =3D &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] =3D &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC1_APPS_CLK_SRC] =3D &gcc_sdcc1_apps_clk_src.clkr, + [GCC_SDCC1_ICE_CORE_CLK] =3D &gcc_sdcc1_ice_core_clk.clkr, + [GCC_SDCC1_ICE_CORE_CLK_SRC] =3D &gcc_sdcc1_ice_core_clk_src.clkr, + [GCC_SDCC2_AHB_CLK] =3D &gcc_sdcc2_ahb_clk.clkr, + [GCC_SDCC2_APPS_CLK] =3D &gcc_sdcc2_apps_clk.clkr, + [GCC_SDCC2_APPS_CLK_SRC] =3D &gcc_sdcc2_apps_clk_src.clkr, + [GCC_SDCC4_AHB_CLK] =3D &gcc_sdcc4_ahb_clk.clkr, + [GCC_SDCC4_APPS_CLK] =3D &gcc_sdcc4_apps_clk.clkr, + [GCC_SDCC4_APPS_CLK_SRC] =3D &gcc_sdcc4_apps_clk_src.clkr, + [GCC_UFS_1X_CLKREF_CLK] =3D &gcc_ufs_1x_clkref_clk.clkr, + [GCC_UFS_PHY_AHB_CLK] =3D &gcc_ufs_phy_ahb_clk.clkr, + [GCC_UFS_PHY_AXI_CLK] =3D &gcc_ufs_phy_axi_clk.clkr, + [GCC_UFS_PHY_AXI_CLK_SRC] =3D &gcc_ufs_phy_axi_clk_src.clkr, + [GCC_UFS_PHY_ICE_CORE_CLK] =3D &gcc_ufs_phy_ice_core_clk.clkr, + [GCC_UFS_PHY_ICE_CORE_CLK_SRC] =3D &gcc_ufs_phy_ice_core_clk_src.clkr, + [GCC_UFS_PHY_PHY_AUX_CLK] =3D &gcc_ufs_phy_phy_aux_clk.clkr, + [GCC_UFS_PHY_PHY_AUX_CLK_SRC] =3D &gcc_ufs_phy_phy_aux_clk_src.clkr, + [GCC_UFS_PHY_RX_SYMBOL_0_CLK] =3D &gcc_ufs_phy_rx_symbol_0_clk.clkr, + [GCC_UFS_PHY_RX_SYMBOL_1_CLK] =3D &gcc_ufs_phy_rx_symbol_1_clk.clkr, + [GCC_UFS_PHY_TX_SYMBOL_0_CLK] =3D &gcc_ufs_phy_tx_symbol_0_clk.clkr, + [GCC_UFS_PHY_UNIPRO_CORE_CLK] =3D &gcc_ufs_phy_unipro_core_clk.clkr, + [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =3D + &gcc_ufs_phy_unipro_core_clk_src.clkr, + [GCC_USB30_PRIM_MASTER_CLK] =3D &gcc_usb30_prim_master_clk.clkr, + [GCC_USB30_PRIM_MASTER_CLK_SRC] =3D &gcc_usb30_prim_master_clk_src.clkr, + [GCC_USB30_PRIM_MOCK_UTMI_CLK] =3D &gcc_usb30_prim_mock_utmi_clk.clkr, + [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =3D + &gcc_usb30_prim_mock_utmi_clk_src.clkr, + [GCC_USB30_PRIM_SLEEP_CLK] =3D &gcc_usb30_prim_sleep_clk.clkr, + [GCC_USB3_PRIM_CLKREF_CLK] =3D &gcc_usb3_prim_clkref_clk.clkr, + [GCC_USB3_PRIM_PHY_AUX_CLK] =3D &gcc_usb3_prim_phy_aux_clk.clkr, + [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] =3D &gcc_usb3_prim_phy_aux_clk_src.clkr, + [GCC_USB3_PRIM_PHY_COM_AUX_CLK] =3D &gcc_usb3_prim_phy_com_aux_clk.clkr, + [GCC_USB3_PRIM_PHY_PIPE_CLK] =3D &gcc_usb3_prim_phy_pipe_clk.clkr, + [GCC_VIDEO_AXI_CLK] =3D &gcc_video_axi_clk.clkr, + [GCC_VIDEO_XO_CLK] =3D &gcc_video_xo_clk.clkr, + [GPLL0] =3D &gpll0.clkr, + [GPLL0_OUT_EVEN] =3D &gpll0_out_even.clkr, + [GPLL6] =3D &gpll6.clkr, + [GPLL9] =3D &gpll9.clkr, +}; + +static struct gdsc *gcc_sm7250_gdscs[] =3D { + [UFS_PHY_GDSC] =3D &ufs_phy_gdsc, + [USB30_PRIM_GDSC] =3D &usb30_prim_gdsc, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =3D + &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] =3D + &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc, + [HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] =3D + &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc, +}; + +static const struct qcom_reset_map gcc_sm7250_resets[] =3D { + [GCC_DPM_BCR] =3D { 0x46000 }, + [GCC_GPU_BCR] =3D { 0x71000 }, + [GCC_MMSS_BCR] =3D { 0xb000 }, + [GCC_NPU_BWMON_BCR] =3D { 0x70000 }, + [GCC_NPU_BCR] =3D { 0x4d000 }, + [GCC_PDM_BCR] =3D { 0x33000 }, + [GCC_PRNG_BCR] =3D { 0x34000 }, + [GCC_QUPV3_WRAPPER_0_BCR] =3D { 0x17000 }, + [GCC_QUPV3_WRAPPER_1_BCR] =3D { 0x18000 }, + [GCC_QUSB2PHY_PRIM_BCR] =3D { 0x12000 }, + [GCC_SDCC1_BCR] =3D { 0x26000 }, + [GCC_SDCC2_BCR] =3D { 0x14000 }, + [GCC_SDCC4_BCR] =3D { 0x16000 }, + [GCC_UFS_PHY_BCR] =3D { 0x77000 }, + [GCC_USB30_PRIM_BCR] =3D { 0xf000 }, + [GCC_USB3_DP_PHY_PRIM_BCR] =3D { 0x50008 }, + [GCC_USB3_PHY_PRIM_BCR] =3D { 0x50000 }, + [GCC_USB3PHY_PHY_PRIM_BCR] =3D { 0x50004 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] =3D { 0x6a000 }, +}; + +static const struct clk_rcg_dfs_data gcc_dfs_clocks[] =3D { + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), +}; + +static const struct regmap_config gcc_sm7250_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x9c100, + .fast_io =3D true, +}; + +static const struct qcom_cc_desc gcc_sm7250_desc =3D { + .config =3D &gcc_sm7250_regmap_config, + .clks =3D gcc_sm7250_clocks, + .num_clks =3D ARRAY_SIZE(gcc_sm7250_clocks), + .resets =3D gcc_sm7250_resets, + .num_resets =3D ARRAY_SIZE(gcc_sm7250_resets), + .gdscs =3D gcc_sm7250_gdscs, + .num_gdscs =3D ARRAY_SIZE(gcc_sm7250_gdscs), +}; + +static const struct of_device_id gcc_sm7250_match_table[] =3D { + { .compatible =3D "qcom,gcc-sm7250" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_sm7250_match_table); + +static int gcc_sm7250_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + regmap =3D qcom_cc_map(pdev, &gcc_sm7250_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* + * Disable the GPLL0 active input to NPU and GPU + * via MISC registers. + */ + regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); + regmap_update_bits(regmap, 0x71028, 0x3, 0x3); + + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x0b004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b008); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b00c); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x52000); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ + + ret =3D qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, + ARRAY_SIZE(gcc_dfs_clocks)); + if (ret) + return ret; + + return qcom_cc_really_probe(&pdev->dev, &gcc_sm7250_desc, regmap); +} + +static struct platform_driver gcc_sm7250_driver =3D { + .probe =3D gcc_sm7250_probe, + .driver =3D { + .name =3D "gcc-sm7250", + .of_match_table =3D gcc_sm7250_match_table, + }, +}; + +static int __init gcc_sm7250_init(void) +{ + return platform_driver_register(&gcc_sm7250_driver); +} +subsys_initcall(gcc_sm7250_init); + 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linux-kernel@vger.kernel.org, Sreeshankar K Subject: [PATCH 2/2] dt-bindings: clock: Add GCC clock bindings for SM7250 Date: Sun, 16 Aug 2026 08:28:01 +0000 Message-ID: <20260816082801.5773-3-sreeshankar0910@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260816082801.5773-1-sreeshankar0910@gmail.com> References: <20260816082801.5773-1-sreeshankar0910@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree bindings for global clock controller on SM7250 SoC. Signed-off-by: Sreeshankar K --- .../bindings/clock/qcom,gcc-sm7250.yaml | 60 +++++++ include/dt-bindings/clock/qcom,gcc-sm7250.h | 163 ++++++++++++++++++ 2 files changed, 223 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sm7250= .yaml create mode 100644 include/dt-bindings/clock/qcom,gcc-sm7250.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm7250.yaml b= /Documentation/devicetree/bindings/clock/qcom,gcc-sm7250.yaml new file mode 100644 index 000000000..822df7dc1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm7250.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sm7250.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SM7250 + +maintainers: + - Bjorn Andersson + - Sreeshankar K + +description: | + Qualcomm global clock control module provides the clocks, resets and pow= er + domains on SM7250. + + See also: include/dt-bindings/clock/qcom,gcc-sm7250.h + +properties: + compatible: + const: qcom,gcc-sm7250 + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + +required: + - compatible + - clocks + - clock-names + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@100000 { + compatible =3D "qcom,gcc-sm7250"; + reg =3D <0x00100000 0x1f0000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names =3D "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,gcc-sm7250.h b/include/dt-bindi= ngs/clock/qcom,gcc-sm7250.h new file mode 100644 index 000000000..f50a13173 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sm7250.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2026, Sreeshankar K + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM7250_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SM7250_H + +/* GCC clocks */ +#define GPLL0 0 +#define GPLL0_OUT_EVEN 1 +#define GPLL6 2 +#define GPLL9 3 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 4 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 5 +#define GCC_BOOT_ROM_AHB_CLK 6 +#define GCC_CAMERA_AHB_CLK 7 +#define GCC_CAMERA_HF_AXI_CLK 8 +#define GCC_CAMERA_SF_AXI_CLK 9 +#define GCC_CAMERA_XO_CLK 10 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 11 +#define GCC_CPUSS_AHB_CLK 12 +#define GCC_CPUSS_AHB_CLK_SRC 13 +#define GCC_CPUSS_GNOC_CLK 14 +#define GCC_CPUSS_RBCPR_CLK 15 +#define GCC_DDRSS_GPU_AXI_CLK 16 +#define GCC_DISP_GPLL0_CLK_SRC 17 +#define GCC_DISP_AHB_CLK 18 +#define GCC_DISP_HF_AXI_CLK 19 +#define GCC_DISP_SF_AXI_CLK 20 +#define GCC_DISP_XO_CLK 21 +#define GCC_GP1_CLK 22 +#define GCC_GP1_CLK_SRC 23 +#define GCC_GP2_CLK 24 +#define GCC_GP2_CLK_SRC 25 +#define GCC_GP3_CLK 26 +#define GCC_GP3_CLK_SRC 27 +#define GCC_GPU_CFG_AHB_CLK 28 +#define GCC_GPU_GPLL0_CLK_SRC 29 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 30 +#define GCC_GPU_IREF_CLK 31 +#define GCC_GPU_MEMNOC_GFX_CLK 32 +#define GCC_GPU_SNOC_DVM_GFX_CLK 33 +#define GCC_NPU_AXI_CLK 34 +#define GCC_NPU_BWMON2_AXI_CLK 35 +#define GCC_NPU_BWMON_AXI_CLK 36 +#define GCC_NPU_BWMON_CFG_AHB_CLK 37 +#define GCC_NPU_CFG_AHB_CLK 38 +#define GCC_NPU_DMA_CLK 39 +#define GCC_NPU_GPLL0_CLK_SRC 40 +#define GCC_NPU_GPLL0_DIV_CLK_SRC 41 +#define GCC_PDM2_CLK 42 +#define GCC_PDM2_CLK_SRC 43 +#define GCC_PDM_AHB_CLK 44 +#define GCC_PDM_XO4_CLK 45 +#define GCC_PRNG_AHB_CLK 46 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 47 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 48 +#define GCC_QMIP_DISP_AHB_CLK 49 +#define GCC_QMIP_RT_DISP_AHB_CLK 50 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 51 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 52 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 53 +#define GCC_QUPV3_WRAP0_CORE_CLK 54 +#define GCC_QUPV3_WRAP0_S0_CLK 55 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 56 +#define GCC_QUPV3_WRAP0_S1_CLK 57 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 58 +#define GCC_QUPV3_WRAP0_S2_CLK 59 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 60 +#define GCC_QUPV3_WRAP0_S3_CLK 61 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 62 +#define GCC_QUPV3_WRAP0_S4_CLK 63 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 64 +#define GCC_QUPV3_WRAP0_S5_CLK 65 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 66 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 67 +#define GCC_QUPV3_WRAP1_CORE_CLK 68 +#define GCC_QUPV3_WRAP1_S0_CLK 69 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 70 +#define GCC_QUPV3_WRAP1_S1_CLK 71 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 72 +#define GCC_QUPV3_WRAP1_S2_CLK 73 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 74 +#define GCC_QUPV3_WRAP1_S3_CLK 75 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 76 +#define GCC_QUPV3_WRAP1_S4_CLK 77 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 78 +#define GCC_QUPV3_WRAP1_S5_CLK 79 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 80 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 81 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 82 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 83 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 84 +#define GCC_SDCC1_AHB_CLK 85 +#define GCC_SDCC1_APPS_CLK 86 +#define GCC_SDCC1_APPS_CLK_SRC 87 +#define GCC_SDCC1_ICE_CORE_CLK 88 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 89 +#define GCC_SDCC2_AHB_CLK 90 +#define GCC_SDCC2_APPS_CLK 91 +#define GCC_SDCC2_APPS_CLK_SRC 92 +#define GCC_SDCC4_AHB_CLK 93 +#define GCC_SDCC4_APPS_CLK 94 +#define GCC_SDCC4_APPS_CLK_SRC 95 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 96 +#define GCC_UFS_1X_CLKREF_CLK 97 +#define GCC_UFS_PHY_AHB_CLK 98 +#define GCC_UFS_PHY_AXI_CLK 99 +#define GCC_UFS_PHY_AXI_CLK_SRC 100 +#define GCC_UFS_PHY_ICE_CORE_CLK 101 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 102 +#define GCC_UFS_PHY_PHY_AUX_CLK 103 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 104 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 105 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 106 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 107 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 108 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 109 +#define GCC_USB30_PRIM_MASTER_CLK 110 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 111 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 112 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 113 +#define GCC_USB30_PRIM_SLEEP_CLK 114 +#define GCC_USB3_PRIM_CLKREF_CLK 115 +#define GCC_USB3_PRIM_PHY_AUX_CLK 116 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 117 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 118 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 119 +#define GCC_VIDEO_AHB_CLK 120 +#define GCC_VIDEO_AXI_CLK 121 +#define GCC_VIDEO_XO_CLK 122 + +/* GCC resets */ +#define GCC_DPM_BCR 0 +#define GCC_GPU_BCR 1 +#define GCC_MMSS_BCR 2 +#define GCC_NPU_BWMON_BCR 3 +#define GCC_NPU_BCR 4 +#define GCC_PDM_BCR 5 +#define GCC_PRNG_BCR 6 +#define GCC_QUPV3_WRAPPER_0_BCR 7 +#define GCC_QUPV3_WRAPPER_1_BCR 8 +#define GCC_QUSB2PHY_PRIM_BCR 9 +#define GCC_SDCC1_BCR 10 +#define GCC_SDCC2_BCR 11 +#define GCC_SDCC4_BCR 12 +#define GCC_UFS_PHY_BCR 13 +#define GCC_USB30_PRIM_BCR 14 +#define GCC_USB3_DP_PHY_PRIM_BCR 15 +#define GCC_USB3_PHY_PRIM_BCR 16 +#define GCC_USB3PHY_PHY_PRIM_BCR 17 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 18 + +/* GCC power domains */ +#define UFS_PHY_GDSC 0 +#define USB30_PRIM_GDSC 1 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 2 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 3 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 4 + +#endif --=20 2.43.0