From nobody Mon Sep 28 22:28:30 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46CA73E3152 for ; Sun, 16 Aug 2026 22:13:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786918405; cv=none; b=Eeg01BNt/xexp68XDH3AwRIfoMg/H92+ymHDKRNoeAUeNUE8ia8hRDNFX7+UF/GTdYoyVPjuhQa1YuM5IQHidzRdp1J/tFUGPG5JIBbP+015w7hgCU7dpBZvRbhDCE1PMggTRxg7owT9miApXJctE8Hz++MhKcfbYMBd/gW//IY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786918405; c=relaxed/simple; bh=tTbACmVU2HxU+N4jOmNg+IWJM1yBQj2QekfY/2/BYjY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To; b=eW9jYsorjD1n20xjvz32WiWWruLaoCwbJ/+7rWGWwVosBWnqCo57VUkXjQt6HR9nXKxDdg14yZO867GLe1n34GveC4lW4ZIScaxZ0n4VcpGka+xpTxd6x1BdwRvz175otHspeR0awP6OJkeXEcMfYmmeuvRM6MFABiFxOMIiDIE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cQyBAa5T; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cQyBAa5T" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8CAA71F00A3D; Sun, 16 Aug 2026 22:13:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786918404; bh=Ur3gVV5h1X82STZEOX2VQPQaHO1sZSusqf6jY1Hr2sQ=; h=From:Date:Subject:References:In-Reply-To:To; b=cQyBAa5Tl99/VHOnrb4iwDsDNbjY7UWC9KRRWAJhC0Np18t87HKsPuzGyGjiPcJOC rujN+dQW6b0Nq/udVBg8E3SBumNfD+kBra9980KabPZtq7ijZsz67SgN0ZFDqfpGLl vWSj7shG5/2XoVMwvT4x4B5ePAp/tUhF3uVdz+xY+kKbHmerOmKRjjxOUx1OhwhSDn BnwhL2X2IuoseGSF+uf27eIYoCE/Bh+XUU+7uU/8uV4oG1c9zQZZNeM4r4JWUeN6hA yHV+EhYeD+33gWqabo37jAfX6PA2zxQK0zigaHCtTucPduDvsma3F155NsUz/m+dWl t6zMJ10HRWbXw== From: Mark Brown Date: Sun, 16 Aug 2026 23:13:15 +0100 Subject: [PATCH 1/2] regmap: Allow a base register to be specified for the RAM regmap Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260816-regmap-kunit-cache-high-bit-v1-1-2b98d9e289c2@kernel.org> References: <20260816-regmap-kunit-cache-high-bit-v1-0-2b98d9e289c2@kernel.org> In-Reply-To: <20260816-regmap-kunit-cache-high-bit-v1-0-2b98d9e289c2@kernel.org> To: linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2577; i=broonie@kernel.org; h=from:subject:message-id; bh=tTbACmVU2HxU+N4jOmNg+IWJM1yBQj2QekfY/2/BYjY=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqgjX9KEuUcuYef8ZP+aK0wLh6h9z4I4nLMbcaW i+wgFtwSIeJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaoI1/QAKCRAk1otyXVSH 0BUOB/9mYKQMH9q1M/YvW5N9fI5EFAefZaNaO6EynU279iQS40rwfQtW8F7MqV/O9k9p1MskcDp YwWrLmutD0H1Dt/EwNvavZbG1NyrQi22SPQJjKboHeTgBjxjerlt/SsZ95u3x+y8FJ6wRr2lpOq qmGU/sMTR3QE9Fel/vUjgYx6E4GDi8lQTEhxxzAi1ciVYq+PLfpaiEwjebpQ0s7fsFsHUJ81+Ax aDAlLX2POu3aPD4f33iOLXt3iomEu6tCI39l1hMfxVaN8IjJKrlCKV4q/oXBRlps1kVY6VdWWnF QnhRX9rN6oPACJ5nQHdqU/2Psdt8gWZNXfex5AsQU39b7y0T X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB To allow testing of register maps with very large register values add support for specifying base address to the RAM regmap. Signed-off-by: Mark Brown --- drivers/base/regmap/internal.h | 1 + drivers/base/regmap/regmap-ram.c | 26 ++++++++++++++++++++------ 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/base/regmap/internal.h b/drivers/base/regmap/internal.h index 55273a6178f8..8176d91aacd1 100644 --- a/drivers/base/regmap/internal.h +++ b/drivers/base/regmap/internal.h @@ -322,6 +322,7 @@ static inline unsigned int regcache_get_index_by_order(= const struct regmap *map, } =20 struct regmap_ram_data { + unsigned int base_reg; unsigned int *vals; /* Allocatd by caller */ bool *read; bool *written; diff --git a/drivers/base/regmap/regmap-ram.c b/drivers/base/regmap/regmap-= ram.c index c7356b0d8c83..a666bfb4d667 100644 --- a/drivers/base/regmap/regmap-ram.c +++ b/drivers/base/regmap/regmap-ram.c @@ -20,8 +20,11 @@ static int regmap_ram_write(void *context, unsigned int = reg, unsigned int val) { struct regmap_ram_data *data =3D context; =20 - data->vals[reg] =3D val; - data->written[reg] =3D true; + if (reg < data->base_reg) + return -EINVAL; + + data->vals[reg - data->base_reg] =3D val; + data->written[reg - data->base_reg] =3D true; =20 return 0; } @@ -30,8 +33,11 @@ static int regmap_ram_read(void *context, unsigned int r= eg, unsigned int *val) { struct regmap_ram_data *data =3D context; =20 - *val =3D data->vals[reg]; - data->read[reg] =3D true; + if (reg < data->base_reg) + return -EINVAL; + + *val =3D data->vals[reg - data->base_reg]; + data->read[reg - data->base_reg] =3D true; =20 return 0; } @@ -60,17 +66,25 @@ struct regmap *__regmap_init_ram(struct device *dev, const char *lock_name) { struct regmap *map; + unsigned int num_regs; =20 if (!config->max_register) { pr_crit("No max_register specified for RAM regmap\n"); return ERR_PTR(-EINVAL); } =20 - data->read =3D kzalloc_objs(bool, config->max_register + 1); + if (data->base_reg > config->max_register) { + pr_crit("base_reg above max_register for RAM regmap\n"); + return ERR_PTR(-EINVAL); + } + + num_regs =3D config->max_register - data->base_reg + 1; + + data->read =3D kzalloc_objs(bool, num_regs); if (!data->read) return ERR_PTR(-ENOMEM); =20 - data->written =3D kzalloc_objs(bool, config->max_register + 1); + data->written =3D kzalloc_objs(bool, num_regs); if (!data->written) { kfree(data->read); return ERR_PTR(-ENOMEM); --=20 2.47.3 From nobody Mon Sep 28 22:28:30 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 431093E4510 for ; Sun, 16 Aug 2026 22:13:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786918406; cv=none; b=dO19dbpvTPrR/p5TClY0BcZrDEmzv4Hn0axcNISArSBzLJcK/1uC/gzaemQxenB6GfLc3ph0Ljkz9ZVGpGKpS4znBai6xWjMdSxlJ3Uin1EBqvcz6fSboxN5r9cbNcCybbI70KC73juRpRAhBhATLqm4QQEaGHox1aUIJsfsR1U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786918406; c=relaxed/simple; bh=PyWUCMTjjZ8wZksjyQ8CUtfre7lqkk7/i1hO7y2k++k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To; b=JaeS8WpdOMuhQZ5KmW7Dw/jFfzjSvJ5vT1U7bZE/doRkdzBcUWt3g57rYhKxBpKpO+v0ahnMmb8XOVUNFg7lzJkuV5xRrdLTYc9gF0DV8YdoLpZZhSXW50djCHHR7JwGpnZb+of946TGTZagKU8eC3PByUJA3RLe0JHYUfnMxFg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=j8c1kT+Q; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="j8c1kT+Q" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 798CF1F00A3A; Sun, 16 Aug 2026 22:13:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786918405; bh=r/bh9AOXbjoTSoYwhwUnT+LfNy0miGP4Gh3Y2rSgDLk=; h=From:Date:Subject:References:In-Reply-To:To; b=j8c1kT+QuRkOLDd67Ts07Dv+aMF8R7m6wrL0lAvyz6iSOl+o+JH07fKDAXe/1I2Xk jbxtQbdHLy8HjN7NX3cwOTOhodZZNL7bxEOxv+GuSC/m2DYtq7fiXKpTZtCAvhjhEv ekQRhFhPYfYymwc31PwQstKbjgmK7CZVMwAKExYB6A0pCe6LoMFXiRAwZZ/KQ7UQdx BUulLtpkRqAXwKQBoGv85AWERYv3f4nVbupI2jSYfIdrI9nEPKFGTQ9ovNFjs/H2rL MQhl8VeVPQm6nTYATJxnqcAci0cC3yN+e11hvgdiYAScSUzyxf66n0IAuJxKQzDJHf IvRmEj/3seJyw== From: Mark Brown Date: Sun, 16 Aug 2026 23:13:16 +0100 Subject: [PATCH 2/2] regmap: Test rbtree and maple caches for very high register numbers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260816-regmap-kunit-cache-high-bit-v1-2-2b98d9e289c2@kernel.org> References: <20260816-regmap-kunit-cache-high-bit-v1-0-2b98d9e289c2@kernel.org> In-Reply-To: <20260816-regmap-kunit-cache-high-bit-v1-0-2b98d9e289c2@kernel.org> To: linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=5566; i=broonie@kernel.org; h=from:subject:message-id; bh=PyWUCMTjjZ8wZksjyQ8CUtfre7lqkk7/i1hO7y2k++k=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqgjX+rn5xQNAKKPih+PyLCEyWK6kj225Us/kjO OP3QXRWcTSJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaoI1/gAKCRAk1otyXVSH 0CBrB/40O3IRaO7zl7zIbDRHxvsrRqYTuqqVmGmfHjQ9azDpj9uxuaEAbveNx3R5D++5jTg+bX4 GxDHKq21nT7hBBes+3KhHWl9YeXvefTgfd6dsBZujYP8YLaMo97WzrofKEpQtqIPCiIWOtq+Rg6 8PVE0G++ZQ+udWoXiFnDaq0oHRqtdaheuVsUtFIE3CGaLOFn3SG/PM9hkkFneKJykyXlbp6qFRI NgG8l/rqHazFayHuidtzHepCfss/yMF1Q542NvKqH8NZ4jLXThqoUst8CSuYaJhmNm/O0KGTC2P 45QdGNW1jwA+TbNc2kdbQIoOkO+a+gpQ0r24EWIVDuyZiHyC X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB We've had bugs in the cache code with handling of register numbers with the top bit set before, add some test cases for this. It's not really worth fixing up all the individual tests to support a base address, instead write a specific test that reproduces a bunch of the coverge. Run this on the rbtree and maple caches which are the only ones that can reasonably support this case. Signed-off-by: Mark Brown --- drivers/base/regmap/regmap-kunit.c | 94 ++++++++++++++++++++++++++++++++++= +++- 1 file changed, 93 insertions(+), 1 deletion(-) diff --git a/drivers/base/regmap/regmap-kunit.c b/drivers/base/regmap/regma= p-kunit.c index 2999d9c185d5..98093451a7b4 100644 --- a/drivers/base/regmap/regmap-kunit.c +++ b/drivers/base/regmap/regmap-kunit.c @@ -11,6 +11,8 @@ =20 #define BLOCK_TEST_SIZE 12 =20 +#define HIGH_BIT_REG (UINT_MAX - 0x5000) + KUNIT_DEFINE_ACTION_WRAPPER(regmap_exit_action, regmap_exit, struct regmap= *); =20 struct regmap_test_priv { @@ -23,6 +25,7 @@ struct regmap_test_param { enum regcache_type cache; enum regmap_endian val_endian; =20 + unsigned int base_reg; unsigned int from_reg; bool fast_io; }; @@ -204,7 +207,8 @@ static struct regmap *gen_regmap(struct kunit *test, config->max_register +=3D (BLOCK_TEST_SIZE * config->reg_stride); } =20 - size =3D array_size(config->max_register + 1, sizeof(*buf)); + size =3D array_size(config->max_register - param->base_reg + 1, + sizeof(*buf)); buf =3D kmalloc(size, GFP_KERNEL); if (!buf) return ERR_PTR(-ENOMEM); @@ -215,6 +219,7 @@ static struct regmap *gen_regmap(struct kunit *test, if (!(*data)) goto out_free; (*data)->vals =3D buf; + (*data)->base_reg =3D param->base_reg; =20 if (config->num_reg_defaults) { defaults =3D kunit_kcalloc(test, @@ -1648,6 +1653,92 @@ static void cache_write_zero(struct kunit *test) KUNIT_ASSERT_FALSE(test, regcache_reg_cached(map, 1)); } =20 +static const struct regmap_test_param high_bit_cache_types_list[] =3D { + { .cache =3D REGCACHE_RBTREE, .from_reg =3D HIGH_BIT_REG, + .base_reg =3D HIGH_BIT_REG }, + { .cache =3D REGCACHE_MAPLE, .from_reg =3D HIGH_BIT_REG, + .base_reg =3D HIGH_BIT_REG }, +}; + +KUNIT_ARRAY_PARAM(high_bit_cache_types, high_bit_cache_types_list, param_t= o_desc); + +/* + * Dynamically allocated cache types should support registers with the + * high bit set, the backend will return an error for any operation on + * a register below the expected window. + */ +static void cache_high_bit_reg(struct kunit *test) +{ + const struct regmap_test_param *param =3D test->param_value; + struct regmap_ram_data *data; + struct regmap_config config; + struct regmap *map; + unsigned int val[BLOCK_TEST_SIZE], rval; + int i; + + config =3D test_regmap_config; + + map =3D gen_regmap(test, &config, &data); + KUNIT_ASSERT_FALSE(test, IS_ERR(map)); + if (IS_ERR(map)) + return; + + get_random_bytes(&val, sizeof(val)); + + /* No defaults so no registers cached */ + for (i =3D 0; i < BLOCK_TEST_SIZE; i++) + KUNIT_EXPECT_FALSE(test, regcache_reg_cached(map, param->from_reg + i)); + + /* Writes should reach the device */ + for (i =3D 0; i < BLOCK_TEST_SIZE; i++) + KUNIT_EXPECT_EQ(test, 0, regmap_write(map, param->from_reg + i, + val[i])); + for (i =3D 0; i < BLOCK_TEST_SIZE; i++) { + KUNIT_EXPECT_TRUE(test, data->written[i]); + KUNIT_EXPECT_EQ(test, val[i], data->vals[i]); + } + + /* Reads should be satisfied from the cache */ + for (i =3D 0; i < BLOCK_TEST_SIZE; i++) { + KUNIT_EXPECT_TRUE(test, regcache_reg_cached(map, param->from_reg + i)); + KUNIT_EXPECT_EQ(test, 0, regmap_read(map, param->from_reg + i, + &rval)); + KUNIT_EXPECT_EQ(test, val[i], rval); + KUNIT_EXPECT_FALSE(test, data->read[i]); + } + + /* Trash the data on the device then resync */ + regcache_mark_dirty(map); + for (i =3D 0; i < BLOCK_TEST_SIZE; i++) { + data->vals[i] =3D 0; + data->written[i] =3D false; + } + KUNIT_EXPECT_EQ(test, 0, regcache_sync(map)); + + /* Did we just write the correct data out? */ + for (i =3D 0; i < BLOCK_TEST_SIZE; i++) { + KUNIT_EXPECT_TRUE(test, data->written[i]); + KUNIT_EXPECT_EQ(test, val[i], data->vals[i]); + } + + /* Drop some registers */ + KUNIT_EXPECT_EQ(test, 0, regcache_drop_region(map, param->from_reg + 3, + param->from_reg + 5)); + for (i =3D 0; i < BLOCK_TEST_SIZE; i++) + KUNIT_EXPECT_EQ(test, i < 3 || i > 5, + regcache_reg_cached(map, param->from_reg + i)); + + /* Reread and check only the dropped registers hit the device */ + for (i =3D 0; i < BLOCK_TEST_SIZE; i++) + data->read[i] =3D false; + for (i =3D 0; i < BLOCK_TEST_SIZE; i++) { + KUNIT_EXPECT_EQ(test, 0, regmap_read(map, param->from_reg + i, + &rval)); + KUNIT_EXPECT_EQ(test, val[i], rval); + KUNIT_EXPECT_EQ(test, i >=3D 3 && i <=3D 5, data->read[i]); + } +} + /* Check that caching the window register works with sync */ static void cache_range_window_reg(struct kunit *test) { @@ -2168,6 +2259,7 @@ static struct kunit_case regmap_test_cases[] =3D { KUNIT_CASE_PARAM(cache_drop_all_and_sync_has_defaults, sparse_cache_types= _gen_params), KUNIT_CASE_PARAM(cache_present, sparse_cache_types_gen_params), KUNIT_CASE_PARAM(cache_write_zero, sparse_cache_types_gen_params), + KUNIT_CASE_PARAM(cache_high_bit_reg, high_bit_cache_types_gen_params), KUNIT_CASE_PARAM(cache_range_window_reg, real_cache_types_only_gen_params= ), =20 KUNIT_CASE_PARAM(raw_read_defaults_single, raw_test_types_gen_params), --=20 2.47.3