From nobody Tue Aug 25 14:34:17 2026 Received: from mail-lf1-f50.google.com (mail-lf1-f50.google.com [209.85.167.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F98D374169 for ; Sat, 15 Aug 2026 11:37:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786793828; cv=none; b=D+2GidD99pdAvMXYTczQvcPKbwrZsZQfrbeS0FTf1q/QxSTpJtRN0WOHArfnnhhRQglDFGfkpdqiJKx6v4Uf9a636Sz1hwVziaHMKgIH3KcmU50crCiEhPEiNZ1XTq7SgV46J6ClBT3/HAWcKNilu1HtGnZF9J76bkLhLOfIAz0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786793828; c=relaxed/simple; bh=tQJ0i1MfjTGpgskD8LkZJQe8cZ1L34361W7BOazpZNI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ergi+N5OLinXINGnMJe4QMuZa0s0xJnydqZoOP03CoJcU7CPBkcHCIQkB78vgcfrya1f+FTOosxzRyz6kA37/6DTzLII4h18bqH84yxM0d5Mva93QxzkaFXm36hK2j9AFr7/h75JZuZzO7WrzqQlw85zKxX86qW43VLEYjAFUtE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=TZNGZHV4; arc=none smtp.client-ip=209.85.167.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TZNGZHV4" Received: by mail-lf1-f50.google.com with SMTP id 2adb3069b0e04-5aeb8c19017so2392514e87.0 for ; Sat, 15 Aug 2026 04:37:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1786793824; x=1787398624; darn=vger.kernel.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:from:to:cc:subject :date:message-id:reply-to:content-type; bh=G8DJOAERut18sMiiQSBR+SS27P0WTvLv9LFTZmBTo+E=; b=TZNGZHV40LXxHRBx0w3bzrQMcT8Y0YeKXHRlmJkMdx7ZmxH2IbNiTyt+tJg1VPMQjo JGzCfXcF4FTTi64Y+s0qo6XPa89T6f3inPJ7U/E+TU0wTaQkOCRFnM2b10WDMSVAZ2LH 96AkUokn8GbWvf9wlSWiCHmRMnwQal8qoIfwUod+GzWdv/cBX717aQX9FNtWikxomMPF 5TZcO4COCCY7yeeOl6sCVyJTXeKD3KZszM7tFkrVqpQtgs/+1sXnMcfBA3GxLz4g467h 3mXB9ixi4LxvBRt7JZi5eU1UcOI8b/+zeMxIEKlq4F2w4lK8qoFW/fj/2QcgpyfW08EL V9yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786793824; x=1787398624; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=G8DJOAERut18sMiiQSBR+SS27P0WTvLv9LFTZmBTo+E=; b=PVe7OS11GGAJogB4WQq4Gn7pVxwtqQDQLdVsPkx84wL8fLEeNdY+lBC7SKBAbAj20h 2XB7ENqYnllBM4znmqr4y7/nyIbzqUSNGHvjwbc/RZ69gNpsrJgW5xXyN1hDWCHUJVAS OIfdI+zSsYieEGbVIwvcnRzvwEEqDr1HK4z9ZoLq1BsmP/KHOf0LY7O7iViGPMxCy3RM 27LSGYoEOuLfl6cDkxEdoaU/uq87HL2LoKIkUBiBcugHzCd6b/pizKJl22yaU6ehtyDu UFGopxL16ZPLZKYmko1dGz9ENZ9x5pqbFNpHK8wm/mIPS01fVD/qKWAKvdKt1syYiOwU 5sqw== X-Forwarded-Encrypted: i=1; AHgh+RonA6YNNHuJFJLuFNn1t6ndu5mSRXRAnQYuZGBAQBS+WgG11cObyiOjPCp1AWLEwqIHAEvfC++qTAwVmXA=@vger.kernel.org X-Gm-Message-State: AOJu0YxVatitoAGTabgeNMCb6e+6XgI6cPnP11da4uWP0K4Ql4CVi+LF exeL8CoMVXMtRT8Fn/893vKq2UfmJWLH6o2VyqjFbMv7LsS+gEvfZwXF X-Gm-Gg: AR+sD10Cjvl0X7GEZT6psgSJ9JNnovaTPzksu1Xs22tXjO0bEh3YJz60F/ExqWFvSTf 0kTTSpwR5gLFRSUNND0l1vQVkmr3/V99FiG35pYDBaOwnWtZv+/P2G631a43VYSqvwoxsnOT4kv 3XqmNZXlCoNX0s9vtXuZX6dM6AghZVU+lN/lnj4YhOi7daE2MviMuUT7Ow2ut62ZzeHmM8QN5Qk 243q4Bik73HWfKplds3XMQHRQF4PD5rxYOYCBB7SIz4DI2hU+JzbNhQ7EBrMH44icbhWo/+7Xal kJrXC5kQIYU6nshcBgLeQPTGcNmA1/o3AiBxhPEZ2qTtcF1Zhtp6R2MYhXs47fvt7UkuJtRckoy bd+IxT1mTqsaVzFokArwmbSnRDO4+P6Fhq8RfrgFninfcmSzYQkKtKVv6nQlFQ64ht7cgB/o3yf S227h3rtl3PJblLlP3vNzkrn5yT2HbdZlDyiQl6bWzm3w1pZQIXkhMmAPq2hOAwuIvJTD0lrN0Z A/Iys5iQhYWa/cFUMjWs5ag+BAkgEQ9xw== X-Received: by 2002:a05:6512:39c9:b0:5b1:4e5e:559c with SMTP id 2adb3069b0e04-5b45913b876mr2072844e87.30.1786793824145; Sat, 15 Aug 2026 04:37:04 -0700 (PDT) Received: from localhost (host-80-73-162-2.rev.as20985.net. [80.73.162.2]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5b458c0ab08sm1070598e87.73.2026.08.15.04.37.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Aug 2026 04:37:03 -0700 (PDT) From: Andrey Golovko To: Shenghao Ding , Kevin Lu , Baojun Xu , Sen Wang , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai Cc: "Holalu Yogendra, Niranjan" , Pierre-Louis Bossart , Charles Keepax , Vijendar Mukunda , Antoine Monnet , Robin Everaars , Ville Saarinen , linux-sound@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/2] ASoC: tas2783-sdw: make multi-byte MBQ registers reachable Date: Sat, 15 Aug 2026 14:40:00 +0300 Message-ID: <20260815112000.4180-2-andrey.golovko@gmail.com> In-Reply-To: <20260815112000.4180-1-andrey.golovko@gmail.com> References: <20260815112000.4180-1-andrey.golovko@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" tas2783_sdca_mbq_size() declares registers of one, two and four bytes, but the regmap is created with val_bits =3D 8. The SoundWire MBQ bus rejects any register whose declared size exceeds the configured value width: ctx->val_size =3D config->val_bits / BITS_PER_BYTE; ... size =3D ctx->cfg.mbq_size(ctx->dev, reg); if (!size || size > ctx->val_size) return -EINVAL; Both regmap_sdw_mbq_read() and regmap_sdw_mbq_write() bail out on that, so every register the driver itself declares as two or four bytes wide is unreachable through the regmap, in both directions, and the failure happens before anything reaches the bus. That is measurable. On an ASUS ProArt PX13 HN7306EAC with two TAS2783 aggregated on one link, a regmap read of XU22 Control 0x07, declared two bytes, and of XU22 Control 0x12, declared four bytes, returns -EINVAL on both amplifiers. With val_bits widened the same reads reach the peripheral, which answers -ENODATA for both, powered or not - this part appears not to implement them. So the change makes the registers addressable; whether a given peripheral answers is up to the peripheral. Widen val_bits to cover the largest size the callback returns. The callback keeps deciding the size of each individual transfer, so single-byte registers are unaffected. The calibration path needs adjusting along with it. regmap_bulk_write(..., buf, sizeof(u32)) relied on val_bits =3D 8 to spread one calibration value over four consecutive single-byte registers; with a four-byte value width the same call would ask for four four-byte values and read past the end of the four-byte buffer. Write the four registers explicitly instead, keeping the most-significant-byte -first layout. Read back over the bus, bypassing the cache, the five calibration values of both amplifiers are byte for byte what they were before this patch. What this does not do is repair regcache_sync(). On this machine a sync aborts earlier, at a single-byte Control - the FU23 Mute of channel 0, which tas2783_reg_default[] gives 0x1 while the driver's init sequence writes 0x00, so the sync tries to restore it and the peripheral answers -ENODATA - and no multi-byte register is reached at all. Signed-off-by: Andrey Golovko --- v3: new in this revision. Written on 28 July, held back until the read-only Control patches settled; it is the answer to Mark's question on v2 2/2, which cannot stand without it. sound/soc/codecs/tas2783-sdw.c | 37 +++++++++++++++++++++++++--------- 1 file changed, 28 insertions(+), 9 deletions(-) diff --git a/sound/soc/codecs/tas2783-sdw.c b/sound/soc/codecs/tas2783-sdw.c index caf8fe1bf4db..b657ad031306 100644 --- a/sound/soc/codecs/tas2783-sdw.c +++ b/sound/soc/codecs/tas2783-sdw.c @@ -564,7 +564,13 @@ static bool tas2783_volatile_register(struct device *d= ev, u32 reg) =20 static const struct regmap_config tas_regmap =3D { .reg_bits =3D 32, - .val_bits =3D 8, + /* + * tas2783_sdca_mbq_size() declares registers of one, two and four + * bytes. val_bits has to cover the widest of those: the SoundWire MBQ + * bus rejects any register whose declared size exceeds val_bits, which + * would make every multi-byte register unreachable in both directions. + */ + .val_bits =3D 32, .readable_reg =3D tas2783_readable_register, .writeable_reg =3D tas2783_writeable_register, .volatile_reg =3D tas2783_volatile_register, @@ -667,9 +673,9 @@ static s32 tas2783_validate_calibdata(struct tas2783_pr= v *tas_dev, =20 static void tas2783_set_calib_params_to_device(struct tas2783_prv *tas_dev= , u32 *cali_data) { - u32 dev_count, offset, i, device_num; + u32 dev_count, offset, i, j, device_num; u32 reg_value; - u8 buf[4]; + s32 ret; =20 dev_count =3D cali_data[1]; offset =3D 3; @@ -683,12 +689,25 @@ static void tas2783_set_calib_params_to_device(struct= tas2783_prv *tas_dev, u32 =20 for (i =3D 0; i < ARRAY_SIZE(tas2783_cali_reg); i++) { reg_value =3D cali_data[offset + i]; - buf[0] =3D reg_value >> 24; - buf[1] =3D reg_value >> 16; - buf[2] =3D reg_value >> 8; - buf[3] =3D reg_value & 0xff; - regmap_bulk_write(tas_dev->regmap, tas2783_cali_reg[i], - buf, sizeof(u32)); + + /* + * A calibration value occupies four consecutive + * single-byte registers, most significant byte first. + * Write them one by one: these registers are declared + * as one byte wide by tas2783_sdca_mbq_size(), so a + * multi-byte regmap access would not match the layout. + */ + for (j =3D 0; j < sizeof(u32); j++) { + ret =3D regmap_write(tas_dev->regmap, + tas2783_cali_reg[i] + j, + (reg_value >> (24 - 8 * j)) & 0xff); + if (ret) { + dev_err(tas_dev->dev, + "calib write to 0x%x failed, err=3D%d\n", + tas2783_cali_reg[i] + j, ret); + break; + } + } } break; } --=20 2.53.0 From nobody Tue Aug 25 14:34:17 2026 Received: from mail-lj1-f182.google.com (mail-lj1-f182.google.com [209.85.208.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04BB137702C for ; Sat, 15 Aug 2026 11:37:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786793829; cv=none; b=MYnMxNA2NQrT2EgRXpiZPGmDxveDgSBDHd3313yN9/SCsaYSAms1CxB9TcZ7WBK4uuh7+O84Q+PDO8Isw/2WTJBouO6s7wJNWGVpoMqAar5vhLlCw0b8Xs1ZVVpr/EBYbI0iVp9aab4moEo6d7g3zZCIkM+mLCLQouCGy8ZV0z0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786793829; c=relaxed/simple; bh=bFiso7/5bo2qxT7JVBiB6HAnxRgKouO81GPHXA0xeG8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XaRlj5frxtso35NuHeV+PyGpJAhhrQaAnyLraRiUl1xbM9Pwp0m1VArYKcc7BDhh/LZXQ8XO3ClcFMJ85KomxZ0iNUAk1IX0Efbz/KDsHMYjy+eVda8POkQjH/uMFbmVl2Fqq9Oy9Wrl62QEX0Z7eixQWx7cZ1E56nmP351vnkU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ChOvNQl0; arc=none smtp.client-ip=209.85.208.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ChOvNQl0" Received: by mail-lj1-f182.google.com with SMTP id 38308e7fff4ca-3a148d4509bso3523411fa.1 for ; Sat, 15 Aug 2026 04:37:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1786793825; x=1787398625; darn=vger.kernel.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:from:to:cc:subject :date:message-id:reply-to:content-type; bh=ITTecIXlxtWR6cUn9ksAsBIcZ/nNQKXG0g9oEXa5NjI=; b=ChOvNQl0RrizKzE7cpfEj8y4WZcJePCQ0EhVUVZvGjIkqcCs808E58vcEjoPDUTyDc 68r8CmZG8MB0lkEDu4wSWzd9degVSo9EDaXvfzp4GrPGnaf5vW8zsCeRjCcHKuw0XYY0 2b0qQLSMJ89SEkvD5bkhw3aiZxjU+7ru9hW+HR7ODIR4GriP2jPFTmLgmyYVURe2EXqH IVl8uRoI+4/yaXiiWNgR5ayhfurdsWwBPGpFu6Y01PH6q78yDWpKB/EV0LnKiSDzvkvN dWv8U420iJ+DaBXfzs/joBsVLpYjgbJseOD14H/LS6M9XdTSo8rUqh/eHqfD3TkTlKBn +15Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786793825; x=1787398625; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=ITTecIXlxtWR6cUn9ksAsBIcZ/nNQKXG0g9oEXa5NjI=; b=ILxXdPM4E0cq9tYdvEAdtG1cOjoThhrrchlO1mXRuLVZtWl5tQh8S1QiIuB2yQkobb VFGcUmfGvEag1IJSDnu3wjZPLaV/gvLYtTomBVHCOMnVFXi34277noqn5VCRjEUnDRR0 QEemHhptJHL3HpayFfBl6ii8pqjoTFt9cOGbERXiRbI4bej2NoszykVFoYnQOqdqbh2X 4KPfAXu09aLIrOWq98Cflj/CEdrDKJhzPZok10ePajYLo+1K2J8PsPSVkyv3yE5BeEOx KbN3BuLC4ewNLBsxPEJpx/1cRdhXEZ2a69gOijH9OU0sBS5AWOO80upbibsKbEJqLzOw ZFkg== X-Forwarded-Encrypted: i=1; AHgh+Rqh5u//N+qKb59uFgf4viS71tzJNM6VNgAPkqHFOHpWJZMQw2tYsXwZzmRL5KINh9aOuZThm8vZNn8ihpQ=@vger.kernel.org X-Gm-Message-State: AOJu0YwIiLhXfUOUYdrg67uYOpgwh18YnnqPlpTP2rwl06n4cPFuVAlo anUH3UC42GaX1RHnxTC90e4O/utWfqgAtlA/pEbO+VCg39q3PKo19g8v X-Gm-Gg: AR+sD13DHsXJcX9eYpmJ1Pz/SRCk9fQrOeAqWrWKTUglVh8n6XarBrCic7jYEpeAinO p0mAxfbltZ2GAp5gFC3px3uWgclRtRO0VFlSUsfqglMS66RjvsJQcCGL5nCQDB68z/Z1VOrr/1M 3/VokyNZM0OVCa5PgTPIzAr8WnmuJPQys8pjKzEse83AtyQsDvxU1zNew3/1k7XQ2coaezHWt8v JddgGAk8JPzQ40leN296/NkSRQy2ZeBDR1xBqGVemnKidy3stj+M5KVZwfvH8bHdGSv3Nda1aM6 PlkaKEzwuhNsRcJ57TuKy6xWyPSvydHPU7OCfE6737UeIiqMImSoxbUhlNsxuNtvOyKPfjDZOWc QNVpsFZqSSYKr7O7+PDlc32kiqmkTk9n9LoV26IXDk7TsS+nx2+4SEBu2EKPjqYut7VeS3CZSDu OR2mZ5ouqvWJIlE/oU+Mn2u/lMXt4Q/EvS8CKsqdSUA1wFvKbx4UxCRN2GomxqkxnkVRNl7YUh8 voOzcOtUGUjr9GRGm+AOzM= X-Received: by 2002:a05:651c:a347:b0:3a1:3191:2dbc with SMTP id 38308e7fff4ca-3a1327cbe76mr10906951fa.22.1786793824841; Sat, 15 Aug 2026 04:37:04 -0700 (PDT) Received: from localhost (host-80-73-162-2.rev.as20985.net. [80.73.162.2]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-3a130872f84sm10436161fa.1.2026.08.15.04.37.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Aug 2026 04:37:04 -0700 (PDT) From: Andrey Golovko To: Shenghao Ding , Kevin Lu , Baojun Xu , Sen Wang , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai Cc: "Holalu Yogendra, Niranjan" , Pierre-Louis Bossart , Charles Keepax , Vijendar Mukunda , Antoine Monnet , Robin Everaars , Ville Saarinen , linux-sound@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/2] ASoC: tas2783-sdw: do not cache read-only Controls Date: Sat, 15 Aug 2026 14:40:00 +0300 Message-ID: <20260815112000.4180-3-andrey.golovko@gmail.com> In-Reply-To: <20260815112000.4180-1-andrey.golovko@gmail.com> References: <20260815112000.4180-1-andrey.golovko@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The read-only SDCA Controls are readings of device state, but the regmap caches them and tas2783_reg_default[] gives each one a placeholder, so a read is answered from the cache and never reaches the peripheral. The answer is whatever the cache happens to hold: on an ASUS ProArt PX13 a read of the PDE23 actual power state returns the 0x3 placeholder, i.e. PS3, while the Function is powered and a cache-bypassing read of the same Control over the bus answers 0x0. Once the cache has been given a value it keeps it, so the Control reports a state the device left long ago. Mark those Controls volatile and drop their entries from the defaults. regcache_read() and regcache_write() skip volatile registers, so a read-only Control no longer enters the cache at all: reads reach the peripheral, and a sync cannot attempt to write a reading back. That is what regcache_sync() asks for in the first place - "any registers that should not be synced should be marked as volatile". The list is the same one the writeable_reg callback needs, so move it into a helper both callbacks use. The File Download Status is not on it, because the host writes that Control, but it is volatile all the same: the device raises its own bits on its own schedule, and sdca_fdl_process() reads the Control to see them. A cached answer would hide the device half of the handshake. Nothing in the driver reads any of these Controls - it performs no register reads at all - so the change is visible only through the regmap. Signed-off-by: Andrey Golovko --- v3: rebased onto for-7.3, behind 1/2, which is what makes the multi-byte Controls readable once they stop being cached. No other change since v2. v2: File Download Status is not read-only, so it is marked volatile on its own; its entry stays out of tas2783_reg_default[]. sound/soc/codecs/tas2783-sdw.c | 68 ++++++++++++++-------------------- 1 file changed, 27 insertions(+), 41 deletions(-) diff --git a/sound/soc/codecs/tas2783-sdw.c b/sound/soc/codecs/tas2783-sdw.c index b657ad031306..e859749ac825 100644 --- a/sound/soc/codecs/tas2783-sdw.c +++ b/sound/soc/codecs/tas2783-sdw.c @@ -185,35 +185,17 @@ static const struct reg_default tas2783_reg_default[]= =3D { {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_FU26, 0x01, 1), 0x1}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_FU26, 0x0b, 1), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_XU22, 0x01, 0), 0x1}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_XU22, 0x06, 0), 0x0}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_XU22, 0x07, 0), 0x0}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_XU22, 0x08, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_XU22, 0x09, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_XU22, 0x0a, 0), 0x0}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_CS24, 0x02, 0), 0x0}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_CS21, 0x02, 0), 0x0}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_CS26, 0x02, 0), 0x0}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_CS28, 0x02, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_PDE23, 0x1, 0), 0x3}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_SAPU29, 0x05, 0), 0x0}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_PPU21, 0x06, 0), 0x0}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_PPU26, 0x06, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_IT21, 0x04, 0), 0x0}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_IT21, 0x08, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_IT29, 0x04, 0), 0x0}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_IT29, 0x08, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_IT26, 0x04, 0), 0x0}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_IT26, 0x08, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_IT28, 0x04, 0), 0x0}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_IT28, 0x08, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_OT24, 0x04, 0), 0x0}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_OT24, 0x08, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_OT23, 0x04, 0), 0x0}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_OT23, 0x08, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_OT25, 0x04, 0), 0x0}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_OT25, 0x08, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_OT28, 0x04, 0), 0x0}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_OT28, 0x08, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_MU26, 0x01, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_MU26, 0x01, 1), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_MU26, 0x01, 2), 0x0}, @@ -222,40 +204,28 @@ static const struct reg_default tas2783_reg_default[]= =3D { {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_MU26, 0x01, 5), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_MU26, 0x01, 6), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_MU26, 0x01, 7), 0x0}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_MU26, 0x06, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_OT127, 0x04, 0), 0x0}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_OT127, 0x08, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_FU127, 0x01, 0), 0x1}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_FU127, 0x01, 1), 0x1}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_FU127, 0x01, 2), 0x1}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_FU127, 0x0b, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_FU127, 0x0b, 1), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_FU127, 0x0b, 2), 0x0}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_CS127, 0x02, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_MFPU21, 0x01, 0), 0x0}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_MFPU21, 0x04, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_MFPU21, 0x05, 0), 0x1}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_MFPU21, 0x08, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_MFPU26, 0x01, 0), 0x0}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_MFPU26, 0x04, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_MFPU26, 0x05, 0), 0x1}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_MFPU26, 0x08, 0), 0x0}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_FU23, 0x10, 0), 0x0}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_FU26, 0x10, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_XU22, 0x10, 0), 0x1}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_XU22, 0x12, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_XU22, 0x13, 0), 0x0}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_XU22, 0x14, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_XU22, 0x15, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_XU22, 0x16, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_CS24, 0x10, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_CS21, 0x10, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_CS26, 0x10, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_CS28, 0x10, 0), 0x0}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_PDE23, 0x10, 0), 0x3}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_UDMPU23, 0x10, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_SAPU29, 0x10, 0), 0x1}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_SAPU29, 0x11, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_SAPU29, 0x12, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_PPU21, 0x10, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_PPU21, 0x11, 0), 0x0}, @@ -286,7 +256,6 @@ static const struct reg_default tas2783_reg_default[] = =3D { {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_OT127, 0x12, 5), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_OT127, 0x12, 6), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_OT127, 0x12, 7), 0x0}, - {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_FU127, 0x10, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_CS127, 0x10, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_MFPU21, 0x10, 0), 0x0}, {SDW_SDCA_CTL(1, TAS2783_SDCA_ENT_MFPU21, 0x11, 0), 0x0}, @@ -495,15 +464,15 @@ static bool tas2783_readable_register(struct device *= dev, unsigned int reg) return tas2783_sdca_mbq_size(dev, reg) > 0; } =20 -static bool tas2783_writeable_register(struct device *dev, unsigned int re= g) +/* + * The read-only SDCA Controls the driver describes: the Latency of every + * Entity, the Clock Valid of every Clock Source, the actual power state of + * the Power Domain Entity, the protection status, the algorithm ready flag + * and the Extension Unit id, version and firmware download status. None = of + * them is a setting; every one is a reading of device state. + */ +static bool tas2783_read_only_control(unsigned int reg) { - /* - * The Latency Control of every Entity, together with the Power Domain - * actual state and the protection status, is read-only. They are - * listed in tas2783_reg_default[] with a placeholder value, so without - * this a regcache_sync() would try to write them back and the - * peripheral would reject the transaction, aborting the sync. - */ switch (reg) { case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, TAS2783_SDCA_ENT_FU21, 0x10, 0): case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, TAS2783_SDCA_ENT_FU23, 0x10, 0): @@ -538,16 +507,33 @@ static bool tas2783_writeable_register(struct device = *dev, unsigned int reg) case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, TAS2783_SDCA_ENT_MFPU21, 0x04, 0): case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, TAS2783_SDCA_ENT_MFPU26, 0x08, 0): case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, TAS2783_SDCA_ENT_MFPU26, 0x04, 0): - return false; + return true; =20 default: - return tas2783_sdca_mbq_size(dev, reg) > 0; + return false; } } =20 +static bool tas2783_writeable_register(struct device *dev, unsigned int re= g) +{ + if (tas2783_read_only_control(reg)) + return false; + + return tas2783_sdca_mbq_size(dev, reg) > 0; +} + static bool tas2783_volatile_register(struct device *dev, u32 reg) { + if (tas2783_read_only_control(reg)) + return true; + switch (reg) { + /* + * The File Download Status is a handshake: the device raises its own + * bits on its own schedule and the host writes back a response, so it + * is writable, but it must never be answered from the cache. + */ + case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, TAS2783_SDCA_ENT_XU22, 0x14, 0): case 0x000 ... 0x080: /* Data port 0. */ case 0x100 ... 0x140: /* Data port 1. */ case 0x200 ... 0x240: /* Data port 2. */ --=20 2.53.0