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Fri, 14 Aug 2026 16:58:34 -0700 (PDT) Received: from fedora ([5.31.134.170]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499899753ccsm77751245e9.0.2026.08.14.16.58.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Aug 2026 16:58:34 -0700 (PDT) From: Mohamed Ahmed To: linux-kernel@vger.kernel.org Cc: dri-devel@lists.freedesktop.org, Lyude Paul , Danilo Krummrich , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Mary Guillemard , nouveau@lists.freedesktop.org, Mohamed Ahmed Subject: [PATCH 1/7] nouveau/disp: add GB20x HDMI vendor infoframe writer Date: Sat, 15 Aug 2026 03:56:59 +0400 Message-ID: <20260814235705.59132-2-mohamedahmedegypt2001@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260814235705.59132-1-mohamedahmedegypt2001@gmail.com> References: <20260814235705.59132-1-mohamedahmedegypt2001@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" GB20x (NVDisplay 5.0) reorganised the SF HDMI packet units and the legacy VSI unit at 0x6f0100 no longer exists. Per NVIDIA's published CA71 DISP_SF_USER class header, only three legacy units remain (AVI at +0x000, GCP at +0x040, ACR at +0x080), and vendor infoframes must instead be sent through the shared generic infoframe units at +0x130, which feed a 9-dword data FIFO at +0x3f0/+0x3f4. Add a VSI writer using the same programming sequence OpenRM uses on these chips (nvhdmipkt_C971.c, programAdvancedInfoframeC971()): disable the unit and wait for it to idle, clear the SENT status, write the packet through the data FIFO with a zero HB3 inserted after the three header bytes, then enable the unit for every-frame transmission during vblank. Generic unit 1 is used for the VSI, matching the slot assignment in NVIDIA's nvkms (NVHDMIPKT_TYPE_SHARED_GENERIC2, unit 0 is reserved for extended metadata packets and unit 2 for the HDR DRM infoframe, if those are wired up later). Signed-off-by: Mohamed Ahmed --- .../gpu/drm/nouveau/nvkm/engine/disp/Kbuild | 1 + .../gpu/drm/nouveau/nvkm/engine/disp/gb202.c | 62 +++++++++++++++++++ .../gpu/drm/nouveau/nvkm/engine/disp/ior.h | 2 + 3 files changed, 65 insertions(+) create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/disp/gb202.c diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild b/drivers/gpu/= drm/nouveau/nvkm/engine/disp/Kbuild index e1aecd3fe96c..98d6ca5ac311 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild @@ -27,6 +27,7 @@ nvkm-y +=3D nvkm/engine/disp/gp102.o nvkm-y +=3D nvkm/engine/disp/gv100.o nvkm-y +=3D nvkm/engine/disp/tu102.o nvkm-y +=3D nvkm/engine/disp/ga102.o +nvkm-y +=3D nvkm/engine/disp/gb202.o =20 nvkm-y +=3D nvkm/engine/disp/udisp.o nvkm-y +=3D nvkm/engine/disp/uconn.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gb202.c b/drivers/gpu= /drm/nouveau/nvkm/engine/disp/gb202.c new file mode 100644 index 000000000000..8fd72bcb6f04 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gb202.c @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2026 Valve Corp. + */ +#include "priv.h" +#include "ior.h" + +#include + +/* GB20x (NVD5.0) reorganised the SF HDMI packet units. The AVI unit is + * unchanged from GV100, but the legacy VSI unit is gone. Vendor infoframes + * are sent through the shared generic infoframe units instead. Register + * layout per NVIDIA's clc971.h/clca71.h, programming sequence per + * nvhdmipkt_C971.c:programAdvancedInfoframeC971(). + */ +void +gb202_sor_hdmi_infoframe_vsi(struct nvkm_ior *ior, int head, void *data, u= 32 size) +{ + struct nvkm_device *device =3D ior->disp->engine.subdev.device; + const u32 hoff =3D head * 0x400; + /* Generic infoframe unit 1, the slot NVIDIA's driver uses for the VSI. */ + const u32 ctrl =3D 0x6f0138 + hoff; + u8 buf[36] =3D {}; + int i; + + /* Disable the unit and wait for it to go idle. */ + nvkm_mask(device, ctrl, 0x00000001, 0x00000000); + if (nvkm_msec(device, 2000, + if (!(nvkm_rd32(device, ctrl) & 0x00400000)) + break; + ) < 0) + return; + + if (!size) + return; + + /* Clear SENT status, and point the data FIFO at unit 1's slot. */ + nvkm_mask(device, ctrl, 0x00800000, 0x00800000); + nvkm_wr32(device, 0x6f03f0 + hoff, 0x00000001); + + /* The FIFO takes the raw packet, except that a zero HB3 is inserted + * after the three header bytes. A unit sends 36 bytes. + */ + size =3D min_t(u32, size, 31); + memcpy(buf, data, min_t(u32, size, 3)); + if (size > 3) + memcpy(&buf[4], (u8 *)data + 3, size - 3); + + for (i =3D 0; i < 36; i +=3D 4) { + nvkm_wr32(device, 0x6f03f4 + hoff, buf[i + 0] | buf[i + 1] << 8 | + buf[i + 2] << 16 | buf[i + 3] << 24); + } + + /* No flip ID or scanline matching. */ + nvkm_wr32(device, 0x6f013c + hoff, 0x00000000); + + /* ENABLE | RUN_MODE=3DALWAYS | LOC=3DVBLANK | OFFSET=3D1 | SIZE=3D0. */ + nvkm_wr32(device, ctrl, 0x00000041); + + /* Audio priority low (the init value). */ + nvkm_wr32(device, 0x6f03f8 + hoff, 0x00000002); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h b/drivers/gpu/d= rm/nouveau/nvkm/engine/disp/ior.h index 3ba04bead2f9..8906fe8ef404 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h @@ -196,6 +196,8 @@ extern const struct nvkm_ior_func_hda gv100_sor_hda; =20 void tu102_sor_dp_vcpi(struct nvkm_ior *, int, u8, u8, u16, u16); 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Fri, 14 Aug 2026 16:58:46 -0700 (PDT) Received: from fedora ([5.31.134.170]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499899753ccsm77751245e9.0.2026.08.14.16.58.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Aug 2026 16:58:45 -0700 (PDT) From: Mohamed Ahmed To: linux-kernel@vger.kernel.org Cc: dri-devel@lists.freedesktop.org, Lyude Paul , Danilo Krummrich , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Mary Guillemard , nouveau@lists.freedesktop.org, Mohamed Ahmed Subject: [PATCH 2/7] nouveau/gsp: fix HDMI vendor infoframes on GB20x Date: Sat, 15 Aug 2026 03:57:00 +0400 Message-ID: <20260814235705.59132-3-mohamedahmedegypt2001@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260814235705.59132-1-mohamedahmedegypt2001@gmail.com> References: <20260814235705.59132-1-mohamedahmedegypt2001@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The GSP path reuses the GV100 direct-MMIO infoframe writers on every chip. On GB20x that is only half right as while the legacy SF AVI unit is unchanged, the legacy VSI unit at 0x6f0100 was removed, so gv100_sor_hdmi_infoframe_vsi() writes into a reserved area and no vendor infoframe ever reaches the wire. This affects HDMI-VIC signalling which can impact some 4K modes for legacy HDMI 1.4 sinks. Select the SOR functions per GPU family in r535_sor_new(), keyed on the display root class from the RM GPU table and use the new generic-infoframe VSI writer on GB20x. Everything else stays on the r535 table. Signed-off-by: Mohamed Ahmed --- .../nouveau/nvkm/subdev/gsp/rm/r535/disp.c | 29 ++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c b/drive= rs/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c index 1155f079b0c3..96febd01da78 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c @@ -36,6 +36,8 @@ =20 #include =20 +#include + #include =20 #include "nvrm/disp.h" @@ -587,6 +589,16 @@ r535_sor_hdmi =3D { .audio =3D r535_sor_hdmi_audio, }; =20 +static const struct nvkm_ior_func_hdmi +gb202_sor_hdmi =3D { + .ctrl =3D r535_sor_hdmi_ctrl, + /* The legacy AVI unit is unchanged on GB20x. */ + .infoframe_avi =3D gv100_sor_hdmi_infoframe_avi, + .infoframe_vsi =3D gb202_sor_hdmi_infoframe_vsi, + .audio =3D r535_sor_hdmi_audio, + .frl_train =3D r535_sor_frl_train, +}; + static const struct nvkm_ior_func r535_sor =3D { .hdmi =3D &r535_sor_hdmi, @@ -595,10 +607,25 @@ r535_sor =3D { .bl =3D &r535_sor_bl, }; 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charset="utf-8" r535_sor_hdmi_audio() brackets audio enablement with a General Control Packet AVMute toggle written through the legacy GCP unit at 0x6f00c0/0x6f00cc. On GB20x the SF packet units were compacted and the old generic and audio-infoframe units are gone and the GCP unit moved from slot 3 to slot 1 (control 0x6f0040 and subpack 0x6f004c from NVIDIA's published clc971.h. The same offsets are also used by OpenRM's hdmiWriteGeneralCtrlPacketC871() on these chips). The old addresses are reserved on GB20x, so the AVMute writes were silent no-ops and mitigated only by the equivalent GCP this function already sends through the SET_OD_PACKET RM control. Add a GB20x variant of the audio function using the new offsets, keeping the direct MMIO path in sync with the hardware as on earlier chips. Signed-off-by: Mohamed Ahmed --- .../drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c b/drive= rs/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c index 96febd01da78..f51ad7c754d8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c @@ -559,6 +559,21 @@ r535_sor_hdmi_audio(struct nvkm_ior *sor, int head, bo= ol enable) nvkm_mask(device, 0x6f00c0 + hdmi, 0x00000001, 0x00000001); } =20 +static void +gb202_sor_hdmi_audio(struct nvkm_ior *sor, int head, bool enable) +{ + struct nvkm_device *device =3D sor->disp->engine.subdev.device; + const u32 hdmi =3D head * 0x400; + + r535_sor_hdmi_ctrl_audio(sor->asy.outp, enable); + r535_sor_hdmi_ctrl_audio_mute(sor->asy.outp, !enable); + + /* General Control (GCP): the unit moved to slot 1 on NVD5.0. */ + nvkm_mask(device, 0x6f0040 + hdmi, 0x00000001, 0x00000000); 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Fri, 14 Aug 2026 16:58:56 -0700 (PDT) Received: from fedora ([5.31.134.170]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499899753ccsm77751245e9.0.2026.08.14.16.58.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Aug 2026 16:58:55 -0700 (PDT) From: Mohamed Ahmed To: linux-kernel@vger.kernel.org Cc: dri-devel@lists.freedesktop.org, Lyude Paul , Danilo Krummrich , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Mary Guillemard , nouveau@lists.freedesktop.org, Mohamed Ahmed Subject: [PATCH 4/7] nouveau/gsp: use per-version DP_CONFIG_STREAM params on r570 firmware Date: Sat, 15 Aug 2026 03:57:02 +0400 Message-ID: <20260814235705.59132-5-mohamedahmedegypt2001@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260814235705.59132-1-mohamedahmedegypt2001@gmail.com> References: <20260814235705.59132-1-mohamedahmedegypt2001@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" NVIDIA removed the deprecated actualPclkHz/linkClkFreqHz fields and the whole Legacy{activeCnt, activeFrac, activePolarity, mvidWarEnabled, MvidWarParams} block from the SST sub-struct of NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS between the 535 and 570 releases (compared in OpenRM tags 535.113.01 vs 570.144), shrinking the struct. Everything nouveau writes sits at identical offsets in both layouts but the size is wrong on r570, which means r535_sor_dp_sst() and r535_sor_dp_vcpi() are sent with an incorrect size. Route the .sst/.vcpi IOR functions through nvkm_rm_api_disp the same way bl_ctrl and dp.get_caps/set_indexed_link_rates already are. Keep the existing implementation for r535 and add an r570 implementation built against the 570.144 layout, which already exists in r570/nvrm/disp.h but was unused until now. Also add the NV0073_CTRL_CMD_DP_CONFIG_STREAM define that was missing from the layout. Other DP controls sent through shared r535 code did not change layout between the tags. Signed-off-by: Mohamed Ahmed --- .../nouveau/nvkm/subdev/gsp/rm/r535/disp.c | 25 +++++++- .../nouveau/nvkm/subdev/gsp/rm/r570/disp.c | 64 +++++++++++++++++++ .../nvkm/subdev/gsp/rm/r570/nvrm/disp.h | 2 + .../gpu/drm/nouveau/nvkm/subdev/gsp/rm/rm.h | 5 ++ 4 files changed, 93 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c b/drive= rs/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c index f51ad7c754d8..dd632767aea5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c @@ -403,7 +403,7 @@ r535_sor_dp_audio(struct nvkm_ior *sor, int head, bool = enable) } =20 static void -r535_sor_dp_vcpi(struct nvkm_ior *sor, int head, u8 slot, u8 slot_nr, u16 = pbn, u16 aligned_pbn) +r535_dp_vcpi(struct nvkm_ior *sor, int head, u8 slot, u8 slot_nr, u16 pbn,= u16 aligned_pbn) { struct nvkm_disp *disp =3D sor->disp; struct NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS *ctrl; @@ -434,9 +434,17 @@ r535_sor_dp_vcpi(struct nvkm_ior *sor, int head, u8 sl= ot, u8 slot_nr, u16 pbn, u WARN_ON(nvkm_gsp_rm_ctrl_wr(&disp->rm.objcom, ctrl)); } =20 +static void +r535_sor_dp_vcpi(struct nvkm_ior *sor, int head, u8 slot, u8 slot_nr, u16 = pbn, u16 aligned_pbn) +{ + const struct nvkm_rm_api *rmapi =3D sor->disp->engine.subdev.device->gsp-= >rm->api; + + rmapi->disp->dp.vcpi(sor, head, slot, slot_nr, pbn, aligned_pbn); +} + static int -r535_sor_dp_sst(struct nvkm_ior *sor, int head, bool ef, - u32 watermark, u32 hblanksym, u32 vblanksym) +r535_dp_sst(struct nvkm_ior *sor, int head, bool ef, + u32 watermark, u32 hblanksym, u32 vblanksym) { struct nvkm_disp *disp =3D sor->disp; struct NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS *ctrl; @@ -463,6 +471,15 @@ r535_sor_dp_sst(struct nvkm_ior *sor, int head, bool e= f, return nvkm_gsp_rm_ctrl_wr(&disp->rm.objcom, ctrl); } =20 +static int +r535_sor_dp_sst(struct nvkm_ior *sor, int head, bool ef, + u32 watermark, u32 hblanksym, u32 vblanksym) +{ + const struct nvkm_rm_api *rmapi =3D sor->disp->engine.subdev.device->gsp-= >rm->api; + + return rmapi->disp->dp.sst(sor, head, ef, watermark, hblanksym, vblanksym= ); +} + static const struct nvkm_ior_func_dp r535_sor_dp =3D { .sst =3D r535_sor_dp_sst, @@ -1828,6 +1845,8 @@ r535_disp =3D { .dp =3D { .get_caps =3D r535_dp_get_caps, .set_indexed_link_rates =3D r535_dp_set_indexed_link_rates, + .sst =3D r535_dp_sst, + .vcpi =3D r535_dp_vcpi, }, .chan =3D { .set_pushbuf =3D r535_disp_chan_set_pushbuf, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/disp.c b/drive= rs/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/disp.c index a96e31c2d80b..61f82e15ff39 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/disp.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/disp.c @@ -5,6 +5,7 @@ #include =20 #include +#include #include =20 #include "nvhw/drf.h" @@ -74,6 +75,67 @@ r570_disp_chan_set_pushbuf(struct nvkm_disp *disp, s32 o= class, int inst, struct return nvkm_gsp_rm_ctrl_wr(&gsp->internal.device.subdevice, ctrl); } =20 +static void +r570_dp_vcpi(struct nvkm_ior *sor, int head, u8 slot, u8 slot_nr, u16 pbn,= u16 aligned_pbn) +{ + struct nvkm_disp *disp =3D sor->disp; + NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS *ctrl; + + ctrl =3D nvkm_gsp_rm_ctrl_get(&disp->rm.objcom, + NV0073_CTRL_CMD_DP_CONFIG_STREAM, sizeof(*ctrl)); + if (WARN_ON(IS_ERR(ctrl))) + return; + + ctrl->subDeviceInstance =3D 0; + ctrl->head =3D head; + ctrl->sorIndex =3D sor->id; + ctrl->dpLink =3D sor->asy.link =3D=3D 2; + ctrl->bEnableOverride =3D 1; + ctrl->bMST =3D 1; + ctrl->hBlankSym =3D 0; + ctrl->vBlankSym =3D 0; + ctrl->colorFormat =3D 0; + ctrl->bEnableTwoHeadOneOr =3D 0; + ctrl->singleHeadMultistreamMode =3D 0; + ctrl->MST.slotStart =3D slot; + ctrl->MST.slotEnd =3D slot + slot_nr - 1; + ctrl->MST.PBN =3D pbn; + ctrl->MST.Timeslice =3D aligned_pbn; + ctrl->MST.sendACT =3D 0; + ctrl->MST.singleHeadMSTPipeline =3D 0; + ctrl->MST.bEnableAudioOverRightPanel =3D 0; + WARN_ON(nvkm_gsp_rm_ctrl_wr(&disp->rm.objcom, ctrl)); +} + +static int +r570_dp_sst(struct nvkm_ior *sor, int head, bool ef, + u32 watermark, u32 hblanksym, u32 vblanksym) +{ + struct nvkm_disp *disp =3D sor->disp; + NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS *ctrl; + + ctrl =3D nvkm_gsp_rm_ctrl_get(&disp->rm.objcom, + NV0073_CTRL_CMD_DP_CONFIG_STREAM, sizeof(*ctrl)); + if (IS_ERR(ctrl)) + return PTR_ERR(ctrl); + + ctrl->subDeviceInstance =3D 0; + ctrl->head =3D head; + ctrl->sorIndex =3D sor->id; + ctrl->dpLink =3D sor->asy.link =3D=3D 2; + ctrl->bEnableOverride =3D 1; + ctrl->bMST =3D 0; + ctrl->hBlankSym =3D hblanksym; + ctrl->vBlankSym =3D vblanksym; + ctrl->colorFormat =3D 0; + ctrl->bEnableTwoHeadOneOr =3D 0; + ctrl->SST.bEnhancedFraming =3D ef; + ctrl->SST.tuSize =3D 64; + ctrl->SST.waterMark =3D watermark; + ctrl->SST.bEnableAudioOverRightPanel =3D 0; + return nvkm_gsp_rm_ctrl_wr(&disp->rm.objcom, ctrl); +} + static int r570_dp_set_indexed_link_rates(struct nvkm_outp *outp) { @@ -255,6 +317,8 @@ r570_disp =3D { .dp =3D { .get_caps =3D r570_dp_get_caps, .set_indexed_link_rates =3D r570_dp_set_indexed_link_rates, + .sst =3D r570_dp_sst, + .vcpi =3D r570_dp_vcpi, }, .chan =3D { .set_pushbuf =3D r570_disp_chan_set_pushbuf, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/nvrm/disp.h b/= drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/nvrm/disp.h index 06e972835d77..742b25a2a12d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/nvrm/disp.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/nvrm/disp.h @@ -256,6 +256,8 @@ typedef struct NV0073_CTRL_DP_CTRL_PARAMS { NvU32 eightLaneDpcdBaseAddr; } NV0073_CTRL_DP_CTRL_PARAMS; =20 +#define NV0073_CTRL_CMD_DP_CONFIG_STREAM (0x731362U) /* = finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0= 073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS_MESSAGE_ID" */ + typedef struct NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS { NvU32 subDeviceInstance; NvU32 head; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/rm.h b/drivers/gpu/= drm/nouveau/nvkm/subdev/gsp/rm/rm.h index a9af94adf9ef..e0c10a7e3452 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/rm.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/rm.h @@ -6,6 +6,7 @@ #ifndef __NVKM_RM_H__ #define __NVKM_RM_H__ #include "handles.h" +struct nvkm_ior; struct nvkm_outp; struct r535_gr; =20 @@ -93,6 +94,10 @@ struct nvkm_rm_api { struct { int (*get_caps)(struct nvkm_disp *, int *link_bw, bool *mst, bool *wm); int (*set_indexed_link_rates)(struct nvkm_outp *); + int (*sst)(struct nvkm_ior *, int head, bool ef, + u32 watermark, u32 hblanksym, u32 vblanksym); + void (*vcpi)(struct nvkm_ior *, int head, + u8 slot, u8 slot_nr, u16 pbn, u16 aligned_pbn); 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Fri, 14 Aug 2026 16:59:01 -0700 (PDT) Received: from fedora ([5.31.134.170]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499899753ccsm77751245e9.0.2026.08.14.16.58.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Aug 2026 16:59:00 -0700 (PDT) From: Mohamed Ahmed To: linux-kernel@vger.kernel.org Cc: dri-devel@lists.freedesktop.org, Lyude Paul , Danilo Krummrich , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Mary Guillemard , nouveau@lists.freedesktop.org, Mohamed Ahmed Subject: [PATCH 5/7] nouveau/gsp: fix vblank interrupts on GB20x Date: Sat, 15 Aug 2026 03:57:03 +0400 Message-ID: <20260814235705.59132-6-mohamedahmedegypt2001@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260814235705.59132-1-mohamedahmedegypt2001@gmail.com> References: <20260814235705.59132-1-mohamedahmedegypt2001@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The GSP path programs per-head timing (vblank) interrupts the same way on every generation. NVD5.0 (GB20x) reworked the FE interrupt frontend around four message-based kernel vectors (high latency, low latency, PMU, and GSP) and moved RM head-timing interrupts to the dedicated low-latency vector: - The enable is NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING, 0x611ef0 + head*4 (570.144 kernel_head_0501.c and v05_01 dev_disp.h. (Renamed kernel_head_0502.c in 610 releases)). - The vector is reported as a separate interrupt table entry, MC_ENGINE_IDX_DISP_LOW (intr_gb202.c, intrCacheDispIntrVectors). - The vector must be re-armed through NV_PDISP_FE_INTR_RETRIGGER(1) at 0x611f34 after servicing (kdispServiceInterrupt -> kdispIntrRetrigger_v05_01). The event latch (0x611800), per-head status (0x611c00), and dispatch summary (0x611ec0) the interrupt handler uses are unchanged on GB20x (kheadReadPendingVblank_v03_00 and kheadResetPendingLastData_v03_00 remain for DISPv0502+). On GB20x the old code enables head timing onto the legacy vector, leaves its handler there, and never re-arms the message-based vectors. Page flips still complete (nv50 sends those events from the commit path), so the desktop looks fine while DRM vblank waits and vblank sequence queries are affected. Select the head functions and the interrupt handler per generation in r535_disp_oneinit(), keyed on the display root class from the RM GPU table like the SOR split. Translate the low-latency interrupt table as a second NVKM_ENGINE_DISP instance, attach the handler to it on GB20x, and retrigger the vector after servicing. Signed-off-by: Mohamed Ahmed --- .../nouveau/nvkm/subdev/gsp/rm/r535/disp.c | 63 ++++++++++++++++++- .../drm/nouveau/nvkm/subdev/gsp/rm/r570/gsp.c | 8 +++ 2 files changed, 68 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c b/drive= rs/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c index dd632767aea5..248ed6368e48 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c @@ -696,6 +696,33 @@ r535_head =3D { .vblank_put =3D r535_head_vblank_put, }; =20 +/* NVD5.0 (GB20x and later) moved the RM head-timing interrupt enable to + * the low-latency vector's EN1 block. The event latch is unchanged. + */ +static void +gb202_head_vblank_put(struct nvkm_head *head) +{ + struct nvkm_device *device =3D head->disp->engine.subdev.device; + + nvkm_mask(device, 0x611ef0 + (head->id * 4), 0x00000002, 0x00000000); +} + +static void +gb202_head_vblank_get(struct nvkm_head *head) +{ + struct nvkm_device *device =3D head->disp->engine.subdev.device; + + nvkm_wr32(device, 0x611800 + (head->id * 4), 0x00000002); + nvkm_mask(device, 0x611ef0 + (head->id * 4), 0x00000002, 0x00000002); +} + +static const struct nvkm_head_func +gb202_head =3D { + .state =3D r535_head_state, + .vblank_get =3D gb202_head_vblank_get, + .vblank_put =3D gb202_head_vblank_put, +}; + static struct nvkm_conn * r535_conn_new(struct nvkm_disp *disp, u32 id) { @@ -1496,6 +1523,20 @@ r535_disp_intr(struct nvkm_inth *inth) return IRQ_HANDLED; } =20 +static irqreturn_t +gb202_disp_intr(struct nvkm_inth *inth) +{ + struct nvkm_disp *disp =3D container_of(inth, typeof(*disp), engine.subde= v.inth); + irqreturn_t ret =3D r535_disp_intr(inth); + + /* The FE interrupt vectors are message-based on NVD5.0. Re-arm the + * low-latency vector so it fires again for any event that latched + * while we were servicing. + */ + nvkm_wr32(disp->engine.subdev.device, 0x611f34, 0x00000001); + return ret; +} + static void r535_disp_fini(struct nvkm_disp *disp, bool suspend) { @@ -1568,7 +1609,9 @@ r535_disp_oneinit(struct nvkm_disp *disp) struct nvkm_device *device =3D disp->engine.subdev.device; struct nvkm_gsp *gsp =3D device->gsp; const struct nvkm_rm_api *rmapi =3D gsp->rm->api; + const struct nvkm_rm_gpu *gpu =3D gsp->rm->gpu; NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS *ctrl; + nvkm_inth_func intr_func; unsigned long mask; int ret, i; =20 @@ -1722,7 +1765,12 @@ r535_disp_oneinit(struct nvkm_disp *disp) nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl); =20 for_each_set_bit(i, &disp->head.mask, disp->head.nr) { - ret =3D nvkm_head_new_(&r535_head, disp, i); + const struct nvkm_head_func *func =3D &r535_head; + + if (gpu->disp.class.root >=3D GB202_DISP) + func =3D &gb202_head; + + ret =3D nvkm_head_new_(func, disp, i); if (ret) return ret; } @@ -1766,12 +1814,21 @@ r535_disp_oneinit(struct nvkm_disp *disp) if (ret) return ret; =20 - ret =3D nvkm_gsp_intr_stall(gsp, disp->engine.subdev.type, disp->engine.s= ubdev.inst); + if (gpu->disp.class.root >=3D GB202_DISP) { + /* GB20x deliver head-timing interrupts on the display's + * separate low-latency vector (interrupt table instance 1). + */ + ret =3D nvkm_gsp_intr_stall(gsp, disp->engine.subdev.type, 1); + intr_func =3D gb202_disp_intr; + } else { + ret =3D nvkm_gsp_intr_stall(gsp, disp->engine.subdev.type, disp->engine.= subdev.inst); + intr_func =3D r535_disp_intr; + } if (ret < 0) return ret; =20 ret =3D nvkm_inth_add(&device->vfn->intr, ret, NVKM_INTR_PRIO_NORMAL, &di= sp->engine.subdev, - r535_disp_intr, &disp->engine.subdev.inth); + intr_func, &disp->engine.subdev.inth); if (ret) return ret; =20 diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/gsp.c b/driver= s/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/gsp.c index 996941c668ba..2590b22663cb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/gsp.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/gsp.c @@ -44,6 +44,14 @@ r570_gsp_xlat_mc_engine_idx(u32 mc_engine_idx, enum nvkm= _subdev_type *ptype, int *ptype =3D NVKM_ENGINE_DISP; *pinst =3D 0; return true; + case MC_ENGINE_IDX_DISP_LOW: + /* GB20x+ report a separate low-latency display vector, used + * for head-timing interrupts. Expose it as a second DISP + * interrupt instance. + */ + *ptype =3D NVKM_ENGINE_DISP; + *pinst =3D 1; + return true; case MC_ENGINE_IDX_CE0 ... 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Fri, 14 Aug 2026 16:59:05 -0700 (PDT) Received: from fedora ([5.31.134.170]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499899753ccsm77751245e9.0.2026.08.14.16.59.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Aug 2026 16:59:04 -0700 (PDT) From: Mohamed Ahmed To: linux-kernel@vger.kernel.org Cc: dri-devel@lists.freedesktop.org, Lyude Paul , Danilo Krummrich , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Mary Guillemard , nouveau@lists.freedesktop.org, Mohamed Ahmed Subject: [PATCH 6/7] nouveau/dispnv50: program pixel clocks above 2.147GHz on GB20x Date: Sat, 15 Aug 2026 03:57:04 +0400 Message-ID: <20260814235705.59132-7-mohamedahmedegypt2001@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260814235705.59132-1-mohamedahmedegypt2001@gmail.com> References: <20260814235705.59132-1-mohamedahmedegypt2001@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The HEAD_SET_PIXEL_CLOCK_FREQUENCY(_MAX) methods carry only 31 HERTZ bits. Starting with C97D the upper bits live in separate HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI(_MAX) methods, which nouveau never programmed and headca7d_mode() computed m->clock * 1000 into the 31-bit field. NVVAL's mask then silently truncates anything past 2^31 Hz, which means that every mode scanned out at pclk modulo 2^31. No mode nouveau can currently commit crosses the boundary (an uncompressed HDMI FRL mode tops out around 1.78GHz at 8bpc), but this is a prerequisite for the upcoming DSC work, which makes 2.147GHz+ modes reachable. Program the full value split across the low and HI methods, exactly as OpenRM's EvoSetRasterParams9() does (nvkms-evo4.c, 31-bit low word plus the 4 HI HERTZ bits, giving 35 bits of range). Signed-off-by: Mohamed Ahmed --- drivers/gpu/drm/nouveau/dispnv50/headca7d.c | 21 ++++++++++++++++--- .../drm/nouveau/include/nvhw/class/clca7d.h | 4 ++++ 2 files changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/headca7d.c b/drivers/gpu/drm/= nouveau/dispnv50/headca7d.c index eeaeb15aa664..2046e38a4d79 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headca7d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headca7d.c @@ -219,10 +219,11 @@ headca7d_mode(struct nv50_head *head, struct nv50_hea= d_atom *asyh) { struct nvif_push *push =3D &head->disp->core->chan.push; struct nv50_head_mode *m =3D &asyh->mode; + const u64 hz =3D (u64)m->clock * 1000; const int i =3D head->base.index; int ret; =20 - ret =3D PUSH_WAIT(push, 11); + ret =3D PUSH_WAIT(push, 15); if (ret) return ret; =20 @@ -245,11 +246,25 @@ headca7d_mode(struct nv50_head *head, struct nv50_hea= d_atom *asyh) PUSH_MTHD(push, NVCA7D, HEAD_SET_CONTROL(i), NVDEF(NVCA7D, HEAD_SET_CONTROL, STRUCTURE, PROGRESSIVE)); =20 + /* The FREQUENCY methods carry only 31 HERTZ bits; the upper bits + * of anything past 2.147GHz live in the HI methods + * (EvoSetRasterParams9()). Truncation here scans out at pclk modulo 2^31. + */ PUSH_MTHD(push, NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i), - NVVAL(NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY, HERTZ, m->clock * 1000)); + NVVAL(NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY, HERTZ, + (u32)(hz & 0x7fffffff))); =20 PUSH_MTHD(push, NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i), - NVVAL(NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX, HERTZ, m->clock * 10= 00)); + NVVAL(NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX, HERTZ, + (u32)(hz & 0x7fffffff))); + + PUSH_MTHD(push, NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI(i), + NVVAL(NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI, HERTZ, + (u32)(hz >> 31))); + + PUSH_MTHD(push, NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI_MAX(i), + NVVAL(NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI_MAX, HERTZ, + (u32)(hz >> 31))); =20 return 0; } diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/clca7d.h b/drivers/= gpu/drm/nouveau/include/nvhw/class/clca7d.h index 0fec6fc21d44..1ab12d91c9d9 100644 --- a/drivers/gpu/drm/nouveau/include/nvhw/class/clca7d.h +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/clca7d.h @@ -653,6 +653,10 @@ #define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 = 31:31 #define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE = (0x00000000) #define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE = (0x00000001) +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI(a) = (0x000020C0 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI_HERTZ = 3:0 +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI_MAX(a) = (0x000020C4 + (a)*0x00000800) +#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI_MAX_HERTZ = 3:0 #define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS(a) = (0x00002030 + (a)*0x00000800) #define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR = 2:0 #define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_NONE = (0x00000000) --=20 2.55.0 From nobody Mon Sep 28 23:55:41 2026 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2C6E33937B for ; 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Fri, 14 Aug 2026 16:59:10 -0700 (PDT) Received: from fedora ([5.31.134.170]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499899753ccsm77751245e9.0.2026.08.14.16.59.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Aug 2026 16:59:10 -0700 (PDT) From: Mohamed Ahmed To: linux-kernel@vger.kernel.org Cc: dri-devel@lists.freedesktop.org, Lyude Paul , Danilo Krummrich , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Mary Guillemard , nouveau@lists.freedesktop.org, Mohamed Ahmed Subject: [PATCH 7/7] nouveau: honor HF-EEODB EDIDs by converting to struct drm_edid Date: Sat, 15 Aug 2026 03:57:05 +0400 Message-ID: <20260814235705.59132-8-mohamedahmedegypt2001@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260814235705.59132-1-mohamedahmedegypt2001@gmail.com> References: <20260814235705.59132-1-mohamedahmedegypt2001@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" HDMI 2.1 sinks ship HF-EEODB EDIDs. Byte 126 deliberately claims one extension block for legacy sources, and the true count lives in the CTA block's first data block. Their high-refresh timings (e.g., 4K240, 6K165, etc) sit in DisplayID extension blocks 2+. The kernel already reads these EDIDs whole, and on GSP boards RM returns the full EDID with its true size. However, nouveau then hands the buffer to the legacy API which sizes the EDID from byte 126 so the DisplayID blocks are not parsed/exposed and the sysfs blob truncates to 256 bytes. Convert to the struct drm_edid API, which carries the real size. Read via drm_edid_read_ddc()/drm_edid_read_switcheroo() where an adapter exists, and serve RM's buffer through drm_edid_read_custom() with a block-reading callback where not, which also routes the GSP path through drm's block validation and the debugfs EDID override (previously dead on GSP boards, since nothing consulted it outside the i2c readers). The connector keeps a borrowed const drm_edid_raw() view in ->edid, same as i915's detect_edid so the raw-EDID consumers (SAD parsing, deep-color flags, the DVI dual-link byte, DP CEC) are untouched. Ownership and freeing move to the drm_edid. The OF path additionally now frees any previous EDID itself rather than relying on the callers. MST connectors keep their separate legacy path. Signed-off-by: Mohamed Ahmed --- drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +- drivers/gpu/drm/nouveau/nouveau_connector.c | 95 ++++++++++++++++----- drivers/gpu/drm/nouveau/nouveau_connector.h | 7 +- 3 files changed, 80 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouv= eau/dispnv50/disp.c index 364227f5456f..c3b7fd29c077 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -1804,7 +1804,7 @@ nv50_sor_atomic_enable(struct drm_encoder *encoder, s= truct drm_atomic_commit *st lvds_8bpc =3D bios->fp.if_is_24bit; } else { if (nv_connector->type =3D=3D DCB_CONNECTOR_LVDS_SPWG) { - if (((u8 *)nv_connector->edid)[121] =3D=3D 2) + if (((const u8 *)nv_connector->edid)[121] =3D=3D 2) lvds_dual =3D true; } else if (mode->clock >=3D bios->fp.duallink_transition_clk) { diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/= nouveau/nouveau_connector.c index b0b0ad9a0c24..4105555151c9 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -397,7 +397,7 @@ nouveau_connector_destroy(struct drm_connector *connect= or) struct nouveau_connector *nv_connector =3D nouveau_connector(connector); nvif_event_dtor(&nv_connector->irq); nvif_event_dtor(&nv_connector->hpd); - kfree(nv_connector->edid); + drm_edid_free(nv_connector->drm_edid); drm_connector_unregister(connector); drm_connector_cleanup(connector); if (nv_connector->aux.transfer) @@ -490,8 +490,11 @@ nouveau_connector_of_detect(struct drm_connector *conn= ector) int idx =3D name ? name[strlen(name) - 1] - 'A' : 0; =20 if (nv_encoder->dcb->i2c_index =3D=3D idx && edid) { + drm_edid_free(nv_connector->drm_edid); + nv_connector->drm_edid =3D + drm_edid_alloc(edid, EDID_LENGTH); nv_connector->edid =3D - kmemdup(edid, EDID_LENGTH, GFP_KERNEL); + drm_edid_raw(nv_connector->drm_edid); return nv_encoder; } } @@ -546,17 +549,42 @@ nouveau_connector_set_encoder(struct drm_connector *c= onnector, } } =20 +struct nouveau_rm_edid { + u8 *data; + int size; +}; + +static int +nouveau_connector_rm_edid_block(void *context, u8 *buf, unsigned int block, + size_t len) +{ + struct nouveau_rm_edid *rm =3D context; + size_t offset =3D (size_t)block * EDID_LENGTH; + + if (offset + len > rm->size) + return -EINVAL; + + memcpy(buf, rm->data + offset, len); + return 0; +} + static void nouveau_connector_set_edid(struct nouveau_connector *nv_connector, - struct edid *edid) + const struct drm_edid *drm_edid) { - if (nv_connector->edid !=3D edid) { - struct edid *old_edid =3D nv_connector->edid; + if (nv_connector->drm_edid =3D=3D drm_edid) + return; =20 - drm_connector_update_edid_property(&nv_connector->base, edid); - kfree(old_edid); - nv_connector->edid =3D edid; - } + /* Updates the EDID property and display_info with HF-EEODB-aware + * sizing. The legacy helpers truncate both to what EDID byte 126 + * admits, hiding the DisplayID extension blocks that carry every + * timing a DTD can't express (>655.35 MHz). + */ + drm_edid_connector_update(&nv_connector->base, drm_edid); + + drm_edid_free(nv_connector->drm_edid); + nv_connector->drm_edid =3D drm_edid; + nv_connector->edid =3D drm_edid_raw(drm_edid); } =20 static enum drm_connector_status @@ -590,20 +618,36 @@ nouveau_connector_detect(struct drm_connector *connec= tor, bool force) =20 nv_encoder =3D nouveau_connector_ddc_detect(connector); if (nv_encoder) { - struct edid *new_edid =3D NULL; + const struct drm_edid *new_edid =3D NULL; =20 if (nv_encoder->i2c) { if ((vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) && nv_connector->type =3D=3D DCB_CONNECTOR_LVDS) - new_edid =3D drm_get_edid_switcheroo(connector, nv_encoder->i2c); + new_edid =3D drm_edid_read_switcheroo(connector, nv_encoder->i2c); else - new_edid =3D drm_get_edid(connector, nv_encoder->i2c); + new_edid =3D drm_edid_read_ddc(connector, nv_encoder->i2c); } else { - ret =3D nvif_outp_edid_get(&nv_encoder->outp, (u8 **)&new_edid); + struct nouveau_rm_edid rm =3D {}; + + ret =3D nvif_outp_edid_get(&nv_encoder->outp, &rm.data); if (ret < 0) return connector_status_disconnected; + + /* ret is RM's true buffer size: an HF-EEODB EDID is + * larger than its byte 126 admits, and RM (which + * owns the DDC pads on GSP boards) reads it whole. + * Serve it through drm's block reader so EEODB + * sizing, block validation, and the debugfs EDID + * override all apply. + */ + rm.size =3D ret; + new_edid =3D drm_edid_read_custom(connector, + nouveau_connector_rm_edid_block, + &rm); + kfree(rm.data); } =20 + nouveau_connector_set_edid(nv_connector, new_edid); if (!nv_connector->edid) { NV_ERROR(drm, "DDC responded, but no EDID for %s\n", @@ -686,7 +730,7 @@ nouveau_connector_detect_lvds(struct drm_connector *con= nector, bool force) struct nouveau_drm *drm =3D nouveau_drm(dev); struct nouveau_connector *nv_connector =3D nouveau_connector(connector); struct nouveau_encoder *nv_encoder =3D NULL; - struct edid *edid =3D NULL; + const struct drm_edid *edid =3D NULL; enum drm_connector_status status =3D connector_status_disconnected; =20 nv_encoder =3D find_encoder(connector, DCB_OUTPUT_LVDS); @@ -697,7 +741,7 @@ nouveau_connector_detect_lvds(struct drm_connector *con= nector, bool force) if (!drm->vbios.fp_no_ddc) { status =3D nouveau_connector_detect(connector, force); if (status =3D=3D connector_status_connected) { - edid =3D nv_connector->edid; + edid =3D nv_connector->drm_edid; goto out; } } @@ -712,7 +756,13 @@ nouveau_connector_detect_lvds(struct drm_connector *co= nnector, bool force) * valid - it's not (rh#613284) */ if (nv_encoder->dcb->lvdsconf.use_acpi_for_edid) { - edid =3D nouveau_acpi_edid(dev, connector); + struct edid *raw =3D nouveau_acpi_edid(dev, connector); + + if (raw) { + edid =3D drm_edid_alloc(raw, + EDID_LENGTH * (1 + raw->extensions)); + kfree(raw); + } if (edid) { status =3D connector_status_connected; goto out; @@ -733,9 +783,10 @@ nouveau_connector_detect_lvds(struct drm_connector *co= nnector, bool force) * stored for the panel stored in them. */ if (!drm->vbios.fp_no_ddc) { - edid =3D (struct edid *)nouveau_bios_embedded_edid(dev); - if (edid) { - edid =3D kmemdup(edid, EDID_LENGTH, GFP_KERNEL); + const void *embedded =3D nouveau_bios_embedded_edid(dev); + + if (embedded) { + edid =3D drm_edid_alloc(embedded, EDID_LENGTH); if (edid) status =3D connector_status_connected; } @@ -915,7 +966,7 @@ nouveau_connector_detect_depth(struct drm_connector *co= nnector) */ if (nv_connector->edid && nv_connector->type =3D=3D DCB_CONNECTOR_LVDS_SPWG) - duallink =3D ((u8 *)nv_connector->edid)[121] =3D=3D 2; + duallink =3D ((const u8 *)nv_connector->edid)[121] =3D=3D 2; else duallink =3D mode->clock >=3D bios->fp.duallink_transition_clk; =20 @@ -973,8 +1024,8 @@ nouveau_connector_get_modes(struct drm_connector *conn= ector) nv_connector->native_mode =3D NULL; } =20 - if (nv_connector->edid) - ret =3D drm_add_edid_modes(connector, nv_connector->edid); + if (nv_connector->drm_edid) + ret =3D drm_edid_connector_add_modes(connector); else if (nv_encoder->dcb->type =3D=3D DCB_OUTPUT_LVDS && (nv_encoder->dcb->lvdsconf.use_straps_for_mode || diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.h b/drivers/gpu/drm/= nouveau/nouveau_connector.h index 0608cabed058..ca8f310b3680 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.h +++ b/drivers/gpu/drm/nouveau/nouveau_connector.h @@ -137,7 +137,12 @@ struct nouveau_connector { int scaling_mode; =20 struct nouveau_encoder *detected_encoder; - struct edid *edid; + /* Borrowed decoded view of ->drm_edid for the raw-EDID consumers + * (SADs, deep-colour flags, dual-link byte); do not free. + */ + const struct edid *edid; + /* Owner of the sink's EDID, HF-EEODB-complete. */ + const struct drm_edid *drm_edid; struct drm_display_mode *native_mode; #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT struct nouveau_backlight *backlight; --=20 2.55.0