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Fri, 14 Aug 2026 06:42:02 -0700 (PDT) Received: from haichao.tail057a43.ts.net ([2001:da8:e000:1206:e9af:7c0e:be31:2c3f]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-394ea972c79sm2932232a91.4.2026.08.14.06.41.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Aug 2026 06:42:02 -0700 (PDT) From: Ruoyu Wang To: Michael Turquette , Stephen Boyd , Matthias Brugger , AngeloGioacchino Del Regno , Rob Herring , Wenzhen Yu , Ryder Lee Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Ruoyu Wang Subject: [PATCH v2] clk: mediatek: mt7629: Properly use CLK_IS_CRITICAL flag Date: Fri, 14 Aug 2026 21:41:56 +0800 Message-ID: <20260814134156.1388413-1-ruoyuw560@gmail.com> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT7629 clock driver calls clk_prepare_enable() for six clocks that must remain running. These calls create permanent references owned by the driver. In topckgen and apmixedsys, provider registration can fail after the references are acquired, leaving them unreleased. Mark ARMPLL, main_core_en, the AXI, memory and DDRPHY selectors, and the UART0 gate with CLK_IS_CRITICAL, and remove the manual enable calls. Keep CLK_SET_RATE_PARENT on the three muxes while adding the critical flag. The common clock framework then preserves the existing always-on behavior without driver-owned prepare and enable references. This issue was found by a static analysis checker and confirmed by manual source review. Fixes: 3b5e748615e7 ("clk: mediatek: add clock support for MT7629 SoC") Signed-off-by: Ruoyu Wang --- Changes in v2: - Preserve CLK_SET_RATE_PARENT on the AXI, memory and DDRPHY muxes. - Rebase onto clk-next and repeat the focused ARM W=3D1 build. v1: https://lore.kernel.org/r/20260813153113.3952621-1-ruoyuw560@gmail.com/ drivers/clk/mediatek/clk-mt7629.c | 39 +++++++++++++++---------------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-m= t7629.c index e154771b1b8bb..1a3abffd3238f 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -48,8 +48,9 @@ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ NULL, "clk20m") =20 -#define GATE_APMIXED(_id, _name, _parent, _shift) \ - GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops= _no_setclr_inv) +#define GATE_APMIXED_AO(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, _shift, \ + &mtk_clk_gate_ops_no_setclr_inv, CLK_IS_CRITICAL) =20 #define GATE_INFRA(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) @@ -57,6 +58,10 @@ #define GATE_PERI0(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 +#define GATE_PERI0_AO(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &peri0_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_IS_CRITICAL) + #define GATE_PERI1(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 @@ -311,7 +316,7 @@ static const struct mtk_gate_regs peri1_cg_regs =3D { =20 static const struct mtk_pll_data plls[] =3D { PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0, - 0, 21, 0x0204, 24, 0, 0x0204, 0), + PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0), PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0, HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0), PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0, @@ -325,7 +330,7 @@ static const struct mtk_pll_data plls[] =3D { }; =20 static const struct mtk_gate apmixed_clks[] =3D { - GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5), + GATE_APMIXED_AO(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5), }; =20 static const struct mtk_gate infra_clks[] =3D { @@ -437,7 +442,7 @@ static const struct mtk_gate peri_clks[] =3D { GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "pwm_qtr_26m", 9), GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "faxi", 12), GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1", 14), - GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "faxi", 17), + GATE_PERI0_AO(CLK_PERI_UART0_PD, "peri_uart0_pd", "faxi", 17), GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "faxi", 18), GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "faxi", 19), GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "faxi", 20), @@ -459,12 +464,15 @@ static struct mtk_composite infra_muxes[] =3D { =20 static struct mtk_composite top_muxes[] =3D { /* CLK_CFG_0 */ - MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, - 0x040, 0, 3, 7), - MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, - 0x040, 8, 1, 15), - MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, - 0x040, 16, 1, 23), + MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, + 0x040, 0, 3, 7, + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), + MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, + 0x040, 8, 1, 15, + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), + MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, + 0x040, 16, 1, 23, + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 0x040, 24, 3, 31), /* CLK_CFG_1 */ @@ -568,10 +576,6 @@ static int mtk_topckgen_init(struct platform_device *p= dev) ARRAY_SIZE(top_muxes), base, &mt7629_clk_lock, clk_data); =20 - clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk); - clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk); - clk_prepare_enable(clk_data->hws[CLK_TOP_DDRPHYCFG_SEL]->clk); - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } =20 @@ -620,8 +624,6 @@ static int mtk_pericfg_init(struct platform_device *pde= v) if (r) return r; =20 - clk_prepare_enable(clk_data->hws[CLK_PERI_UART0_PD]->clk); - return 0; } =20 @@ -640,9 +642,6 @@ static int mtk_apmixedsys_init(struct platform_device *= pdev) mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); =20 - clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk); - clk_prepare_enable(clk_data->hws[CLK_APMIXED_MAIN_CORE_EN]->clk); - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } =20 base-commit: 684633bd76956b5d7ed59eb799e6fe7f45e47be4 --=20 2.51.0