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Fri, 14 Aug 2026 06:41:49 -0700 (PDT) Received: from haichao.tail057a43.ts.net ([2001:da8:e000:1206:e9af:7c0e:be31:2c3f]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-394ebb888e3sm2750835a91.11.2026.08.14.06.41.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Aug 2026 06:41:49 -0700 (PDT) From: Ruoyu Wang To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Thierry Reding , Laurent Pinchart , Axel Lin Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Ruoyu Wang Subject: [PATCH] pwm: renesas-tpu: Fix runtime PM reference leak Date: Fri, 14 Aug 2026 21:41:43 +0800 Message-ID: <20260814134143.1388120-1-ruoyuw560@gmail.com> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" tpu_pwm_timer_start() used pm_runtime_get_sync() without checking its return value before touching the TPU clock. A failed runtime resume was therefore ignored, and the callback continued into register access. Use pm_runtime_resume_and_get() and propagate a failed resume. Keep the matching put when clock preparation fails after a successful resume. tpu_pwm_disable() also needs to propagate a failed start so that the PWM apply callback does not access registers while runtime PM is inactive. This issue was found by a static analysis checker and confirmed by manual source review. Fixes: 99b82abb0a35 ("pwm: Add Renesas TPU PWM driver") Signed-off-by: Ruoyu Wang --- drivers/pwm/pwm-renesas-tpu.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-renesas-tpu.c b/drivers/pwm/pwm-renesas-tpu.c index 2196080b41770..c0bbe275275c8 100644 --- a/drivers/pwm/pwm-renesas-tpu.c +++ b/drivers/pwm/pwm-renesas-tpu.c @@ -149,10 +149,14 @@ static int tpu_pwm_timer_start(struct tpu_pwm_device = *tpd) =20 if (!tpd->timer_on) { /* Wake up device and enable clock. */ - pm_runtime_get_sync(&tpd->tpu->pdev->dev); + ret =3D pm_runtime_resume_and_get(&tpd->tpu->pdev->dev); + if (ret < 0) + return ret; + ret =3D clk_prepare_enable(tpd->tpu->clk); if (ret) { dev_err(&tpd->tpu->pdev->dev, "cannot enable clock\n"); + pm_runtime_put(&tpd->tpu->pdev->dev); return ret; } tpd->timer_on =3D true; @@ -382,15 +386,21 @@ static int tpu_pwm_enable(struct pwm_chip *chip, stru= ct pwm_device *pwm) return 0; } =20 -static void tpu_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +static int tpu_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) { struct tpu_device *tpu =3D to_tpu_device(chip); struct tpu_pwm_device *tpd =3D &tpu->tpd[pwm->hwpwm]; + int ret; =20 /* The timer must be running to modify the pin output configuration. */ - tpu_pwm_timer_start(tpd); + ret =3D tpu_pwm_timer_start(tpd); + if (ret < 0) + return ret; + tpu_pwm_set_pin(tpd, TPU_PIN_INACTIVE); tpu_pwm_timer_stop(tpd); + + return 0; } =20 static int tpu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, @@ -401,7 +411,10 @@ static int tpu_pwm_apply(struct pwm_chip *chip, struct= pwm_device *pwm, =20 if (state->polarity !=3D pwm->state.polarity) { if (enabled) { - tpu_pwm_disable(chip, pwm); + err =3D tpu_pwm_disable(chip, pwm); + if (err) + return err; + enabled =3D false; } =20 @@ -412,7 +425,7 @@ static int tpu_pwm_apply(struct pwm_chip *chip, struct = pwm_device *pwm, =20 if (!state->enabled) { if (enabled) - tpu_pwm_disable(chip, pwm); + return tpu_pwm_disable(chip, pwm); =20 return 0; } --=20 2.51.0