From nobody Tue Sep 29 00:30:54 2026 Received: from mta0.migadu.com (out-204.mta0.migadu.com [91.218.175.204]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 479AA33A6E9 for ; Fri, 14 Aug 2026 11:45:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.204 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786707956; cv=none; b=bP91mw2pMHX05MACufwhloraruy7CVDOQV2Yl2Cace0Qo2B8oXojfGPb7+1mhe0cNTveP/cpfV0gEDN/5S67mdybyz+y2/l6R7ye78Vxvr58NVJcokKXFQLUrZzkLmi1R5pWQfAzL8BH30oXcWoiLz7V2elqikaUZNtI73Bi6jM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786707956; c=relaxed/simple; bh=NElRwhKXJKskKs7L0lwTCSgGuGKP1HD6hmKGJ40v/N0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZItkMoE4Ru+iVo6US9Fay9ez5DIRrbyrPWHIP5GoK0fjS7B1mApA6++APuwcqEzgWNEREy9V3ML8ziXEoBiHuO/4MyUv5nF9PW5iLC9ElmIhHwlpdybvbOI4QsbBLKesdGM7ImU51miM+KAxTEc3yY61iZbVJi9aldpQsfyNeRM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=q+o6IG4A; arc=none smtp.client-ip=91.218.175.204 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="q+o6IG4A" X-Envelope-To: linux-kernel@vger.kernel.org DKIM-Signature: a=rsa-sha256; bh=NElRwhKXJKskKs7L0lwTCSgGuGKP1HD6hmKGJ40v/N0=; c=simple/simple; d=linux.dev; h=from:to:subject:date:message-id:mime-version:content-type; s=key1; t=1786707953; v=1; x=1787312753; b=q+o6IG4AvlFRhAXBwBrDK0GUiZbfDHME/P9E/gOjY++OULnL/qxlQbtzV5j2ep91+Sc3qHap X8nreY0E6I5pPDWCUYSV2MidnZaWyF3d4GgSbY0SOIZcWRmHJuSmELsjUnOQjPS91TJVkSq4fpC d5xzmORm7IMjLgGJF2p9T46U= X-Envelope-To: linux-kernel@vger.kernel.org Received: from localhost.localdomain (2408:823d:2011:2c0:e810:54f9:f0a3:99d) by smtp.migadu.com with ESMTPS id 7749c2dafb5b1cfd; Fri, 14 Aug 2026 11:45:43 +0000 X-Migadu-Flow: FLOW_OUT From: Jinyu Tang To: Anup Patel , Anup Patel , Sean Christopherson Cc: Paolo Bonzini , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Atish Patra , Paul Walmsley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Andrew Jones , Conor Dooley , Yong-Xuan Wang , Nutty Liu , Jinyu Tang , Jinyu Tang Subject: [PATCH v3 1/3] KVM: riscv: Implement KVM_PRE_FAULT_MEMORY Date: Fri, 14 Aug 2026 07:45:05 -0400 Message-ID: <20260814114507.583424-2-jinyu.tang@linux.dev> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260814114507.583424-1-jinyu.tang@linux.dev> References: <20260814114507.583424-1-jinyu.tang@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The generic KVM_PRE_FAULT_MEMORY ioctl lets userspace populate KVM page tables before running a vCPU over a GPA range. x86 already supports the ioctl, but RISC-V does not expose the capability and has no arch hook. Add the RISC-V arch hook and reuse the existing G-stage fault mapping path with a read access. Report progress using the G-stage mapping returned by the map path, so the ioctl can advance by the actual leaf size that covers the requested GPA. Retry until a mapping is installed or a signal, VM-dead request, or real error is observed. Signed-off-by: Jinyu Tang --- v2 -> v3: - Retry internally when the map path returns success without a visible G-stage mapping, instead of exposing -EAGAIN. (Sashiko) arch/riscv/kvm/Kconfig | 1 + arch/riscv/kvm/gstage.c | 3 +++ arch/riscv/kvm/mmu.c | 42 +++++++++++++++++++++++++++++++++++++++++ arch/riscv/kvm/vm.c | 1 + 4 files changed, 47 insertions(+) diff --git a/arch/riscv/kvm/Kconfig b/arch/riscv/kvm/Kconfig index ec2cee0a39e0..8ac209e8ac87 100644 --- a/arch/riscv/kvm/Kconfig +++ b/arch/riscv/kvm/Kconfig @@ -28,6 +28,7 @@ config KVM select KVM_COMMON select KVM_GENERIC_DIRTYLOG_READ_PROTECT select KVM_GENERIC_HARDWARE_ENABLING + select KVM_GENERIC_PRE_FAULT_MEMORY select KVM_MMIO select VIRT_XFER_TO_GUEST_WORK select SCHED_INFO diff --git a/arch/riscv/kvm/gstage.c b/arch/riscv/kvm/gstage.c index e5002cb9cbef..6bd8b8fd6ceb 100644 --- a/arch/riscv/kvm/gstage.c +++ b/arch/riscv/kvm/gstage.c @@ -280,6 +280,9 @@ int kvm_riscv_gstage_map_page(struct kvm_gstage *gstage, out_map->level, true); } else if (ALIGN_DOWN(PFN_PHYS(pte_pfn(ptep_get(ptep))), page_size) =3D= =3D hpa) { kvm_riscv_gstage_update_pte_prot(gstage, ptep_level, gpa, ptep, prot); + out_map->addr =3D ALIGN_DOWN(gpa, page_size); + out_map->level =3D ptep_level; + out_map->pte =3D ptep_get(ptep); return 0; } } diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c index 6035b5ec9503..33d4ba406b0d 100644 --- a/arch/riscv/kvm/mmu.c +++ b/arch/riscv/kvm/mmu.c @@ -748,6 +748,48 @@ int kvm_riscv_mmu_map(struct kvm_vcpu *vcpu, struct kv= m_memory_slot *memslot, return ret; } =20 +long kvm_arch_vcpu_pre_fault_memory(struct kvm_vcpu *vcpu, + struct kvm_pre_fault_memory *range) +{ + struct kvm_gstage_mapping out_map =3D { 0 }; + struct kvm_memory_slot *memslot; + unsigned long map_size; + unsigned long hva; + gpa_t end; + gfn_t gfn; + int ret; + + gfn =3D gpa_to_gfn(range->gpa); + memslot =3D kvm_vcpu_gfn_to_memslot(vcpu, gfn); + if (!memslot) + return -ENOENT; + + hva =3D gfn_to_hva_memslot_prot(memslot, gfn, NULL); + if (kvm_is_error_hva(hva)) + return -ENOENT; + + for (;;) { + if (signal_pending(current)) + return -EINTR; + + if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) + return -EIO; + + cond_resched(); + ret =3D kvm_riscv_mmu_map(vcpu, memslot, range->gpa, hva, false, &out_ma= p); + if (ret) + return ret; + + if (pte_val(out_map.pte)) + break; + } + + map_size =3D PAGE_SIZE << (out_map.level * kvm_riscv_gstage_index_bits); + end =3D ALIGN_DOWN(range->gpa, map_size) + map_size; + + return min_t(u64, range->size, end - range->gpa); +} + int kvm_riscv_mmu_alloc_pgd(struct kvm *kvm) { struct page *pgd_page; diff --git a/arch/riscv/kvm/vm.c b/arch/riscv/kvm/vm.c index a9f083feeb76..58500a19b33b 100644 --- a/arch/riscv/kvm/vm.c +++ b/arch/riscv/kvm/vm.c @@ -187,6 +187,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long = ext) case KVM_CAP_MP_STATE: case KVM_CAP_IMMEDIATE_EXIT: case KVM_CAP_SET_GUEST_DEBUG: + case KVM_CAP_PRE_FAULT_MEMORY: r =3D 1; break; case KVM_CAP_NR_VCPUS: --=20 2.43.0 From nobody Tue Sep 29 00:30:54 2026 Received: from mta1.migadu.com (out-56.mta1.migadu.com [95.215.58.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51AD733A6E9 for ; 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charset="utf-8" RISC-V selftests can create guests with five page-table levels, for example when the selected guest mode is Sv57. The RISC-V page-table walker only had index arrays for levels 0 through 3, so virt_arch_pg_map() indexed past the end of the arrays when level 4 was used. Add the missing L4 index mask and shift so selftests can build guest page tables for Sv57 VMs. Reviewed-by: Nutty Liu Signed-off-by: Jinyu Tang --- tools/testing/selftests/kvm/include/riscv/processor.h | 3 +++ tools/testing/selftests/kvm/lib/riscv/processor.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/= testing/selftests/kvm/include/riscv/processor.h index e3acf2ae9881..abde3c71c891 100644 --- a/tools/testing/selftests/kvm/include/riscv/processor.h +++ b/tools/testing/selftests/kvm/include/riscv/processor.h @@ -127,6 +127,9 @@ void vm_install_exception_handler(struct kvm_vm *vm, in= t vector, exception_handl =20 void vm_install_interrupt_handler(struct kvm_vm *vm, exception_handler_fn = handler); =20 +/* L4 index Bit[56:48] */ +#define PGTBL_L4_INDEX_MASK 0x01FF000000000000ULL +#define PGTBL_L4_INDEX_SHIFT 48 /* L3 index Bit[47:39] */ #define PGTBL_L3_INDEX_MASK 0x0000FF8000000000ULL #define PGTBL_L3_INDEX_SHIFT 39 diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/test= ing/selftests/kvm/lib/riscv/processor.c index ded5429f3448..b4d41a407553 100644 --- a/tools/testing/selftests/kvm/lib/riscv/processor.c +++ b/tools/testing/selftests/kvm/lib/riscv/processor.c @@ -43,6 +43,7 @@ static u64 pte_index_mask[] =3D { PGTBL_L1_INDEX_MASK, PGTBL_L2_INDEX_MASK, PGTBL_L3_INDEX_MASK, + PGTBL_L4_INDEX_MASK, }; =20 static u32 pte_index_shift[] =3D { @@ -50,6 +51,7 @@ static u32 pte_index_shift[] =3D { PGTBL_L1_INDEX_SHIFT, PGTBL_L2_INDEX_SHIFT, PGTBL_L3_INDEX_SHIFT, + PGTBL_L4_INDEX_SHIFT, }; =20 static u64 pte_index(struct kvm_vm *vm, gva_t gva, int level) --=20 2.43.0 From nobody Tue Sep 29 00:30:54 2026 Received: from mta1.migadu.com (out-115.mta1.migadu.com [95.215.58.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5E5D463B87 for ; Fri, 14 Aug 2026 11:46:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.115 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786707982; cv=none; b=NZUIQYPsBBjBzAWA8pp2UJu/OrHVRNMJ00F+65qulkei2oomCKoqRf5h+2LwZtfQc2Ebi+FZkpFZDkmyk2XZqbPLnpHMU0LEVrajtUPXVHeMH89nyS6CmOQkYMoQNWPfywBichRF8Uv/JWPcoDB8wmAwXpgNWKbTtZqC1oAtKYM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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bh=DWVWKUddK6cm3cADsjGMhQ+YmtUIIGHlVIpbg6PZ+20=; c=simple/simple; d=linux.dev; h=from:to:subject:date:message-id:mime-version:content-type; s=key1; t=1786707976; v=1; x=1787312776; b=Mgnu+qNy6Iz1+MR4NJ3XFgkQrO+0DMir9y68GygGO3dLVzA4wXNxxBZvwKYpt0RCeNRHwlJT rb58ufnUyi92xEHdQZG1Ihp4Lsr1PG3gwwNfONEa9FAeZk1dEo7qMC6X6UzRDsD7JphP2h/ZL0Y 3XYwncCQ/OtG3UH5it9772xY= X-Envelope-To: linux-kernel@vger.kernel.org Received: from localhost.localdomain (2408:823d:2011:2c0:e810:54f9:f0a3:99d) by smtp.migadu.com with ESMTPS id f255273505126e07; Fri, 14 Aug 2026 11:46:13 +0000 X-Migadu-Flow: FLOW_OUT From: Jinyu Tang To: Anup Patel , Anup Patel , Sean Christopherson Cc: Paolo Bonzini , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Atish Patra , Paul Walmsley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Andrew Jones , Conor Dooley , Yong-Xuan Wang , Nutty Liu , Jinyu Tang , Jinyu Tang Subject: [PATCH v3 3/3] KVM: selftests: Enable pre_fault_memory_test for RISC-V Date: Fri, 14 Aug 2026 07:45:07 -0400 Message-ID: <20260814114507.583424-4-jinyu.tang@linux.dev> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260814114507.583424-1-jinyu.tang@linux.dev> References: <20260814114507.583424-1-jinyu.tang@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RISC-V now supports KVM_PRE_FAULT_MEMORY, so include the generic pre_fault_memory_test in the RISC-V KVM selftest build. The test uses PAGE_SIZE from the architecture processor header. Define the normal 4K RISC-V selftest page size so the generic test can build for RISC-V. Reviewed-by: Nutty Liu Signed-off-by: Jinyu Tang --- v1 -> v2: - Drop the per-test guest_modes_append_default() call from pre_fault_memory_test.c. RISC-V already initializes supported and default guest modes from kvm_selftest_arch_init(), which is called by the common kvm_selftest_init() constructor, as suggested by Sean. tools/testing/selftests/kvm/Makefile.kvm | 1 + tools/testing/selftests/kvm/include/riscv/processor.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/tools/testing/selftests/kvm/Makefile.kvm b/tools/testing/selft= ests/kvm/Makefile.kvm index 6fc34e9bf8e1..ac64ac92fd4b 100644 --- a/tools/testing/selftests/kvm/Makefile.kvm +++ b/tools/testing/selftests/kvm/Makefile.kvm @@ -225,6 +225,7 @@ TEST_GEN_PROGS_riscv +=3D coalesced_io_test TEST_GEN_PROGS_riscv +=3D dirty_log_perf_test TEST_GEN_PROGS_riscv +=3D get-reg-list TEST_GEN_PROGS_riscv +=3D mmu_stress_test +TEST_GEN_PROGS_riscv +=3D pre_fault_memory_test TEST_GEN_PROGS_riscv +=3D rseq_test TEST_GEN_PROGS_riscv +=3D steal_time =20 diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/= testing/selftests/kvm/include/riscv/processor.h index abde3c71c891..70487c8ed155 100644 --- a/tools/testing/selftests/kvm/include/riscv/processor.h +++ b/tools/testing/selftests/kvm/include/riscv/processor.h @@ -12,6 +12,9 @@ #include #include "kvm_util.h" =20 +#define PAGE_SHIFT 12 +#define PAGE_SIZE BIT_ULL(PAGE_SHIFT) + #define INSN_OPCODE_MASK 0x007c #define INSN_OPCODE_SHIFT 2 #define INSN_OPCODE_SYSTEM 28 --=20 2.43.0