From nobody Tue Sep 29 00:33:20 2026 Received: from mta-64-226.siemens.flowmailer.net (mta-64-226.siemens.flowmailer.net [185.136.64.226]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA53B4582D1 for ; Fri, 14 Aug 2026 09:19:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.136.64.226 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786699167; cv=none; b=i8cShbQcmqmfXKBTuHo76zx9N0xdt++lgfhMZycwULKIUwV7uHs5U30S88+m10DK84JpHHpfu+zg7VF2ekuWDgVxKoRLFN29vcFYmQw6wQkEN7AzXl8j7UJBg1FMUNRtqctCJgrFPsRoDcL/rlW8Iia733uvKUn2Ls9/LpxArj8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786699167; c=relaxed/simple; bh=wFOJGu0UcuBUmUcbX+jWOx9GxjPqzlP3B2t1idchaHw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gVS8CNda8gzmbeGipVTpQ/JcuHuB4jXi0wXo0yiDAgUpsH4jQAzpf6Bm10gXnf2ckBP5fRrZyVAcuDbisw34pAZZHdV4cqN6WJRxHulHyupZ/gT0VFQtxFdzHdnb+j+TcmhpYrZNjZ0NbPscrH/8cr+r/fnfuWaH2+UdrGToibU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com; dkim=pass (2048-bit key) header.d=siemens.com header.i=alexander.sverdlin@siemens.com header.b=LFdHQEFD; arc=none smtp.client-ip=185.136.64.226 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=siemens.com header.i=alexander.sverdlin@siemens.com header.b="LFdHQEFD" Received: by mta-64-226.siemens.flowmailer.net with ESMTPSA id 202608140909103ef5f4a35c000207f6 for ; Fri, 14 Aug 2026 11:09:10 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm2; d=siemens.com; i=alexander.sverdlin@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=pEAWZMUCnZp1tau2mG/PHGMRuIUt+oO0/JiRyASXCtg=; b=LFdHQEFDUTsy9clQdzxNN3VtB3DUnvu1rePp6wmNr2syJu3qs/TojC3ilL6l3VqCMCILnw L7MnxHTK3m89bqzitvYKxLgKqJlmOobg7/7+2pO7Tgb6WKtB3Aby9vkpg96y8u7mGtObo/Rx esPt0htQrs0ijpDd1FGRNZL2EQvHKC6q9A6iM27B9bSaepS4JVx/Unoq7Nzj723pI6Mxey1e 8DL5Ac4cmnDDoebF1lmzSsgs6VdWT7DplYJ1uMjWJqEdB7JDvHBb3RaSr/FFsEdu16ejAPLO auV33AXlSmR4+BjkfHaEB/KrAcXKVikWOpQFszkwrSZSu845sIZfYFxQ==; From: "A. Sverdlin" To: netdev@vger.kernel.org Cc: Alexander Sverdlin , Wei Fang , Frank Li , Shenwei Wang , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Linux Team , imx@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 1/2] dt-bindings: net: fsl,fec: add fsl,rx-flush-queues Date: Fri, 14 Aug 2026 11:09:00 +0200 Message-ID: <20260814090906.2225075-2-alexander.sverdlin@siemens.com> In-Reply-To: <20260814090906.2225075-1-alexander.sverdlin@siemens.com> References: <20260814090906.2225075-1-alexander.sverdlin@siemens.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-456497:519-21489:flowmailer Content-Type: text/plain; charset="utf-8" From: Alexander Sverdlin The FEC/ENET controller can enable receive flushing per RX queue via the QOS Scheme register (RX_FLUSHn bits). When enabled, a frame at the head of the RX FIFO that cannot be forwarded (because its ring has no empty buffer descriptor) is discarded instead of blocking the FIFO. Add the fsl,rx-flush-queues property to describe the set of RX queues for which flushing is enabled. Most controllers are subject to erratum ERR050395 and support flushing on a single queue only; the driver enforces that constraint, so keep the binding generic to allow future controllers with the erratum fixed to enable flushing on several queues. Signed-off-by: Alexander Sverdlin --- .../devicetree/bindings/net/fsl,fec.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/net/fsl,fec.yaml b/Documenta= tion/devicetree/bindings/net/fsl,fec.yaml index 24e863fdbdab0..808aaf3fd9f27 100644 --- a/Documentation/devicetree/bindings/net/fsl,fec.yaml +++ b/Documentation/devicetree/bindings/net/fsl,fec.yaml @@ -162,6 +162,20 @@ properties: Should specify the rx queue number, otherwise set rx queue number to= 1. enum: [1, 2, 3] =20 + fsl,rx-flush-queues: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 3 + items: + enum: [0, 1, 2] + description: + List of RX queue indices for which the receive flushing feature (QOS + Scheme register RX_FLUSHn) is enabled. When enabled, a frame at the = head + of the RX FIFO that cannot be forwarded (because its ring has no emp= ty + buffer descriptor) is discarded instead of blocking the FIFO. On most + controllers erratum ERR050395 restricts flushing to a single queue. = If + absent, RX flushing is disabled for all queues. + fsl,magic-packet: $ref: /schemas/types.yaml#/definitions/flag description: --=20 2.55.0 From nobody Tue Sep 29 00:33:20 2026 Received: from mta-64-227.siemens.flowmailer.net (mta-64-227.siemens.flowmailer.net [185.136.64.227]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24408459ADC for ; Fri, 14 Aug 2026 09:09:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.136.64.227 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786698565; cv=none; b=m3vE8Z9gmibDxYpyfUpcEbbSHPJIDBQH9uSSUdMBgW0EQtBhhJKv6TlRHth1wBY5yWyKE9SVcVHjHicgcL8pv2glxeIn6+PzNdUgm8yUhlLQ1fkj7FZaFwtH1GtvGZN2wx4Uud8qYvz5eKQ74R+FfPBytRhbpsYmnLvhzdzGUc4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786698565; c=relaxed/simple; bh=JmT62r1LQFUMewiOjNoxJSZLjb5Rke2Ty3fgGYMzUjM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=icmvfXpqnu97IuLWgTNG2xnD75kdq7+7kkTpmdvEpcE8jn2rD3Gj1aR9i5kPvepuPp5sR3Th2CRxPdwY494cJzxGFGM2LnzwAea4w1F4t/d/FH4ArYLoBQPBQCVyQtQfFrv8+PMAyBTnk8o9Q4/naK4a7R4JSuu9kZiljKGWynU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com; dkim=pass (2048-bit key) header.d=siemens.com header.i=alexander.sverdlin@siemens.com header.b=aFQbwDBU; arc=none smtp.client-ip=185.136.64.227 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=siemens.com header.i=alexander.sverdlin@siemens.com header.b="aFQbwDBU" Received: by mta-64-227.siemens.flowmailer.net with ESMTPSA id 20260814090911cb50b2fe9800020737 for ; Fri, 14 Aug 2026 11:09:11 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm2; d=siemens.com; i=alexander.sverdlin@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=WMBYKt6pXyX/he4h/0lqd2dFpbK1SOcahc23JBZCrXA=; b=aFQbwDBUcXsjxrjR8In9gObCKyk903HbObS6ctu+LEEll4GHW3elsYUCydAboMMbBzV7Bu mfUOCTgmQcCoiNpLcqqoXbfDV04op8pXs8d2JBgAHBvog7K7t3zzGahO7GvZfXe2tbYkgnUH RPlEIqQI9JfWX3Ri6wEtJGvqwZi+6tAEiQrUfqAWF9ikIm4zXRccK09Gq8h9OvUU6BTBT8AF VhzdVsX8SNKgMRrsz66YULWck4n1nT7aH/8pfrSq+oX5Eg0fy7c3cbOFSP/aM9iLIQ7K5UP+ q0hjdJsWV5i6ceaoQry7XxIYENBYFqCx0ZwMb9Y+uQTqEBvndaiNviGg==; From: "A. Sverdlin" To: netdev@vger.kernel.org Cc: Alexander Sverdlin , Wei Fang , Frank Li , Shenwei Wang , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Linux Team , imx@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 2/2] net: fec: support receive flushing via fsl,rx-flush-queues Date: Fri, 14 Aug 2026 11:09:01 +0200 Message-ID: <20260814090906.2225075-3-alexander.sverdlin@siemens.com> In-Reply-To: <20260814090906.2225075-1-alexander.sverdlin@siemens.com> References: <20260814090906.2225075-1-alexander.sverdlin@siemens.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-456497:519-21489:flowmailer Content-Type: text/plain; charset="utf-8" From: Alexander Sverdlin The FEC/ENET controller can flush frames stuck at the head of the RX FIFO when their destination ring has no empty buffer descriptor, instead of letting them block the FIFO. This is controlled per RX queue through the RX_FLUSHn bits of the QOS Scheme register (FEC_QOS_SCHEME). Parse the new fsl,rx-flush-queues property, build the RX flush mask and program it in fec_enet_enable_ring(). Erratum ERR050395 (e.g. i.MX8QXP) can cause an RX path lock-up when flushing is enabled on more than one queue at a time. Rather than encoding that limitation in the binding, enforce it in the driver: reject a configuration that enables flushing on multiple queues unless the controller advertises FEC_QUIRK_HAS_MULTI_RX_FLUSH, which future parts with the erratum fixed can set. Signed-off-by: Alexander Sverdlin --- drivers/net/ethernet/freescale/fec.h | 14 ++++++++++ drivers/net/ethernet/freescale/fec_main.c | 34 +++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/drivers/net/ethernet/freescale/fec.h b/drivers/net/ethernet/fr= eescale/fec.h index 7176803146f3d..4af3ae286895f 100644 --- a/drivers/net/ethernet/freescale/fec.h +++ b/drivers/net/ethernet/freescale/fec.h @@ -186,6 +186,7 @@ #define FEC_RCMR_2 0xfff #define FEC_DMA_CFG_1 0xfff #define FEC_DMA_CFG_2 0xfff +#define FEC_QOS_SCHEME 0xfff #define FEC_TXIC0 0xfff #define FEC_TXIC1 0xfff #define FEC_TXIC2 0xfff @@ -322,6 +323,10 @@ struct bufdesc_ex { #define RCMR_CMP(X) (((X) =3D=3D 1) ? RCMR_CMP_1 : RCMR_CMP_2) #define FEC_TX_BD_FTYPE(X) (((X) & 0xf) << 20) =20 +/* FEC_QOS_SCHEME bits */ +#define QOS_RX_FLUSH(X) (1 << (3 + (X))) /* RX_FLUSHn, n =3D 0, 1, 2 */ +#define QOS_RX_FLUSH_MASK (QOS_RX_FLUSH(0) | QOS_RX_FLUSH(1) | QOS_RX_FLUS= H(2)) + /* The number of Tx and Rx buffers. These are allocated from the page * pool. The code may assume these are power of two, so it is best * to keep them that size. @@ -499,6 +504,12 @@ struct bufdesc_ex { /* Jumbo Frame support */ #define FEC_QUIRK_JUMBO_FRAME BIT(25) =20 +/* Receive flushing (QOS Scheme register RX_FLUSHn) may be enabled on more= than + * one RX queue at a time. Parts without this quirk are subject to erratum + * ERR050395 and must limit RX flushing to a single queue. + */ +#define FEC_QUIRK_HAS_MULTI_RX_FLUSH BIT(24) + struct bufdesc_prop { int qid; /* Address of Rx and Tx buffers */ @@ -604,6 +615,9 @@ struct fec_enet_private { unsigned int num_tx_queues; unsigned int num_rx_queues; =20 + /* Bitmask of RX queues with receive flushing enabled */ + u32 rx_flush_mask; + struct fec_enet_priv_tx_q *tx_queue[FEC_ENET_MAX_TX_QS]; struct fec_enet_priv_rx_q *rx_queue[FEC_ENET_MAX_RX_QS]; =20 diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethern= et/freescale/fec_main.c index ced4dbf8cd90f..a4fe8423630b5 100644 --- a/drivers/net/ethernet/freescale/fec_main.c +++ b/drivers/net/ethernet/freescale/fec_main.c @@ -1090,6 +1090,15 @@ static void fec_enet_enable_ring(struct net_device *= ndev) fep->hwp + FEC_RCMR(i)); } =20 + /* Enable receive flushing for the selected queues */ + if (fep->rx_flush_mask) { + u32 val =3D readl(fep->hwp + FEC_QOS_SCHEME); + + val &=3D ~QOS_RX_FLUSH_MASK; + val |=3D fep->rx_flush_mask; + writel(val, fep->hwp + FEC_QOS_SCHEME); + } + for (i =3D 0; i < fep->num_tx_queues; i++) { txq =3D fep->tx_queue[i]; writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); @@ -5239,6 +5248,31 @@ fec_probe(struct platform_device *pdev) fep->num_rx_queues =3D num_rx_qs; fep->num_tx_queues =3D num_tx_qs; =20 + /* Enable receive flushing on the requested queues. Erratum ERR050395 + * restricts flushing to a single queue; only accept more than one queue + * on controllers known to have the erratum fixed. + */ + for (i =3D 0; i < of_property_count_u32_elems(np, "fsl,rx-flush-queues");= i++) { + u32 q; + + if (of_property_read_u32_index(np, "fsl,rx-flush-queues", i, &q)) + break; + if (q >=3D num_rx_qs) { + dev_warn(&pdev->dev, + "fsl,rx-flush-queues: queue %u exceeds num-rx-queues, ignoring\n", + q); + continue; + } + fep->rx_flush_mask |=3D QOS_RX_FLUSH(q); + } + if (hweight32(fep->rx_flush_mask) > 1 && + !(fep->quirks & FEC_QUIRK_HAS_MULTI_RX_FLUSH)) { + dev_err(&pdev->dev, + "fsl,rx-flush-queues: RX flush on multiple queues not supported\n"); + ret =3D -EINVAL; + goto failed_ioremap; + } + /* default enable pause frame auto negotiation */ if (fep->quirks & FEC_QUIRK_HAS_GBIT) fep->pause_flag |=3D FEC_PAUSE_FLAG_AUTONEG; --=20 2.55.0